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FAILED: patch "[PATCH] riscv: topology: fix default topology reporting" failed to apply to 5.4-stable tree

PATCH [email protected] 1 participant 1 message Oct 16, 2022

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The patch below does not apply to the 5.4-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.

Possible dependencies:

fbd92809997a ("riscv: topology: fix default topology reporting")
4f0e8eef772e ("riscv: Add numa support for riscv64 platform")
cbd34f4bb37d ("riscv: Separate memory init from paging init")
00ab027a3b82 ("RISC-V: Add kernel image sections to the resource tree")
270315b8235e ("Merge tag 'riscv-for-linus-5.10-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux")

thanks,

greg k-h

------------------ original commit in Linus's tree ------------------

From fbd92809997a391f28075f1c8b5ee314c225557c Mon Sep 17 00:00:00 2001
From: Conor Dooley <[email protected]>
Date: Fri, 15 Jul 2022 18:51:56 +0100
Subject: [PATCH] riscv: topology: fix default topology reporting

RISC-V has no sane defaults to fall back on where there is no cpu-map in the devicetree.
Without sane defaults, the package, core and thread IDs are all set to -1. This causes user-visible inaccuracies for tools like hwloc/lstopo which rely on the sysfs cpu topology files to detect a system's topology.

On a PolarFire SoC, which should have 4 harts with a thread each, lstopo currently reports:

Machine (793MB total)
Package L#0

    NUMANode L#0 (P#0 793MB)
    Core L#0
      L1d L#0 (32KB) + L1i L#0 (32KB) + PU L#0 (P#0)
      L1d L#1 (32KB) + L1i L#1 (32KB) + PU L#1 (P#1)
      L1d L#2 (32KB) + L1i L#2 (32KB) + PU L#2 (P#2)
      L1d L#3 (32KB) + L1i L#3 (32KB) + PU L#3 (P#3)

Adding calls to store_cpu_topology() in {boot,smp} hart bringup code results in the correct topolgy being reported:

Machine (793MB total)
Package L#0

    NUMANode L#0 (P#0 793MB)
    L1d L#0 (32KB) + L1i L#0 (32KB) + Core L#0 + PU L#0 (P#0)
    L1d L#1 (32KB) + L1i L#1 (32KB) + Core L#1 + PU L#1 (P#1)
    L1d L#2 (32KB) + L1i L#2 (32KB) + Core L#2 + PU L#2 (P#2)
    L1d L#3 (32KB) + L1i L#3 (32KB) + Core L#3 + PU L#3 (P#3)
CC [email protected] # 456797da792f: arm64: topology: move store_cpu_topology() to shared code
Fixes 03f11f03dbfe ("RISC-V: Parse cpu topology during boot.")
Reported-by Brice Goglin <[email protected]>
Link https://github.com/open-mpi/hwloc/issues/536
Reviewed-by Sudeep Holla <[email protected]>
Reviewed-by Atish Patra <[email protected]>
Signed-off-by Conor Dooley <[email protected]>
arch/riscv/Kconfig +1 -1
index ed66c31e4655..d557cc50295d 100644
@@ -52,7 +52,7 @@ config RISCV
 	select COMMON_CLK
 	select CPU_PM if CPU_IDLE
 	select EDAC_SUPPORT
-	select GENERIC_ARCH_TOPOLOGY if SMP
+	select GENERIC_ARCH_TOPOLOGY
 	select GENERIC_ATOMIC64 if !64BIT
 	select GENERIC_CLOCKEVENTS_BROADCAST if SMP
 	select GENERIC_EARLY_IOREMAP
arch/riscv/kernel/smpboot.c +2 -1
index a752c7b41683..3373df413c88 100644
@@ -49,6 +49,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
 	unsigned int curr_cpuid;
 
 	curr_cpuid = smp_processor_id();
+	store_cpu_topology(curr_cpuid);
 	numa_store_cpu_info(curr_cpuid);
 	numa_add_cpu(curr_cpuid);
 

@@ -162,9 +163,9 @@ asmlinkage __visible void smp_callin(void)
 	mmgrab(mm);
 	current->active_mm = mm;
 
+	store_cpu_topology(curr_cpuid);
 	notify_cpu_starting(curr_cpuid);
 	numa_add_cpu(curr_cpuid);
-	update_siblings_masks(curr_cpuid);
 	set_cpu_online(curr_cpuid, 1);
 
 	/*