FAILED: patch "[PATCH] arm64: errata: Add Cortex-A55 to the repeat tlbi list" failed to apply to 5.10-stable tree
Subsystems (3)
[email protected]
maintainerThe patch below does not apply to the 5.10-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.
Possible dependencies:
171df58028bf ("arm64: errata: Add Cortex-A55 to the repeat tlbi list") 39fdb65f52e9 ("arm64: errata: Add Cortex-A510 to the repeat tlbi list") 1dd498e5e26a ("KVM: arm64: Workaround Cortex-A510's single-step and PAC trap errata") 297ae1eb23b0 ("arm64: cpufeature: List early Cortex-A510 parts as having broken dbm") 708e8af4924e ("arm64: errata: Add detection for TRBE trace data corruption") 3bd94a8759de ("arm64: errata: Add detection for TRBE invalid prohibited states") 607a9afaae09 ("arm64: errata: Add detection for TRBE ignored system register writes") 83bb2c1a01d7 ("KVM: arm64: Save PSTATE early on exit")d7e0a795bf37 ("Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm")
thanks,
greg k-h
------------------ original commit in Linus's tree ------------------
From 171df58028bf4649460fb146a56a58dcb0c8f75a Mon Sep 17 00:00:00 2001
From: James Morse <[email protected]>
Date: Fri, 30 Sep 2022 14:19:59 +0100
Subject: [PATCH] arm64: errata: Add Cortex-A55 to the repeat tlbi list
Cortex-A55 is affected by an erratum where in rare circumstances the CPUs may not handle a race between a break-before-make sequence on one CPU, and another CPU accessing the same page. This could allow a store to a page that has been unmapped.
Work around this by adding the affected CPUs to the list that needs TLB sequences to be done twice.
Documentation/arm64/silicon-errata.rst +2 -0
@@ -76,6 +76,8 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A55 | #1530923 | ARM64_ERRATUM_1530923 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-A55 | #2441007 | ARM64_ERRATUM_2441007 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 | +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A57 | #852523 | N/A |
arch/arm64/Kconfig +17 -0
@@ -634,6 +634,23 @@ config ARM64_ERRATUM_1530923 config ARM64_WORKAROUND_REPEAT_TLBI bool +config ARM64_ERRATUM_2441007 + bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI" + default y + select ARM64_WORKAROUND_REPEAT_TLBI + help + This option adds a workaround for ARM Cortex-A55 erratum #2441007. + + Under very rare circumstances, affected Cortex-A55 CPUs + may not handle a race between a break-before-make sequence on one + CPU, and another CPU accessing the same page. This could allow a + store to a page that has been unmapped. + + Work around this by adding the affected CPUs to the list that needs + TLB sequences to be done twice. + + If unsure, say Y. + config ARM64_ERRATUM_1286807 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation" default y
arch/arm64/kernel/cpu_errata.c +5 -0
@@ -230,6 +230,11 @@ static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = { ERRATA_MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xe), },#endif +#ifdef CONFIG_ARM64_ERRATUM_2441007 + { + ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), + }, +#endif #ifdef CONFIG_ARM64_ERRATUM_2441009 {/* Cortex-A510 r0p0 -> r1p1. Fixed in r1p2 */