Patch "arm64/kexec: Test page size support with new TGRAN range values" has been added to the 5.10-stable tree
[email protected]
AppliedThis is a note to let you know that I've just added the patch titled
arm64/kexec: Test page size support with new TGRAN range values
to the 5.10-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
arm64-kexec-test-page-size-support-with-new-tgran-range-values.patch
and it can be found in the queue-5.10 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
From 79d82cbcbb3d2a56c009ad6a6df92c5dee061dad Mon Sep 17 00:00:00 2001
From: Anshuman Khandual <[email protected]>
Date: Wed, 14 Jul 2021 10:16:15 +0530
Subject: arm64/kexec: Test page size support with new TGRAN range values
From: Anshuman Khandual <[email protected]>
commit 79d82cbcbb3d2a56c009ad6a6df92c5dee061dad upstream.
The commit 26f55386f964 ("arm64/mm: Fix __enable_mmu() for new TGRAN range values") had already switched into testing ID_AA64MMFR0_TGRAN range values. This just changes system_supports_[4|16|64]kb_granule() helpers to perform similar range tests as well. While here, it standardizes page size specific supported min and max TGRAN values.
--- arch/arm64/include/asm/cpufeature.h | 9 ++++++--- arch/arm64/include/asm/sysreg.h | 28 ++++++++++++++++------------ 2 files changed, 22 insertions(+), 15 deletions(-)
arch/arm64/include/asm/cpufeature.h +6 -3
@@ -648,7 +648,8 @@ static inline bool system_supports_4kb_g val =cpuid_feature_extract_unsigned_field (mmfr0,ID_AA64MMFR0_TGRAN4_SHIFT ); -return val ==ID_AA64MMFR0_TGRAN4_SUPPORTED ; +return (val >=ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN ) && + (val <=ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX ); }static inline bool system_supports_64kb_granule (void )
@@ -660,7 +661,8 @@ static inline bool system_supports_64kb_ val =cpuid_feature_extract_unsigned_field (mmfr0,ID_AA64MMFR0_TGRAN64_SHIFT ); -return val ==ID_AA64MMFR0_TGRAN64_SUPPORTED ; +return (val >=ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN ) && + (val <=ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX ); }static inline bool system_supports_16kb_granule (void )
@@ -672,7 +674,8 @@ static inline bool system_supports_16kb_ val =cpuid_feature_extract_unsigned_field (mmfr0,ID_AA64MMFR0_TGRAN16_SHIFT ); -return val ==ID_AA64MMFR0_TGRAN16_SUPPORTED ; +return (val >=ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN ) && + (val <=ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX ); }static inline bool system_supports_mixed_endian_el0 (void )
arch/arm64/include/asm/sysreg.h +16 -12
@@ -786,12 +786,16 @@#define ID_AA64MMFR0_ASID_SHIFT 4#define ID_AA64MMFR0_PARANGE_SHIFT 0 -#define ID_AA64MMFR0_TGRAN4_NI 0xf -#define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0 -#define ID_AA64MMFR0_TGRAN64_NI 0xf -#define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0 -#define ID_AA64MMFR0_TGRAN16_NI 0x0 -#define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1 +#define ID_AA64MMFR0_TGRAN4_NI 0xf +#define ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN 0x0 +#define ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX 0x7 +#define ID_AA64MMFR0_TGRAN64_NI 0xf +#define ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN 0x0 +#define ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX 0x7 +#define ID_AA64MMFR0_TGRAN16_NI 0x0 +#define ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN 0x1 +#define ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX 0xf +#define ID_AA64MMFR0_PARANGE_48 0x5#define ID_AA64MMFR0_PARANGE_52 0x6
@@ -961,16 +965,16 @@#if defined(CONFIG_ARM64_4K_PAGES )#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT -#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_TGRAN4_SUPPORTED -#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX 0x7 +#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN +#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX#elif defined(CONFIG_ARM64_16K_PAGES )#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT -#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_TGRAN16_SUPPORTED -#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX 0xF +#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN +#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX#elif defined(CONFIG_ARM64_64K_PAGES )#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT -#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_TGRAN64_SUPPORTED -#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX 0x7 +#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN +#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX#endif #define MVFR2_FPMISC_SHIFT 4
Patches currently in stable-queue which might be from [email protected] are
queue-5.10/arm64-kexec-test-page-size-support-with-new-tgran-range-values.patch queue-5.10/arm64-mm-fix-__enable_mmu-for-new-tgran-range-values.patch
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