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FAILED: patch "[PATCH] drm/amd/display: Limit dcn32 to 1950Mhz display clock" failed to apply to 6.0-stable tree

PATCH [email protected] 1 participant 1 message Nov 8, 2022

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Stable branch DRM drivers Radeon and amdgpu DRM drivers AMD display core
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The patch below does not apply to the 6.0-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.

Possible dependencies:

e59843c4cdd6 ("drm/amd/display: Limit dcn32 to 1950Mhz display clock") d6170e418d1d ("drm/amd/display: Acquire FCLK DPM levels on DCN32")

thanks,

greg k-h

------------------ original commit in Linus's tree ------------------

From e59843c4cdd68a369591630088171eeacce9859f Mon Sep 17 00:00:00 2001
From: Jun Lei <[email protected]>
Date: Thu, 20 Oct 2022 11:46:44 -0400
Subject: [PATCH] drm/amd/display: Limit dcn32 to 1950Mhz display clock

[why]
Hardware team recommends we limit dispclock to 1950Mhz for all DCN3.2.x

[how]
Limit to 1950 when initializing clocks.

Tested-by Mark Broadworth <[email protected]>
Reviewed-by Alvin Lee <[email protected]>
Acked-by Rodrigo Siqueira <[email protected]>
Signed-off-by Jun Lei <[email protected]>
Signed-off-by Alex Deucher <[email protected]>
Cc [email protected] # 6.0.x
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +4 -4
index 1c612ccf1944..fd0313468fdb 100644
@@ -157,6 +157,7 @@ void dcn32_init_clocks(struct clk_mgr *clk_mgr_base)
 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 	unsigned int num_levels;
 	struct clk_limit_num_entries *num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk;
+	unsigned int i;
 
 	memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks));
 	clk_mgr_base->clks.p_state_change_support = true;

@@ -205,18 +206,17 @@ void dcn32_init_clocks(struct clk_mgr *clk_mgr_base)
 		clk_mgr->dpm_present = true;
 
 	if (clk_mgr_base->ctx->dc->debug.min_disp_clk_khz) {
-		unsigned int i;
-
 		for (i = 0; i < num_levels; i++)
 			if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz
 					< khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz))
 				clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz
 					= khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz);
 	}
+	for (i = 0; i < num_levels; i++)
+		if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz > 1950)
+			clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz = 1950;
 
 	if (clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz) {
-		unsigned int i;
-
 		for (i = 0; i < num_levels; i++)
 			if (clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz
 					< khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz))