FAILED: patch "[PATCH] drm/amd/display: Set memclk levels to be at least 1 for dcn32" failed to apply to 6.0-stable tree

The patch below does not apply to the 6.0-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.

Possible dependencies:

6cb5cec16c38 ("drm/amd/display: Set memclk levels to be at least 1 for dcn32") d6170e418d1d ("drm/amd/display: Acquire FCLK DPM levels on DCN32")

thanks,

greg k-h

------------------ original commit in Linus's tree ------------------

From 6cb5cec16c380be4cf9776a8c23b72e9fe742fd1 Mon Sep 17 00:00:00 2001
From: Dillon Varone <[email protected]>
Date: Thu, 20 Oct 2022 11:46:48 -0400
Subject: [PATCH] drm/amd/display: Set memclk levels to be at least 1 for dcn32

[Why]
Cannot report 0 memclk levels even when SMU does not provide any.

[How]
When memclk levels reported by SMU is 0, set levels to 1.

index fd0313468fdb..6f77d8e538ab 100644
@@ -669,6 +669,9 @@ static void dcn32_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)
 			&clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz,
 			&num_entries_per_clk->num_memclk_levels);
 
+	/* memclk must have at least one level */
+	num_entries_per_clk->num_memclk_levels = num_entries_per_clk->num_memclk_levels ? num_entries_per_clk->num_memclk_levels : 1;
+
 	dcn32_init_single_clock(clk_mgr, PPCLK_FCLK,
 			&clk_mgr_base->bw_params->clk_table.entries[0].fclk_mhz,
 			&num_entries_per_clk->num_fclk_levels);