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FAILED: patch "[PATCH] drm/amdgpu: fix mmhub register base coding error" failed to apply to 5.15-stable tree

PATCH [email protected] 1 participant 1 message Jan 4, 2023

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Stable branch DRM drivers Radeon and amdgpu DRM drivers
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The patch below does not apply to the 5.15-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.

Possible dependencies:

347fafe0eb46 ("drm/amdgpu: fix mmhub register base coding error") 10c4ad3ae025 ("drm/amdgpu: add mmhub v3_0_1 ip block")
f40fc1916ce8 ("drm/amdgpu: split mmhub v3_0_2 callbacks from mmhub v3_0") 9fa57397d933 ("drm/amdgpu: add mmhub v3_0_2 ip callback functions") 1c2014da7785 ("drm/amdgpu: add gmc v11_0 ip block (v3)")
98a0f8687e31 ("drm/amdgpu: add mmhub v3_0 ip block")
2279b4e5967f ("drm/amdgpu: add gfxhub v3_0 ip block")
8b0fb0e967c1 ("drm/amdgpu: Modify gfx block to fit for the unified ras block data and ops") 9d0cb2c31891 ("drm/amdgpu/gfx9.0: convert to IP version checking") 640ae42efb82 ("drm/amdgpu: Updated RAS infrastructure")
3771449bc80f ("drm/amdgpu: Update RAS trigger error block support") a0a2f7bb2209 ("drm/amd/amdgpu: add mpio to ras block")

thanks,

greg k-h

------------------ original commit in Linus's tree ------------------

From 347fafe0eb46df941965c355c77ce480e4d49f1f Mon Sep 17 00:00:00 2001
From: Yang Wang <[email protected]>
Date: Mon, 5 Dec 2022 21:16:26 +0800
Subject: [PATCH] drm/amdgpu: fix mmhub register base coding error
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

fix MMHUB register base coding error.

Fixes ec6837591f992 ("drm/amdgpu/gmc10: program the smallK fragment size")
Signed-off-by Yang Wang <[email protected]>
Reviewed-by Hawking Zhang <[email protected]>
Reviewed-by Christian König <[email protected]>
Signed-off-by Alex Deucher <[email protected]>
Cc [email protected]
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c +1 -1
index 998b5d17b271..0e664d0cc8d5 100644
@@ -319,7 +319,7 @@ static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
 
 	tmp = mmMMVM_L2_CNTL5_DEFAULT;
 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
-	WREG32_SOC15(GC, 0, mmMMVM_L2_CNTL5, tmp);
+	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL5, tmp);
 }
 
 static void mmhub_v2_0_enable_system_domain(struct amdgpu_device *adev)
drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c +1 -1
index 1b027d069ab4..4638ea7c2eec 100644
@@ -243,7 +243,7 @@ static void mmhub_v2_3_init_cache_regs(struct amdgpu_device *adev)
 
 	tmp = mmMMVM_L2_CNTL5_DEFAULT;
 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
-	WREG32_SOC15(GC, 0, mmMMVM_L2_CNTL5, tmp);
+	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL5, tmp);
 }
 
 static void mmhub_v2_3_enable_system_domain(struct amdgpu_device *adev)
drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c +1 -1
index a1d26c4d80b8..16cc82215e2e 100644
@@ -275,7 +275,7 @@ static void mmhub_v3_0_init_cache_regs(struct amdgpu_device *adev)
 
 	tmp = regMMVM_L2_CNTL5_DEFAULT;
 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
-	WREG32_SOC15(GC, 0, regMMVM_L2_CNTL5, tmp);
+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL5, tmp);
 }
 
 static void mmhub_v3_0_enable_system_domain(struct amdgpu_device *adev)
drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c +1 -1
index e8058edc1d10..6bdf2ef0298d 100644
@@ -269,7 +269,7 @@ static void mmhub_v3_0_1_init_cache_regs(struct amdgpu_device *adev)
 
 	tmp = regMMVM_L2_CNTL5_DEFAULT;
 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
-	WREG32_SOC15(GC, 0, regMMVM_L2_CNTL5, tmp);
+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL5, tmp);
 }
 
 static void mmhub_v3_0_1_enable_system_domain(struct amdgpu_device *adev)
drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c +1 -1
index 770be0a8f7ce..45465acaa943 100644
@@ -268,7 +268,7 @@ static void mmhub_v3_0_2_init_cache_regs(struct amdgpu_device *adev)
 
 	tmp = regMMVM_L2_CNTL5_DEFAULT;
 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
-	WREG32_SOC15(GC, 0, regMMVM_L2_CNTL5, tmp);
+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL5, tmp);
 }
 
 static void mmhub_v3_0_2_enable_system_domain(struct amdgpu_device *adev)