use stdatomic API

index 40ea9d2..70bba6c 100644
@@ -1918,9 +1918,9 @@ int mlx5_txpp_map_hca_bar(struct rte_eth_dev *dev)
 		return -ENOTSUP;
 	}
 	/* Check there is no concurrent mapping in other thread. */
-	if (!__atomic_compare_exchange_n(&ppriv->hca_bar, &expected,
-					 base, false,
-					 __ATOMIC_RELAXED, __ATOMIC_RELAXED))
+	if (!rte_atomic_compare_exchange_strong_explicit(&ppriv->hca_bar, &expected,
+					 base,
+					 rte_memory_order_relaxed, rte_memory_order_relaxed))
 		rte_mem_unmap(base, MLX5_ST_SZ_BYTES(initial_seg));
 	return 0;
 }

index b54f3cc..63da8f4 100644
@@ -1117,7 +1117,7 @@
 		return 0;
 	}
 	/* Only need to check refcnt, 0 after "sh" is allocated. */
-	if (!!(__atomic_fetch_add(&sh->self_lb.refcnt, 1, __ATOMIC_RELAXED))) {
+	if (!!(rte_atomic_fetch_add_explicit(&sh->self_lb.refcnt, 1, rte_memory_order_relaxed))) {
 		MLX5_ASSERT(sh->self_lb.ibv_cq && sh->self_lb.qp);
 		priv->lb_used = 1;
 		return 0;

@@ -1163,7 +1163,7 @@
 		claim_zero(mlx5_glue->destroy_cq(sh->self_lb.ibv_cq));
 		sh->self_lb.ibv_cq = NULL;
 	}
-	__atomic_fetch_sub(&sh->self_lb.refcnt, 1, __ATOMIC_RELAXED);
+	rte_atomic_fetch_sub_explicit(&sh->self_lb.refcnt, 1, rte_memory_order_relaxed);
 	return -rte_errno;
 #else
 	RTE_SET_USED(dev);

@@ -1186,8 +1186,9 @@
 
 	if (!priv->lb_used)
 		return;
-	MLX5_ASSERT(__atomic_load_n(&sh->self_lb.refcnt, __ATOMIC_RELAXED));
-	if (!(__atomic_fetch_sub(&sh->self_lb.refcnt, 1, __ATOMIC_RELAXED) - 1)) {
+	MLX5_ASSERT(rte_atomic_load_explicit(&sh->self_lb.refcnt, rte_memory_order_relaxed));
+	if (!(rte_atomic_fetch_sub_explicit(&sh->self_lb.refcnt, 1,
+	    rte_memory_order_relaxed) - 1)) {
 		if (sh->self_lb.qp) {
 			claim_zero(mlx5_glue->destroy_qp(sh->self_lb.qp));
 			sh->self_lb.qp = NULL;

index d1a6382..2ff94db 100644
@@ -855,8 +855,8 @@
 		ct_pool = mng->pools[idx];
 		for (i = 0; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
 			ct = &ct_pool->actions[i];
-			val = __atomic_fetch_sub(&ct->refcnt, 1,
-						 __ATOMIC_RELAXED);
+			val = rte_atomic_fetch_sub_explicit(&ct->refcnt, 1,
+						 rte_memory_order_relaxed);
 			MLX5_ASSERT(val == 1);
 			if (val > 1)
 				cnt++;

@@ -1082,7 +1082,8 @@
 		DRV_LOG(ERR, "Dynamic flex parser is not supported on HWS");
 		return -ENOTSUP;
 	}
-	if (__atomic_fetch_add(&priv->sh->srh_flex_parser.refcnt, 1, __ATOMIC_RELAXED) + 1 > 1)
+	if (rte_atomic_fetch_add_explicit(&priv->sh->srh_flex_parser.refcnt, 1,
+	    rte_memory_order_relaxed) + 1 > 1)
 		return 0;
 	priv->sh->srh_flex_parser.flex.devx_fp = mlx5_malloc(MLX5_MEM_ZERO,
 			sizeof(struct mlx5_flex_parser_devx), 0, SOCKET_ID_ANY);

@@ -1173,7 +1174,7 @@
 	struct mlx5_priv *priv = dev->data->dev_private;
 	struct mlx5_internal_flex_parser_profile *fp = &priv->sh->srh_flex_parser;
 
-	if (__atomic_fetch_sub(&fp->refcnt, 1, __ATOMIC_RELAXED) - 1)
+	if (rte_atomic_fetch_sub_explicit(&fp->refcnt, 1, rte_memory_order_relaxed) - 1)
 		return;
 	mlx5_devx_cmd_destroy(fp->flex.devx_fp->devx_obj);
 	mlx5_free(fp->flex.devx_fp);

207 lines not on this page · raw message

index f31fdfb..1954975 100644
@@ -4623,8 +4623,8 @@ struct mlx5_translated_action_handle {
 			shared_rss = mlx5_ipool_get
 				(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
 									   idx);
-			__atomic_fetch_add(&shared_rss->refcnt, 1,
-					   __ATOMIC_RELAXED);
+			rte_atomic_fetch_add_explicit(&shared_rss->refcnt, 1,
+					   rte_memory_order_relaxed);
 			return idx;
 		default:
 			break;

@@ -7459,7 +7459,7 @@ struct mlx5_list_entry *
 	if (tunnel) {
 		flow->tunnel = 1;
 		flow->tunnel_id = tunnel->tunnel_id;
-		__atomic_fetch_add(&tunnel->refctn, 1, __ATOMIC_RELAXED);
+		rte_atomic_fetch_add_explicit(&tunnel->refctn, 1, rte_memory_order_relaxed);
 		mlx5_free(default_miss_ctx.queue);
 	}
 	mlx5_flow_pop_thread_workspace();

@@ -7470,10 +7470,10 @@ struct mlx5_list_entry *
 	flow_mreg_del_copy_action(dev, flow);
 	flow_drv_destroy(dev, flow);
 	if (rss_desc->shared_rss)
-		__atomic_fetch_sub(&((struct mlx5_shared_action_rss *)
+		rte_atomic_fetch_sub_explicit(&((struct mlx5_shared_action_rss *)
 			mlx5_ipool_get
 			(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
-			rss_desc->shared_rss))->refcnt, 1, __ATOMIC_RELAXED);
+			rss_desc->shared_rss))->refcnt, 1, rte_memory_order_relaxed);
 	mlx5_ipool_free(priv->flows[type], idx);
 	rte_errno = ret; /* Restore rte_errno. */
 	ret = rte_errno;

@@ -7976,7 +7976,8 @@ struct rte_flow *
 
 		tunnel = mlx5_find_tunnel_id(dev, flow->tunnel_id);
 		RTE_VERIFY(tunnel);
-		if (!(__atomic_fetch_sub(&tunnel->refctn, 1, __ATOMIC_RELAXED) - 1))
+		if (!(rte_atomic_fetch_sub_explicit(&tunnel->refctn, 1,
+		    rte_memory_order_relaxed) - 1))
 			mlx5_flow_tunnel_free(dev, tunnel);
 	}
 	flow_mreg_del_copy_action(dev, flow);

@@ -9456,7 +9457,7 @@ struct mlx5_flow_workspace*
 {
 	uint32_t pools_n, us;
 
-	pools_n = __atomic_load_n(&sh->sws_cmng.n_valid, __ATOMIC_RELAXED);
+	pools_n = rte_atomic_load_explicit(&sh->sws_cmng.n_valid, rte_memory_order_relaxed);
 	us = MLX5_POOL_QUERY_FREQ_US / pools_n;
 	DRV_LOG(DEBUG, "Set alarm for %u pools each %u us", pools_n, us);
 	if (rte_eal_alarm_set(us, mlx5_flow_query_alarm, sh)) {

@@ -9558,17 +9559,17 @@ struct mlx5_flow_workspace*
 	for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
 		cnt = MLX5_POOL_GET_CNT(pool, i);
 		age_param = MLX5_CNT_TO_AGE(cnt);
-		if (__atomic_load_n(&age_param->state,
-				    __ATOMIC_RELAXED) != AGE_CANDIDATE)
+		if (rte_atomic_load_explicit(&age_param->state,
+				    rte_memory_order_relaxed) != AGE_CANDIDATE)
 			continue;
 		if (cur->data[i].hits != prev->data[i].hits) {
-			__atomic_store_n(&age_param->sec_since_last_hit, 0,
-					 __ATOMIC_RELAXED);
+			rte_atomic_store_explicit(&age_param->sec_since_last_hit, 0,
+					 rte_memory_order_relaxed);
 			continue;
 		}
-		if (__atomic_fetch_add(&age_param->sec_since_last_hit,
+		if (rte_atomic_fetch_add_explicit(&age_param->sec_since_last_hit,
 				       time_delta,
-				       __ATOMIC_RELAXED) + time_delta <= age_param->timeout)
+				       rte_memory_order_relaxed) + time_delta <= age_param->timeout)
 			continue;
 		/**
 		 * Hold the lock first, or if between the

@@ -9579,10 +9580,10 @@ struct mlx5_flow_workspace*
 		priv = rte_eth_devices[age_param->port_id].data->dev_private;
 		age_info = GET_PORT_AGE_INFO(priv);
 		rte_spinlock_lock(&age_info->aged_sl);
-		if (__atomic_compare_exchange_n(&age_param->state, &expected,
-						AGE_TMOUT, false,
-						__ATOMIC_RELAXED,
-						__ATOMIC_RELAXED)) {
+		if (rte_atomic_compare_exchange_strong_explicit(&age_param->state, &expected,
+						AGE_TMOUT,
+						rte_memory_order_relaxed,
+						rte_memory_order_relaxed)) {
 			TAILQ_INSERT_TAIL(&age_info->aged_counters, cnt, next);
 			MLX5_AGE_SET(age_info, MLX5_AGE_EVENT_NEW);
 		}

@@ -11407,7 +11408,7 @@ struct tunnel_db_element_release_ctx {
 {
 	struct tunnel_db_element_release_ctx *ctx = x;
 	ctx->ret = 0;
-	if (!(__atomic_fetch_sub(&tunnel->refctn, 1, __ATOMIC_RELAXED) - 1))
+	if (!(rte_atomic_fetch_sub_explicit(&tunnel->refctn, 1, rte_memory_order_relaxed) - 1))
 		mlx5_flow_tunnel_free(dev, tunnel);
 }
 

index 34b5e0f..edfa76f 100644
@@ -1049,7 +1049,7 @@ struct mlx5_flow_tunnel {
 	LIST_ENTRY(mlx5_flow_tunnel) chain;
 	struct rte_flow_tunnel app_tunnel;	/** app tunnel copy */
 	uint32_t tunnel_id;			/** unique tunnel ID */
-	uint32_t refctn;
+	RTE_ATOMIC(uint32_t) refctn;
 	struct rte_flow_action action;
 	struct rte_flow_item item;
 	struct mlx5_hlist *groups;		/** tunnel groups */

@@ -1470,7 +1470,7 @@ struct rte_flow_pattern_template {
 	struct mlx5dr_match_template *mt; /* mlx5 match template. */
 	uint64_t item_flags; /* Item layer flags. */
 	uint64_t orig_item_nb; /* Number of pattern items provided by the user (with END item). */
-	uint32_t refcnt;  /* Reference counter. */
+	RTE_ATOMIC(uint32_t) refcnt;  /* Reference counter. */
 	/*
 	 * If true, then rule pattern should be prepended with
 	 * represented_port pattern item.

@@ -1502,7 +1502,7 @@ struct rte_flow_actions_template {
 	uint16_t reformat_off; /* Offset of DR reformat action. */
 	uint16_t mhdr_off; /* Offset of DR modify header action. */
 	uint16_t recom_off;  /* Offset of DR IPv6 routing push remove action. */
-	uint32_t refcnt; /* Reference counter. */
+	RTE_ATOMIC(uint32_t) refcnt; /* Reference counter. */
 	uint8_t flex_item; /* flex item index. */
 };
 

@@ -1855,7 +1855,7 @@ struct rte_flow_template_table {
 /* Shared RSS action structure */
 struct mlx5_shared_action_rss {
 	ILIST_ENTRY(uint32_t)next; /**< Index to the next RSS structure. */
-	uint32_t refcnt; /**< Atomically accessed refcnt. */
+	RTE_ATOMIC(uint32_t) refcnt; /**< Atomically accessed refcnt. */
 	struct rte_flow_action_rss origin; /**< Original rte RSS action. */
 	uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
 	struct mlx5_ind_table_obj *ind_tbl;

120 lines not on this page · raw message

307 lines not on this page · raw message

index 4ae03a2..8a02247 100644
@@ -86,7 +86,7 @@
 			MLX5_ASSERT(!item->refcnt);
 			MLX5_ASSERT(!item->devx_fp);
 			item->devx_fp = NULL;
-			__atomic_store_n(&item->refcnt, 0, __ATOMIC_RELEASE);
+			rte_atomic_store_explicit(&item->refcnt, 0, rte_memory_order_release);
 			priv->flex_item_map |= 1u << idx;
 		}
 	}

@@ -107,7 +107,7 @@
 		MLX5_ASSERT(!item->refcnt);
 		MLX5_ASSERT(!item->devx_fp);
 		item->devx_fp = NULL;
-		__atomic_store_n(&item->refcnt, 0, __ATOMIC_RELEASE);
+		rte_atomic_store_explicit(&item->refcnt, 0, rte_memory_order_release);
 		priv->flex_item_map &= ~(1u << idx);
 		rte_spinlock_unlock(&priv->flex_item_sl);
 	}

@@ -379,7 +379,7 @@
 		return ret;
 	}
 	if (acquire)
-		__atomic_fetch_add(&flex->refcnt, 1, __ATOMIC_RELEASE);
+		rte_atomic_fetch_add_explicit(&flex->refcnt, 1, rte_memory_order_release);
 	return ret;
 }
 

@@ -414,7 +414,7 @@
 		rte_errno = -EINVAL;
 		return -EINVAL;
 	}
-	__atomic_fetch_sub(&flex->refcnt, 1, __ATOMIC_RELEASE);
+	rte_atomic_fetch_sub_explicit(&flex->refcnt, 1, rte_memory_order_release);
 	return 0;
 }
 

@@ -1337,7 +1337,7 @@ struct rte_flow_item_flex_handle *
 	}
 	flex->devx_fp = container_of(ent, struct mlx5_flex_parser_devx, entry);
 	/* Mark initialized flex item valid. */
-	__atomic_fetch_add(&flex->refcnt, 1, __ATOMIC_RELEASE);
+	rte_atomic_fetch_add_explicit(&flex->refcnt, 1, rte_memory_order_release);
 	return (struct rte_flow_item_flex_handle *)flex;
 
 error:

@@ -1378,8 +1378,8 @@ struct rte_flow_item_flex_handle *
 					  RTE_FLOW_ERROR_TYPE_ITEM, NULL,
 					  "invalid flex item handle value");
 	}
-	if (!__atomic_compare_exchange_n(&flex->refcnt, &old_refcnt, 0, 0,
-					 __ATOMIC_ACQUIRE, __ATOMIC_RELAXED)) {
+	if (!rte_atomic_compare_exchange_strong_explicit(&flex->refcnt, &old_refcnt, 0,
+					 rte_memory_order_acquire, rte_memory_order_relaxed)) {
 		rte_spinlock_unlock(&priv->flex_item_sl);
 		return rte_flow_error_set(error, EBUSY,
 					  RTE_FLOW_ERROR_TYPE_ITEM, NULL,

169 lines not on this page · raw message

index 4045c4c..f8eff60 100644
@@ -2055,9 +2055,9 @@ struct mlx5_flow_meter_policy *
 			NULL, "Meter profile id not valid.");
 	/* Meter policy must exist. */
 	if (params->meter_policy_id == priv->sh->mtrmng->def_policy_id) {
-		__atomic_fetch_add
+		rte_atomic_fetch_add_explicit
 			(&priv->sh->mtrmng->def_policy_ref_cnt,
-			1, __ATOMIC_RELAXED);
+			1, rte_memory_order_relaxed);
 		domain_bitmap = MLX5_MTR_ALL_DOMAIN_BIT;
 		if (!priv->sh->config.dv_esw_en)
 			domain_bitmap &= ~MLX5_MTR_DOMAIN_TRANSFER_BIT;

@@ -2137,7 +2137,7 @@ struct mlx5_flow_meter_policy *
 	fm->is_enable = params->meter_enable;
 	fm->shared = !!shared;
 	fm->color_aware = !!params->use_prev_mtr_color;
-	__atomic_fetch_add(&fm->profile->ref_cnt, 1, __ATOMIC_RELAXED);
+	rte_atomic_fetch_add_explicit(&fm->profile->ref_cnt, 1, rte_memory_order_relaxed);
 	if (params->meter_policy_id == priv->sh->mtrmng->def_policy_id) {
 		fm->def_policy = 1;
 		fm->flow_ipool = mlx5_ipool_create(&flow_ipool_cfg);

@@ -2166,7 +2166,7 @@ struct mlx5_flow_meter_policy *
 	}
 	fm->active_state = params->meter_enable;
 	if (mtr_policy)
-		__atomic_fetch_add(&mtr_policy->ref_cnt, 1, __ATOMIC_RELAXED);
+		rte_atomic_fetch_add_explicit(&mtr_policy->ref_cnt, 1, rte_memory_order_relaxed);
 	return 0;
 error:
 	mlx5_flow_destroy_mtr_tbls(dev, fm);

@@ -2271,8 +2271,8 @@ struct mlx5_flow_meter_policy *
 					  NULL, "Failed to create devx meter.");
 	}
 	fm->active_state = params->meter_enable;
-	__atomic_fetch_add(&fm->profile->ref_cnt, 1, __ATOMIC_RELAXED);
-	__atomic_fetch_add(&policy->ref_cnt, 1, __ATOMIC_RELAXED);
+	rte_atomic_fetch_add_explicit(&fm->profile->ref_cnt, 1, rte_memory_order_relaxed);
+	rte_atomic_fetch_add_explicit(&policy->ref_cnt, 1, rte_memory_order_relaxed);
 	return 0;
 }
 #endif

@@ -2295,7 +2295,7 @@ struct mlx5_flow_meter_policy *
 	if (fmp == NULL)
 		return -1;
 	/* Update dependencies. */
-	__atomic_fetch_sub(&fmp->ref_cnt, 1, __ATOMIC_RELAXED);
+	rte_atomic_fetch_sub_explicit(&fmp->ref_cnt, 1, rte_memory_order_relaxed);
 	fm->profile = NULL;
 	/* Remove from list. */
 	if (!priv->sh->meter_aso_en) {

@@ -2313,15 +2313,15 @@ struct mlx5_flow_meter_policy *
 	}
 	mlx5_flow_destroy_mtr_tbls(dev, fm);
 	if (fm->def_policy)
-		__atomic_fetch_sub(&priv->sh->mtrmng->def_policy_ref_cnt,
-				1, __ATOMIC_RELAXED);
+		rte_atomic_fetch_sub_explicit(&priv->sh->mtrmng->def_policy_ref_cnt,
+				1, rte_memory_order_relaxed);
 	if (priv->sh->meter_aso_en) {
 		if (!fm->def_policy) {
 			mtr_policy = mlx5_flow_meter_policy_find(dev,
 						fm->policy_id, NULL);
 			if (mtr_policy)
-				__atomic_fetch_sub(&mtr_policy->ref_cnt,
-						1, __ATOMIC_RELAXED);
+				rte_atomic_fetch_sub_explicit(&mtr_policy->ref_cnt,
+						1, rte_memory_order_relaxed);
 			fm->policy_id = 0;
 		}
 		fm->def_policy = 0;

@@ -2424,13 +2424,13 @@ struct mlx5_flow_meter_policy *
 					  RTE_MTR_ERROR_TYPE_UNSPECIFIED,
 					  NULL, "Meter object is being used.");
 	/* Destroy the meter profile. */
-	__atomic_fetch_sub(&fm->profile->ref_cnt,
-						1, __ATOMIC_RELAXED);
+	rte_atomic_fetch_sub_explicit(&fm->profile->ref_cnt,
+						1, rte_memory_order_relaxed);
 	/* Destroy the meter policy. */
 	policy = mlx5_flow_meter_policy_find(dev,
 			fm->policy_id, NULL);
-	__atomic_fetch_sub(&policy->ref_cnt,
-						1, __ATOMIC_RELAXED);
+	rte_atomic_fetch_sub_explicit(&policy->ref_cnt,
+						1, rte_memory_order_relaxed);
 	memset(fm, 0, sizeof(struct mlx5_flow_meter_info));
 	return 0;
 }

index 14a2a8b..6ad0e8a 100644
@@ -218,9 +218,9 @@ typedef void (*quota_wqe_cmd_t)(volatile struct mlx5_aso_wqe *restrict,
 		struct mlx5_quota *quota_obj =
 			sq->elts[(sq->tail + i) & mask].quota_obj;
 
-		__atomic_compare_exchange_n(&quota_obj->state, &state,
-					    MLX5_QUOTA_STATE_READY, false,
-					    __ATOMIC_RELAXED, __ATOMIC_RELAXED);
+		rte_atomic_compare_exchange_strong_explicit(&quota_obj->state, &state,
+					    MLX5_QUOTA_STATE_READY,
+					    rte_memory_order_relaxed, rte_memory_order_relaxed);
 	}
 }
 

@@ -278,7 +278,7 @@ typedef void (*quota_wqe_cmd_t)(volatile struct mlx5_aso_wqe *restrict,
 		rte_spinlock_lock(&sq->sqsl);
 		mlx5_quota_cmd_completion_handle(sq);
 		rte_spinlock_unlock(&sq->sqsl);
-		if (__atomic_load_n(&quota_obj->state, __ATOMIC_RELAXED) ==
+		if (rte_atomic_load_explicit(&quota_obj->state, rte_memory_order_relaxed) ==
 		    MLX5_QUOTA_STATE_READY)
 			return 0;
 	} while (poll_cqe_times -= MLX5_ASO_WQE_CQE_RESPONSE_DELAY);

@@ -470,9 +470,9 @@ typedef void (*quota_wqe_cmd_t)(volatile struct mlx5_aso_wqe *restrict,
 mlx5_quota_check_ready(struct mlx5_quota *qobj, struct rte_flow_error *error)
 {
 	uint8_t state = MLX5_QUOTA_STATE_READY;
-	bool verdict = __atomic_compare_exchange_n
-		(&qobj->state, &state, MLX5_QUOTA_STATE_WAIT, false,
-		 __ATOMIC_RELAXED, __ATOMIC_RELAXED);
+	bool verdict = rte_atomic_compare_exchange_strong_explicit
+		(&qobj->state, &state, MLX5_QUOTA_STATE_WAIT,
+		 rte_memory_order_relaxed, rte_memory_order_relaxed);
 
 	if (!verdict)
 		return rte_flow_error_set(error, EBUSY,

@@ -507,8 +507,8 @@ typedef void (*quota_wqe_cmd_t)(volatile struct mlx5_aso_wqe *restrict,
 	ret = mlx5_quota_cmd_wqe(dev, qobj, mlx5_quota_wqe_query, qix, work_queue,
 				 async_job ? async_job : &sync_job, push, NULL);
 	if (ret) {
-		__atomic_store_n(&qobj->state, MLX5_QUOTA_STATE_READY,
-				 __ATOMIC_RELAXED);
+		rte_atomic_store_explicit(&qobj->state, MLX5_QUOTA_STATE_READY,
+				 rte_memory_order_relaxed);
 		return rte_flow_error_set(error, EAGAIN,
 					  RTE_FLOW_ERROR_TYPE_ACTION, NULL, "try again");
 	}

@@ -557,8 +557,8 @@ typedef void (*quota_wqe_cmd_t)(volatile struct mlx5_aso_wqe *restrict,
 				 async_job ? async_job : &sync_job, push,
 				 (void *)(uintptr_t)update->conf);
 	if (ret) {
-		__atomic_store_n(&qobj->state, MLX5_QUOTA_STATE_READY,
-				 __ATOMIC_RELAXED);
+		rte_atomic_store_explicit(&qobj->state, MLX5_QUOTA_STATE_READY,
+				 rte_memory_order_relaxed);
 		return rte_flow_error_set(error, EAGAIN,
 					  RTE_FLOW_ERROR_TYPE_ACTION, NULL, "try again");
 	}

@@ -593,9 +593,9 @@ struct rte_flow_action_handle *
 				   NULL, "quota: failed to allocate quota object");
 		return NULL;
 	}
-	verdict = __atomic_compare_exchange_n
-		(&qobj->state, &state, MLX5_QUOTA_STATE_WAIT, false,
-		 __ATOMIC_RELAXED, __ATOMIC_RELAXED);
+	verdict = rte_atomic_compare_exchange_strong_explicit
+		(&qobj->state, &state, MLX5_QUOTA_STATE_WAIT,
+		 rte_memory_order_relaxed, rte_memory_order_relaxed);
 	if (!verdict) {
 		rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
 				   NULL, "quota: new quota object has invalid state");

@@ -616,8 +616,8 @@ struct rte_flow_action_handle *
 				 (void *)(uintptr_t)conf);
 	if (ret) {
 		mlx5_ipool_free(qctx->quota_ipool, id);
-		__atomic_store_n(&qobj->state, MLX5_QUOTA_STATE_FREE,
-				 __ATOMIC_RELAXED);
+		rte_atomic_store_explicit(&qobj->state, MLX5_QUOTA_STATE_FREE,
+				 rte_memory_order_relaxed);
 		rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
 				   NULL, "quota: WR failure");
 		return 0;

161 lines not on this page · raw message

index e005960..481442f 100644
@@ -101,7 +101,7 @@ struct mlx5_hws_cnt_pool {
 	LIST_ENTRY(mlx5_hws_cnt_pool) next;
 	struct mlx5_hws_cnt_pool_cfg cfg __rte_cache_aligned;
 	struct mlx5_hws_cnt_dcs_mng dcs_mng __rte_cache_aligned;
-	uint32_t query_gen __rte_cache_aligned;
+	RTE_ATOMIC(uint32_t) query_gen __rte_cache_aligned;
 	struct mlx5_hws_cnt *pool;
 	struct mlx5_hws_cnt_raw_data_mng *raw_mng;
 	struct rte_ring *reuse_list;

@@ -134,10 +134,10 @@ enum {
 
 /* HWS counter age parameter. */
 struct mlx5_hws_age_param {
-	uint32_t timeout; /* Aging timeout in seconds (atomically accessed). */
-	uint32_t sec_since_last_hit;
+	RTE_ATOMIC(uint32_t) timeout; /* Aging timeout in seconds (atomically accessed). */
+	RTE_ATOMIC(uint32_t) sec_since_last_hit;
 	/* Time in seconds since last hit (atomically accessed). */
-	uint16_t state; /* AGE state (atomically accessed). */
+	RTE_ATOMIC(uint16_t) state; /* AGE state (atomically accessed). */
 	uint64_t accumulator_last_hits;
 	/* Last total value of hits for comparing. */
 	uint64_t accumulator_hits;

@@ -426,7 +426,7 @@ struct mlx5_hws_age_param {
 	iidx = mlx5_hws_cnt_iidx(hpool, *cnt_id);
 	hpool->pool[iidx].in_used = false;
 	hpool->pool[iidx].query_gen_when_free =
-		__atomic_load_n(&hpool->query_gen, __ATOMIC_RELAXED);
+		rte_atomic_load_explicit(&hpool->query_gen, rte_memory_order_relaxed);
 	if (likely(queue != NULL) && cpool->cfg.host_cpool == NULL)
 		qcache = hpool->cache->qcache[*queue];
 	if (unlikely(qcache == NULL)) {

index 2fce908..c627113 100644
@@ -173,7 +173,7 @@ struct mlx5_rxq_ctrl {
 /* RX queue private data. */
 struct mlx5_rxq_priv {
 	uint16_t idx; /* Queue index. */
-	uint32_t refcnt; /* Reference counter. */
+	RTE_ATOMIC(uint32_t) refcnt; /* Reference counter. */
 	struct mlx5_rxq_ctrl *ctrl; /* Shared Rx Queue. */
 	LIST_ENTRY(mlx5_rxq_priv) owner_entry; /* Entry in shared rxq_ctrl. */
 	struct mlx5_priv *priv; /* Back pointer to private data. */

@@ -188,7 +188,7 @@ struct mlx5_rxq_priv {
 /* External RX queue descriptor. */
 struct mlx5_external_rxq {
 	uint32_t hw_id; /* Queue index in the Hardware. */
-	uint32_t refcnt; /* Reference counter. */
+	RTE_ATOMIC(uint32_t) refcnt; /* Reference counter. */
 };
 
 /* mlx5_rxq.c */

@@ -412,7 +412,7 @@ uint16_t mlx5_rx_burst_mprq_vec(void *dpdk_rxq, struct rte_mbuf **pkts,
 	struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[rq_idx];
 	void *addr;
 
-	if (__atomic_load_n(&buf->refcnt, __ATOMIC_RELAXED) > 1) {
+	if (rte_atomic_load_explicit(&buf->refcnt, rte_memory_order_relaxed) > 1) {
 		MLX5_ASSERT(rep != NULL);
 		/* Replace MPRQ buf. */
 		(*rxq->mprq_bufs)[rq_idx] = rep;

@@ -524,9 +524,9 @@ uint16_t mlx5_rx_burst_mprq_vec(void *dpdk_rxq, struct rte_mbuf **pkts,
 		void *buf_addr;
 
 		/* Increment the refcnt of the whole chunk. */
-		__atomic_fetch_add(&buf->refcnt, 1, __ATOMIC_RELAXED);
-		MLX5_ASSERT(__atomic_load_n(&buf->refcnt,
-			    __ATOMIC_RELAXED) <= strd_n + 1);
+		rte_atomic_fetch_add_explicit(&buf->refcnt, 1, rte_memory_order_relaxed);
+		MLX5_ASSERT(rte_atomic_load_explicit(&buf->refcnt,
+			    rte_memory_order_relaxed) <= strd_n + 1);
 		buf_addr = RTE_PTR_SUB(addr, RTE_PKTMBUF_HEADROOM);
 		/*
 		 * MLX5 device doesn't use iova but it is necessary in a

@@ -666,7 +666,7 @@ uint16_t mlx5_rx_burst_mprq_vec(void *dpdk_rxq, struct rte_mbuf **pkts,
 	if (!priv->ext_rxqs || queue_idx < RTE_PMD_MLX5_EXTERNAL_RX_QUEUE_ID_MIN)
 		return false;
 	rxq = &priv->ext_rxqs[queue_idx - RTE_PMD_MLX5_EXTERNAL_RX_QUEUE_ID_MIN];
-	return !!__atomic_load_n(&rxq->refcnt, __ATOMIC_RELAXED);
+	return !!rte_atomic_load_explicit(&rxq->refcnt, rte_memory_order_relaxed);
 }
 
 #define LWM_COOKIE_RXQID_OFFSET 0

index dd51687..f67aaa6 100644
@@ -416,7 +416,7 @@
 		rte_errno = EINVAL;
 		return -rte_errno;
 	}
-	return (__atomic_load_n(&rxq->refcnt, __ATOMIC_RELAXED) == 1);
+	return (rte_atomic_load_explicit(&rxq->refcnt, rte_memory_order_relaxed) == 1);
 }
 
 /* Fetches and drops all SW-owned and error CQEs to synchronize CQ. */

@@ -1319,7 +1319,7 @@
 
 	memset(_m, 0, sizeof(*buf));
 	buf->mp = mp;
-	__atomic_store_n(&buf->refcnt, 1, __ATOMIC_RELAXED);
+	rte_atomic_store_explicit(&buf->refcnt, 1, rte_memory_order_relaxed);
 	for (j = 0; j != strd_n; ++j) {
 		shinfo = &buf->shinfos[j];
 		shinfo->free_cb = mlx5_mprq_buf_free_cb;

@@ -2037,7 +2037,7 @@ struct mlx5_rxq_priv *
 	struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, idx);
 
 	if (rxq != NULL)
-		__atomic_fetch_add(&rxq->refcnt, 1, __ATOMIC_RELAXED);
+		rte_atomic_fetch_add_explicit(&rxq->refcnt, 1, rte_memory_order_relaxed);
 	return rxq;
 }
 

@@ -2059,7 +2059,7 @@ struct mlx5_rxq_priv *
 
 	if (rxq == NULL)
 		return 0;
-	return __atomic_fetch_sub(&rxq->refcnt, 1, __ATOMIC_RELAXED) - 1;
+	return rte_atomic_fetch_sub_explicit(&rxq->refcnt, 1, rte_memory_order_relaxed) - 1;
 }
 
 /**

@@ -2138,7 +2138,7 @@ struct mlx5_external_rxq *
 {
 	struct mlx5_external_rxq *rxq = mlx5_ext_rxq_get(dev, idx);
 
-	__atomic_fetch_add(&rxq->refcnt, 1, __ATOMIC_RELAXED);
+	rte_atomic_fetch_add_explicit(&rxq->refcnt, 1, rte_memory_order_relaxed);
 	return rxq;
 }
 

@@ -2158,7 +2158,7 @@ struct mlx5_external_rxq *
 {
 	struct mlx5_external_rxq *rxq = mlx5_ext_rxq_get(dev, idx);
 
-	return __atomic_fetch_sub(&rxq->refcnt, 1, __ATOMIC_RELAXED) - 1;
+	return rte_atomic_fetch_sub_explicit(&rxq->refcnt, 1, rte_memory_order_relaxed) - 1;
 }
 
 /**

@@ -2447,8 +2447,8 @@ struct mlx5_ind_table_obj *
 		    (memcmp(ind_tbl->queues, queues,
 			    ind_tbl->queues_n * sizeof(ind_tbl->queues[0]))
 		     == 0)) {
-			__atomic_fetch_add(&ind_tbl->refcnt, 1,
-					   __ATOMIC_RELAXED);
+			rte_atomic_fetch_add_explicit(&ind_tbl->refcnt, 1,
+					   rte_memory_order_relaxed);
 			break;
 		}
 	}

@@ -2479,7 +2479,7 @@ struct mlx5_ind_table_obj *
 	unsigned int ret;
 
 	rte_rwlock_write_lock(&priv->ind_tbls_lock);
-	ret = __atomic_fetch_sub(&ind_tbl->refcnt, 1, __ATOMIC_RELAXED) - 1;
+	ret = rte_atomic_fetch_sub_explicit(&ind_tbl->refcnt, 1, rte_memory_order_relaxed) - 1;
 	if (!ret)
 		LIST_REMOVE(ind_tbl, next);
 	rte_rwlock_write_unlock(&priv->ind_tbls_lock);

@@ -2561,7 +2561,7 @@ struct mlx5_ind_table_obj *
 		}
 		return ret;
 	}
-	__atomic_fetch_add(&ind_tbl->refcnt, 1, __ATOMIC_RELAXED);
+	rte_atomic_fetch_add_explicit(&ind_tbl->refcnt, 1, rte_memory_order_relaxed);
 	return 0;
 }
 

@@ -2626,7 +2626,7 @@ struct mlx5_ind_table_obj *
 {
 	uint32_t refcnt;
 
-	refcnt = __atomic_load_n(&ind_tbl->refcnt, __ATOMIC_RELAXED);
+	refcnt = rte_atomic_load_explicit(&ind_tbl->refcnt, rte_memory_order_relaxed);
 	if (refcnt <= 1)
 		return 0;
 	/*

@@ -3258,8 +3258,8 @@ struct mlx5_hrxq *
 	ext_rxq = mlx5_external_rx_queue_get_validate(port_id, dpdk_idx);
 	if (ext_rxq == NULL)
 		return -rte_errno;
-	if (!__atomic_compare_exchange_n(&ext_rxq->refcnt, &unmapped, 1, false,
-					 __ATOMIC_RELAXED, __ATOMIC_RELAXED)) {
+	if (!rte_atomic_compare_exchange_strong_explicit(&ext_rxq->refcnt, &unmapped, 1,
+					 rte_memory_order_relaxed, rte_memory_order_relaxed)) {
 		if (ext_rxq->hw_id != hw_idx) {
 			DRV_LOG(ERR, "Port %u external RxQ index %u "
 				"is already mapped to HW index (requesting is "

@@ -3296,8 +3296,8 @@ struct mlx5_hrxq *
 		rte_errno = EINVAL;
 		return -rte_errno;
 	}
-	if (!__atomic_compare_exchange_n(&ext_rxq->refcnt, &mapped, 0, false,
-					 __ATOMIC_RELAXED, __ATOMIC_RELAXED)) {
+	if (!rte_atomic_compare_exchange_strong_explicit(&ext_rxq->refcnt, &mapped, 0,
+					 rte_memory_order_relaxed, rte_memory_order_relaxed)) {
 		DRV_LOG(ERR, "Port %u external RxQ index %u doesn't exist.",
 			port_id, dpdk_idx);
 		rte_errno = EINVAL;

index f8d6728..c241a1d 100644
@@ -1441,7 +1441,7 @@
 	rte_delay_us_sleep(1000 * priv->rxqs_n);
 	DRV_LOG(DEBUG, "port %u stopping device", dev->data->port_id);
 	if (priv->sh->config.dv_flow_en == 2) {
-		if (!__atomic_load_n(&priv->hws_mark_refcnt, __ATOMIC_RELAXED))
+		if (!rte_atomic_load_explicit(&priv->hws_mark_refcnt, rte_memory_order_relaxed))
 			flow_hw_rxq_flag_set(dev, false);
 	} else {
 		mlx5_flow_stop_default(dev);

index b1e8ea1..0e44df5 100644
@@ -179,7 +179,7 @@ struct mlx5_txq_data {
 __extension__
 struct mlx5_txq_ctrl {
 	LIST_ENTRY(mlx5_txq_ctrl) next; /* Pointer to the next element. */
-	uint32_t refcnt; /* Reference counter. */
+	RTE_ATOMIC(uint32_t) refcnt; /* Reference counter. */
 	unsigned int socket; /* CPU socket ID for allocations. */
 	bool is_hairpin; /* Whether TxQ type is Hairpin. */
 	unsigned int max_inline_data; /* Max inline data. */

@@ -339,8 +339,8 @@ int mlx5_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
 		 * the service thread, data should be re-read.
 		 */
 		rte_compiler_barrier();
-		ci = __atomic_load_n(&sh->txpp.ts.ci_ts, __ATOMIC_RELAXED);
-		ts = __atomic_load_n(&sh->txpp.ts.ts, __ATOMIC_RELAXED);
+		ci = rte_atomic_load_explicit(&sh->txpp.ts.ci_ts, rte_memory_order_relaxed);
+		ts = rte_atomic_load_explicit(&sh->txpp.ts.ts, rte_memory_order_relaxed);
 		rte_compiler_barrier();
 		if (!((ts ^ ci) << (64 - MLX5_CQ_INDEX_WIDTH)))
 			break;

@@ -350,8 +350,8 @@ int mlx5_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
 	mts -= ts;
 	if (unlikely(mts >= UINT64_MAX / 2)) {
 		/* We have negative integer, mts is in the past. */
-		__atomic_fetch_add(&sh->txpp.err_ts_past,
-				   1, __ATOMIC_RELAXED);
+		rte_atomic_fetch_add_explicit(&sh->txpp.err_ts_past,
+				   1, rte_memory_order_relaxed);
 		return -1;
 	}
 	tick = sh->txpp.tick;

@@ -360,8 +360,8 @@ int mlx5_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
 	mts = (mts + tick - 1) / tick;
 	if (unlikely(mts >= (1 << MLX5_CQ_INDEX_WIDTH) / 2 - 1)) {
 		/* We have mts is too distant future. */
-		__atomic_fetch_add(&sh->txpp.err_ts_future,
-				   1, __ATOMIC_RELAXED);
+		rte_atomic_fetch_add_explicit(&sh->txpp.err_ts_future,
+				   1, rte_memory_order_relaxed);
 		return -1;
 	}
 	mts <<= 64 - MLX5_CQ_INDEX_WIDTH;

@@ -1743,8 +1743,8 @@ int mlx5_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
 		/* Convert the timestamp into completion to wait. */
 		ts = *RTE_MBUF_DYNFIELD(loc->mbuf, txq->ts_offset, uint64_t *);
 		if (txq->ts_last && ts < txq->ts_last)
-			__atomic_fetch_add(&txq->sh->txpp.err_ts_order,
-					   1, __ATOMIC_RELAXED);
+			rte_atomic_fetch_add_explicit(&txq->sh->txpp.err_ts_order,
+					   1, rte_memory_order_relaxed);
 		txq->ts_last = ts;
 		wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
 		sh = txq->sh;

155 lines not on this page · raw message

index 14f55e8..da4236f 100644
@@ -1108,7 +1108,7 @@ struct mlx5_txq_ctrl *
 		rte_errno = ENOMEM;
 		goto error;
 	}
-	__atomic_fetch_add(&tmpl->refcnt, 1, __ATOMIC_RELAXED);
+	rte_atomic_fetch_add_explicit(&tmpl->refcnt, 1, rte_memory_order_relaxed);
 	tmpl->is_hairpin = false;
 	LIST_INSERT_HEAD(&priv->txqsctrl, tmpl, next);
 	return tmpl;

@@ -1153,7 +1153,7 @@ struct mlx5_txq_ctrl *
 	tmpl->txq.idx = idx;
 	tmpl->hairpin_conf = *hairpin_conf;
 	tmpl->is_hairpin = true;
-	__atomic_fetch_add(&tmpl->refcnt, 1, __ATOMIC_RELAXED);
+	rte_atomic_fetch_add_explicit(&tmpl->refcnt, 1, rte_memory_order_relaxed);
 	LIST_INSERT_HEAD(&priv->txqsctrl, tmpl, next);
 	return tmpl;
 }

@@ -1178,7 +1178,7 @@ struct mlx5_txq_ctrl *
 
 	if (txq_data) {
 		ctrl = container_of(txq_data, struct mlx5_txq_ctrl, txq);
-		__atomic_fetch_add(&ctrl->refcnt, 1, __ATOMIC_RELAXED);
+		rte_atomic_fetch_add_explicit(&ctrl->refcnt, 1, rte_memory_order_relaxed);
 	}
 	return ctrl;
 }

@@ -1203,7 +1203,7 @@ struct mlx5_txq_ctrl *
 	if (priv->txqs == NULL || (*priv->txqs)[idx] == NULL)
 		return 0;
 	txq_ctrl = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
-	if (__atomic_fetch_sub(&txq_ctrl->refcnt, 1, __ATOMIC_RELAXED) - 1 > 1)
+	if (rte_atomic_fetch_sub_explicit(&txq_ctrl->refcnt, 1, rte_memory_order_relaxed) - 1 > 1)
 		return 1;
 	if (txq_ctrl->obj) {
 		priv->obj_ops.txq_obj_release(txq_ctrl->obj);

@@ -1219,7 +1219,7 @@ struct mlx5_txq_ctrl *
 		txq_free_elts(txq_ctrl);
 		dev->data->tx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STOPPED;
 	}
-	if (!__atomic_load_n(&txq_ctrl->refcnt, __ATOMIC_RELAXED)) {
+	if (!rte_atomic_load_explicit(&txq_ctrl->refcnt, rte_memory_order_relaxed)) {
 		if (!txq_ctrl->is_hairpin)
 			mlx5_mr_btree_free(&txq_ctrl->txq.mr_ctrl.cache_bh);
 		LIST_REMOVE(txq_ctrl, next);

@@ -1249,7 +1249,7 @@ struct mlx5_txq_ctrl *
 	if (!(*priv->txqs)[idx])
 		return -1;
 	txq = container_of((*priv->txqs)[idx], struct mlx5_txq_ctrl, txq);
-	return (__atomic_load_n(&txq->refcnt, __ATOMIC_RELAXED) == 1);
+	return (rte_atomic_load_explicit(&txq->refcnt, rte_memory_order_relaxed) == 1);
 }
 
 /**

index e28db2e..fc03cc0 100644
@@ -203,7 +203,7 @@ struct mlx5_indexed_pool *
 	struct mlx5_indexed_cache *gc, *lc, *olc = NULL;
 
 	lc = pool->cache[cidx]->lc;
-	gc = __atomic_load_n(&pool->gc, __ATOMIC_RELAXED);
+	gc = rte_atomic_load_explicit(&pool->gc, rte_memory_order_relaxed);
 	if (gc && lc != gc) {
 		mlx5_ipool_lock(pool);
 		if (lc && !(--lc->ref_cnt))

@@ -266,8 +266,8 @@ struct mlx5_indexed_pool *
 		pool->cache[cidx]->len = fetch_size - 1;
 		return pool->cache[cidx]->idx[pool->cache[cidx]->len];
 	}
-	trunk_idx = lc ? __atomic_load_n(&lc->n_trunk_valid,
-			 __ATOMIC_ACQUIRE) : 0;
+	trunk_idx = lc ? rte_atomic_load_explicit(&lc->n_trunk_valid,
+			 rte_memory_order_acquire) : 0;
 	trunk_n = lc ? lc->n_trunk : 0;
 	cur_max_idx = mlx5_trunk_idx_offset_get(pool, trunk_idx);
 	/* Check if index reach maximum. */

@@ -332,11 +332,11 @@ struct mlx5_indexed_pool *
 		lc = p;
 		lc->ref_cnt = 1;
 		pool->cache[cidx]->lc = lc;
-		__atomic_store_n(&pool->gc, p, __ATOMIC_RELAXED);
+		rte_atomic_store_explicit(&pool->gc, p, rte_memory_order_relaxed);
 	}
 	/* Add trunk to trunks array. */
 	lc->trunks[trunk_idx] = trunk;
-	__atomic_fetch_add(&lc->n_trunk_valid, 1, __ATOMIC_RELAXED);
+	rte_atomic_fetch_add_explicit(&lc->n_trunk_valid, 1, rte_memory_order_relaxed);
 	/* Enqueue half of the index to global. */
 	ts_idx = mlx5_trunk_idx_offset_get(pool, trunk_idx) + 1;
 	fetch_size = trunk->free >> 1;

index f3c0d76..3146092 100644
@@ -240,7 +240,7 @@ struct mlx5_indexed_trunk {
 
 struct mlx5_indexed_cache {
 	struct mlx5_indexed_trunk **trunks;
-	volatile uint32_t n_trunk_valid; /* Trunks allocated. */
+	volatile RTE_ATOMIC(uint32_t) n_trunk_valid; /* Trunks allocated. */
 	uint32_t n_trunk; /* Trunk pointer array size. */
 	uint32_t ref_cnt;
 	uint32_t len;

@@ -266,7 +266,7 @@ struct mlx5_indexed_pool {
 			uint32_t free_list; /* Index to first free trunk. */
 		};
 		struct {
-			struct mlx5_indexed_cache *gc;
+			RTE_ATOMIC(struct mlx5_indexed_cache *) gc;
 			/* Global cache. */
 			struct mlx5_ipool_per_lcore *cache[RTE_MAX_LCORE + 1];
 			/* Local cache. */

index c61c52b..e63ae1a 100644
@@ -1130,7 +1130,7 @@ struct rte_ixgbe_xstats_name_off {
 	}
 
 	/* NOTE: review for potential ordering optimization */
-	__atomic_clear(&ad->link_thread_running, __ATOMIC_SEQ_CST);
+	rte_atomic_store_explicit(&ad->link_thread_running, 0, rte_memory_order_seq_cst);
 	ixgbe_parse_devargs(eth_dev->data->dev_private,
 			    pci_dev->device.devargs);
 	rte_eth_copy_pci_info(eth_dev, pci_dev);

@@ -1638,7 +1638,7 @@ static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
 	}
 
 	/* NOTE: review for potential ordering optimization */
-	__atomic_clear(&ad->link_thread_running, __ATOMIC_SEQ_CST);
+	rte_atomic_store_explicit(&ad->link_thread_running, 0, rte_memory_order_seq_cst);
 	ixgbevf_parse_devargs(eth_dev->data->dev_private,
 			      pci_dev->device.devargs);
 

@@ -4203,7 +4203,7 @@ static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 	uint32_t timeout = timeout_ms ? timeout_ms : WARNING_TIMEOUT;
 
 	/* NOTE: review for potential ordering optimization */
-	while (__atomic_load_n(&ad->link_thread_running, __ATOMIC_SEQ_CST)) {
+	while (rte_atomic_load_explicit(&ad->link_thread_running, rte_memory_order_seq_cst)) {
 		msec_delay(1);
 		timeout--;
 

@@ -4240,7 +4240,7 @@ static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 
 	intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
 	/* NOTE: review for potential ordering optimization */
-	__atomic_clear(&ad->link_thread_running, __ATOMIC_SEQ_CST);
+	rte_atomic_store_explicit(&ad->link_thread_running, 0, rte_memory_order_seq_cst);
 	return 0;
 }
 

@@ -4336,7 +4336,8 @@ static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 		if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
 			ixgbe_dev_wait_setup_link_complete(dev, 0);
 			/* NOTE: review for potential ordering optimization */
-			if (!__atomic_test_and_set(&ad->link_thread_running, __ATOMIC_SEQ_CST)) {
+			if (!rte_atomic_exchange_explicit(&ad->link_thread_running, 1,
+			    rte_memory_order_seq_cst)) {
 				/* To avoid race condition between threads, set
 				 * the IXGBE_FLAG_NEED_LINK_CONFIG flag only
 				 * when there is no link thread running.

@@ -4348,7 +4349,8 @@ static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 					PMD_DRV_LOG(ERR,
 						"Create link thread failed!");
 					/* NOTE: review for potential ordering optimization */
-					__atomic_clear(&ad->link_thread_running, __ATOMIC_SEQ_CST);
+					rte_atomic_store_explicit(&ad->link_thread_running, 0,
+					    rte_memory_order_seq_cst);
 				}
 			} else {
 				PMD_DRV_LOG(ERR,

index 22fc3be..8ad841e 100644
@@ -511,7 +511,7 @@ struct ixgbe_adapter {
 	 */
 	uint8_t pflink_fullchk;
 	uint8_t mac_ctrl_frame_fwd;
-	bool link_thread_running;
+	RTE_ATOMIC(bool) link_thread_running;
 	rte_thread_t link_thread_tid;
 };
 

index f6c17d4..e7dfd6f 100644
@@ -1831,7 +1831,7 @@
 		 * Use acquire fence to ensure that status_error which includes
 		 * DD bit is loaded before loading of other descriptor words.
 		 */
-		rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
+		rte_atomic_thread_fence(rte_memory_order_acquire);
 
 		rxd = *rxdp;
 

@@ -2114,7 +2114,7 @@
 		 * Use acquire fence to ensure that status_error which includes
 		 * DD bit is loaded before loading of other descriptor words.
 		 */
-		rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
+		rte_atomic_thread_fence(rte_memory_order_acquire);
 
 		rxd = *rxdp;
 

index 824ae4a..6b977e5 100644
@@ -238,8 +238,8 @@ struct iavf_info {
 	struct virtchnl_vlan_caps vlan_v2_caps;
 	uint64_t supported_rxdid;
 	uint8_t *proto_xtr; /* proto xtr type for all queues */
-	volatile enum virtchnl_ops pend_cmd; /* pending command not finished */
-	uint32_t pend_cmd_count;
+	volatile RTE_ATOMIC(enum virtchnl_ops) pend_cmd; /* pending command not finished */
+	RTE_ATOMIC(uint32_t) pend_cmd_count;
 	int cmd_retval; /* return value of the cmd response from PF */
 	uint8_t *aq_resp; /* buffer to store the adminq response from PF */
 

@@ -456,13 +456,13 @@ struct iavf_cmd_info {
 _atomic_set_cmd(struct iavf_info *vf, enum virtchnl_ops ops)
 {
 	enum virtchnl_ops op_unk = VIRTCHNL_OP_UNKNOWN;
-	int ret = __atomic_compare_exchange(&vf->pend_cmd, &op_unk, &ops,
-			0, __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
+	int ret = rte_atomic_compare_exchange_strong_explicit(&vf->pend_cmd, &op_unk, ops,
+			rte_memory_order_acquire, rte_memory_order_acquire);
 
 	if (!ret)
 		PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
 
-	__atomic_store_n(&vf->pend_cmd_count, 1, __ATOMIC_RELAXED);
+	rte_atomic_store_explicit(&vf->pend_cmd_count, 1, rte_memory_order_relaxed);
 
 	return !ret;
 }

@@ -472,13 +472,13 @@ struct iavf_cmd_info {
 _atomic_set_async_response_cmd(struct iavf_info *vf, enum virtchnl_ops ops)
 {
 	enum virtchnl_ops op_unk = VIRTCHNL_OP_UNKNOWN;
-	int ret = __atomic_compare_exchange(&vf->pend_cmd, &op_unk, &ops,
-			0, __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
+	int ret = rte_atomic_compare_exchange_strong_explicit(&vf->pend_cmd, &op_unk, ops,
+			rte_memory_order_acquire, rte_memory_order_acquire);
 
 	if (!ret)
 		PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
 
-	__atomic_store_n(&vf->pend_cmd_count, 2, __ATOMIC_RELAXED);
+	rte_atomic_store_explicit(&vf->pend_cmd_count, 2, rte_memory_order_relaxed);
 
 	return !ret;
 }

index 0a5246d..d1d4e9f 100644
@@ -2025,7 +2025,7 @@ struct iavf_txq_ops iavf_txq_release_mbufs_ops[] = {
 			s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
 
 		/* This barrier is to order loads of different words in the descriptor */
-		rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
+		rte_atomic_thread_fence(rte_memory_order_acquire);
 
 		/* Compute how many contiguous DD bits were set */
 		for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++) {

@@ -2152,7 +2152,7 @@ struct iavf_txq_ops iavf_txq_release_mbufs_ops[] = {
 		}
 
 		/* This barrier is to order loads of different words in the descriptor */
-		rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
+		rte_atomic_thread_fence(rte_memory_order_acquire);
 
 		/* Compute how many contiguous DD bits were set */
 		for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++) {

index 83825aa..20b656e 100644
@@ -273,7 +273,7 @@
 		descs[0] =  vld1q_u64((uint64_t *)(rxdp));
 
 		/* Use acquire fence to order loads of descriptor qwords */
-		rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
+		rte_atomic_thread_fence(rte_memory_order_acquire);
 		/* A.2 reload qword0 to make it ordered after qword1 load */
 		descs[3] = vld1q_lane_u64((uint64_t *)(rxdp + 3), descs[3], 0);
 		descs[2] = vld1q_lane_u64((uint64_t *)(rxdp + 2), descs[2], 0);

index 1111d30..6d5969f 100644
@@ -41,7 +41,7 @@ struct iavf_event_element {
 };
 
 struct iavf_event_handler {
-	uint32_t ndev;
+	RTE_ATOMIC(uint32_t) ndev;
 	rte_thread_t tid;
 	int fd[2];
 	pthread_mutex_t lock;

@@ -129,7 +129,7 @@ struct iavf_event_handler {
 {
 	struct iavf_event_handler *handler = &event_handler;
 
-	if (__atomic_fetch_add(&handler->ndev, 1, __ATOMIC_RELAXED) + 1 != 1)
+	if (rte_atomic_fetch_add_explicit(&handler->ndev, 1, rte_memory_order_relaxed) + 1 != 1)
 		return 0;
 #if defined(RTE_EXEC_ENV_IS_WINDOWS) && RTE_EXEC_ENV_IS_WINDOWS != 0
 	int err = _pipe(handler->fd, MAX_EVENT_PENDING, O_BINARY);

@@ -137,7 +137,7 @@ struct iavf_event_handler {
 	int err = pipe(handler->fd);
 #endif
 	if (err != 0) {
-		__atomic_fetch_sub(&handler->ndev, 1, __ATOMIC_RELAXED);
+		rte_atomic_fetch_sub_explicit(&handler->ndev, 1, rte_memory_order_relaxed);
 		return -1;
 	}
 

@@ -146,7 +146,7 @@ struct iavf_event_handler {
 
 	if (rte_thread_create_internal_control(&handler->tid, "iavf-event",
 				iavf_dev_event_handle, NULL)) {
-		__atomic_fetch_sub(&handler->ndev, 1, __ATOMIC_RELAXED);
+		rte_atomic_fetch_sub_explicit(&handler->ndev, 1, rte_memory_order_relaxed);
 		return -1;
 	}
 

@@ -158,7 +158,7 @@ struct iavf_event_handler {
 {
 	struct iavf_event_handler *handler = &event_handler;
 
-	if (__atomic_fetch_sub(&handler->ndev, 1, __ATOMIC_RELAXED) - 1 != 0)
+	if (rte_atomic_fetch_sub_explicit(&handler->ndev, 1, rte_memory_order_relaxed) - 1 != 0)
 		return;
 
 	int unused = pthread_cancel((pthread_t)handler->tid.opaque_id);

@@ -574,8 +574,8 @@ struct iavf_event_handler {
 				/* read message and it's expected one */
 				if (msg_opc == vf->pend_cmd) {
 					uint32_t cmd_count =
-					__atomic_fetch_sub(&vf->pend_cmd_count,
-							1, __ATOMIC_RELAXED) - 1;
+					rte_atomic_fetch_sub_explicit(&vf->pend_cmd_count,
+							1, rte_memory_order_relaxed) - 1;
 					if (cmd_count == 0)
 						_notify_cmd(vf, msg_ret);
 				} else {

index 0e14b93..c17f1bf 100644
@@ -235,7 +235,7 @@ struct ice_lock {
 ice_alloc_dma_mem(__rte_unused struct ice_hw *hw,
 		  struct ice_dma_mem *mem, u64 size)
 {
-	static uint64_t ice_dma_memzone_id;
+	static RTE_ATOMIC(uint64_t) ice_dma_memzone_id;
 	const struct rte_memzone *mz = NULL;
 	char z_name[RTE_MEMZONE_NAMESIZE];
 

@@ -243,7 +243,7 @@ struct ice_lock {
 		return NULL;
 
 	snprintf(z_name, sizeof(z_name), "ice_dma_%" PRIu64,
-		__atomic_fetch_add(&ice_dma_memzone_id, 1, __ATOMIC_RELAXED));
+		rte_atomic_fetch_add_explicit(&ice_dma_memzone_id, 1, rte_memory_order_relaxed));
 	mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
 					 0, RTE_PGSIZE_2M);
 	if (!mz)

index 7f8f516..204d4ea 100644
@@ -764,7 +764,7 @@ struct virtchnl_proto_hdrs ice_dcf_inner_ipv6_sctp_tmplt = {
 	rte_spinlock_init(&hw->vc_cmd_queue_lock);
 	TAILQ_INIT(&hw->vc_cmd_queue);
 
-	__atomic_store_n(&hw->vsi_update_thread_num, 0, __ATOMIC_RELAXED);
+	rte_atomic_store_explicit(&hw->vsi_update_thread_num, 0, rte_memory_order_relaxed);
 
 	hw->arq_buf = rte_zmalloc("arq_buf", ICE_DCF_AQ_BUF_SZ, 0);
 	if (hw->arq_buf == NULL) {

@@ -888,8 +888,8 @@ struct virtchnl_proto_hdrs ice_dcf_inner_ipv6_sctp_tmplt = {
 				     ice_dcf_dev_interrupt_handler, hw);
 
 	/* Wait for all `ice-thread` threads to exit. */
-	while (__atomic_load_n(&hw->vsi_update_thread_num,
-		__ATOMIC_ACQUIRE) != 0)
+	while (rte_atomic_load_explicit(&hw->vsi_update_thread_num,
+		rte_memory_order_acquire) != 0)
 		rte_delay_ms(ICE_DCF_CHECK_INTERVAL);
 
 	ice_dcf_mode_disable(hw);

index aa2a723..7726681 100644
@@ -105,7 +105,7 @@ struct ice_dcf_hw {
 	void (*vc_event_msg_cb)(struct ice_dcf_hw *dcf_hw,
 				uint8_t *msg, uint16_t msglen);
 
-	int vsi_update_thread_num;
+	RTE_ATOMIC(int) vsi_update_thread_num;
 
 	uint8_t *arq_buf;
 

index d58ec9d..8f3a385 100644
@@ -1743,7 +1743,7 @@ static int ice_dcf_xstats_get(struct rte_eth_dev *dev,
 ice_dcf_adminq_need_retry(struct ice_adapter *ad)
 {
 	return ad->hw.dcf_enabled &&
-	       !__atomic_load_n(&ad->dcf_state_on, __ATOMIC_RELAXED);
+	       !rte_atomic_load_explicit(&ad->dcf_state_on, rte_memory_order_relaxed);
 }
 
 /* Add UDP tunneling port */

@@ -1944,12 +1944,12 @@ static int ice_dcf_xstats_get(struct rte_eth_dev *dev,
 	adapter->real_hw.vc_event_msg_cb = ice_dcf_handle_pf_event_msg;
 	if (ice_dcf_init_hw(eth_dev, &adapter->real_hw) != 0) {
 		PMD_INIT_LOG(ERR, "Failed to init DCF hardware");
-		__atomic_store_n(&parent_adapter->dcf_state_on, false,
-				 __ATOMIC_RELAXED);
+		rte_atomic_store_explicit(&parent_adapter->dcf_state_on, false,
+				 rte_memory_order_relaxed);
 		return -1;
 	}
 
-	__atomic_store_n(&parent_adapter->dcf_state_on, true, __ATOMIC_RELAXED);
+	rte_atomic_store_explicit(&parent_adapter->dcf_state_on, true, rte_memory_order_relaxed);
 
 	if (ice_dcf_init_parent_adapter(eth_dev) != 0) {
 		PMD_INIT_LOG(ERR, "Failed to init DCF parent adapter");

index 6e845f4..a478b69 100644
@@ -123,8 +123,8 @@ struct ice_dcf_reset_event_param {
 		container_of(hw, struct ice_dcf_adapter, real_hw);
 	struct ice_adapter *parent_adapter = &adapter->parent;
 
-	__atomic_fetch_add(&hw->vsi_update_thread_num, 1,
-		__ATOMIC_RELAXED);
+	rte_atomic_fetch_add_explicit(&hw->vsi_update_thread_num, 1,
+		rte_memory_order_relaxed);
 
 	rte_thread_detach(rte_thread_self());
 

@@ -133,8 +133,8 @@ struct ice_dcf_reset_event_param {
 	rte_spinlock_lock(&vsi_update_lock);
 
 	if (!ice_dcf_handle_vsi_update_event(hw)) {
-		__atomic_store_n(&parent_adapter->dcf_state_on, true,
-				 __ATOMIC_RELAXED);
+		rte_atomic_store_explicit(&parent_adapter->dcf_state_on, true,
+				 rte_memory_order_relaxed);
 		ice_dcf_update_vf_vsi_map(&adapter->parent.hw,
 					  hw->num_vfs, hw->vf_vsi_map);
 	}

@@ -156,8 +156,8 @@ struct ice_dcf_reset_event_param {
 
 	free(param);
 
-	__atomic_fetch_sub(&hw->vsi_update_thread_num, 1,
-		__ATOMIC_RELEASE);
+	rte_atomic_fetch_sub_explicit(&hw->vsi_update_thread_num, 1,
+		rte_memory_order_release);
 
 	return 0;
 }

@@ -269,8 +269,8 @@ struct ice_dcf_reset_event_param {
 		PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_DCF_VSI_MAP_UPDATE event : VF%u with VSI num %u",
 			    pf_msg->event_data.vf_vsi_map.vf_id,
 			    pf_msg->event_data.vf_vsi_map.vsi_id);
-		__atomic_store_n(&parent_adapter->dcf_state_on, false,
-				 __ATOMIC_RELAXED);
+		rte_atomic_store_explicit(&parent_adapter->dcf_state_on, false,
+				 rte_memory_order_relaxed);
 		start_vsi_reset_thread(dcf_hw, true,
 				       pf_msg->event_data.vf_vsi_map.vf_id);
 		break;

index 87385d2..0f35c6a 100644
@@ -4062,9 +4062,9 @@ static int ice_init_rss(struct ice_pf *pf)
 	struct rte_eth_link *src = &dev->data->dev_link;
 
 	/* NOTE: review for potential ordering optimization */
-	if (!__atomic_compare_exchange_n((uint64_t *)dst, (uint64_t *)dst,
-			*(uint64_t *)src, 0,
-			__ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST))
+	if (!rte_atomic_compare_exchange_strong_explicit((uint64_t __rte_atomic *)dst,
+			(uint64_t *)dst, *(uint64_t *)src,
+			rte_memory_order_seq_cst, rte_memory_order_seq_cst))
 		return -1;
 
 	return 0;

@@ -4078,9 +4078,9 @@ static int ice_init_rss(struct ice_pf *pf)
 	struct rte_eth_link *src = link;
 
 	/* NOTE: review for potential ordering optimization */
-	if (!__atomic_compare_exchange_n((uint64_t *)dst, (uint64_t *)dst,
-			*(uint64_t *)src, 0,
-			__ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST))
+	if (!rte_atomic_compare_exchange_strong_explicit((uint64_t __rte_atomic *)dst,
+			(uint64_t *)dst, *(uint64_t *)src,
+			rte_memory_order_seq_cst, rte_memory_order_seq_cst))
 		return -1;
 
 	return 0;

index 1a848b3..6cba643 100644
@@ -621,7 +621,7 @@ struct ice_adapter {
 	struct ice_fdir_prof_info fdir_prof_info[ICE_MAX_PTGS];
 	struct ice_rss_prof_info rss_prof_info[ICE_MAX_PTGS];
 	/* True if DCF state of the associated PF is on */
-	bool dcf_state_on;
+	RTE_ATOMIC(bool) dcf_state_on;
 	/* Set bit if the engine is disabled */
 	unsigned long disabled_engine_mask;
 	struct ice_parser *psr;

index 380ce1a..801cc95 100644
@@ -4687,7 +4687,7 @@ enum i40e_status_code
 			u64 size,
 			u32 alignment)
 {
-	static uint64_t i40e_dma_memzone_id;
+	static RTE_ATOMIC(uint64_t) i40e_dma_memzone_id;
 	const struct rte_memzone *mz = NULL;
 	char z_name[RTE_MEMZONE_NAMESIZE];
 

@@ -4695,7 +4695,7 @@ enum i40e_status_code
 		return I40E_ERR_PARAM;
 
 	snprintf(z_name, sizeof(z_name), "i40e_dma_%" PRIu64,
-		__atomic_fetch_add(&i40e_dma_memzone_id, 1, __ATOMIC_RELAXED));
+		rte_atomic_fetch_add_explicit(&i40e_dma_memzone_id, 1, rte_memory_order_relaxed));
 	mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
 			RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
 	if (!mz)

index 5d25ab4..155f243 100644
@@ -486,7 +486,7 @@
 		}
 
 		/* This barrier is to order loads of different words in the descriptor */
-		rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
+		rte_atomic_thread_fence(rte_memory_order_acquire);
 
 		/* Compute how many status bits were set */
 		for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++) {

@@ -745,7 +745,7 @@
 		 * Use acquire fence to ensure that qword1 which includes DD
 		 * bit is loaded before loading of other descriptor words.
 		 */
-		rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
+		rte_atomic_thread_fence(rte_memory_order_acquire);
 
 		rxd = *rxdp;
 		nb_hold++;

@@ -867,7 +867,7 @@
 		 * Use acquire fence to ensure that qword1 which includes DD
 		 * bit is loaded before loading of other descriptor words.
 		 */
-		rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
+		rte_atomic_thread_fence(rte_memory_order_acquire);
 
 		rxd = *rxdp;
 		nb_hold++;

index d873e30..3a99137 100644
@@ -425,7 +425,7 @@
 		descs[0] =  vld1q_u64((uint64_t *)(rxdp));
 
 		/* Use acquire fence to order loads of descriptor qwords */
-		rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
+		rte_atomic_thread_fence(rte_memory_order_acquire);
 		/* A.2 reload qword0 to make it ordered after qword1 load */
 		descs[3] = vld1q_lane_u64((uint64_t *)(rxdp + 3), descs[3], 0);
 		descs[2] = vld1q_lane_u64((uint64_t *)(rxdp + 2), descs[2], 0);

index 001ff49..3c5fdbe 100644
@@ -44,12 +44,12 @@
 hns3_allocate_dma_mem(struct hns3_hw *hw, struct hns3_cmq_ring *ring,
 		      uint64_t size, uint32_t alignment)
 {
-	static uint64_t hns3_dma_memzone_id;
+	static RTE_ATOMIC(uint64_t) hns3_dma_memzone_id;
 	const struct rte_memzone *mz = NULL;
 	char z_name[RTE_MEMZONE_NAMESIZE];
 
 	snprintf(z_name, sizeof(z_name), "hns3_dma_%" PRIu64,
-		__atomic_fetch_add(&hns3_dma_memzone_id, 1, __ATOMIC_RELAXED));
+		rte_atomic_fetch_add_explicit(&hns3_dma_memzone_id, 1, rte_memory_order_relaxed));
 	mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
 					 RTE_MEMZONE_IOVA_CONTIG, alignment,
 					 RTE_PGSIZE_2M);

@@ -198,8 +198,8 @@
 		hns3_err(hw, "wrong cmd addr(%0x) head (%u, %u-%u)", addr, head,
 			 csq->next_to_use, csq->next_to_clean);
 		if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
-			__atomic_store_n(&hw->reset.disable_cmd, 1,
-					 __ATOMIC_RELAXED);
+			rte_atomic_store_explicit(&hw->reset.disable_cmd, 1,
+					 rte_memory_order_relaxed);
 			hns3_schedule_delayed_reset(HNS3_DEV_HW_TO_ADAPTER(hw));
 		}
 

@@ -313,7 +313,7 @@ static int hns3_cmd_poll_reply(struct hns3_hw *hw)
 		if (hns3_cmd_csq_done(hw))
 			return 0;
 
-		if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED)) {
+		if (rte_atomic_load_explicit(&hw->reset.disable_cmd, rte_memory_order_relaxed)) {
 			hns3_err(hw,
 				 "Don't wait for reply because of disable_cmd");
 			return -EBUSY;

@@ -360,7 +360,7 @@ static int hns3_cmd_poll_reply(struct hns3_hw *hw)
 	int retval;
 	uint32_t ntc;
 
-	if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED))
+	if (rte_atomic_load_explicit(&hw->reset.disable_cmd, rte_memory_order_relaxed))
 		return -EBUSY;
 
 	rte_spinlock_lock(&hw->cmq.csq.lock);

@@ -747,7 +747,7 @@ static int hns3_cmd_poll_reply(struct hns3_hw *hw)
 		ret = -EBUSY;
 		goto err_cmd_init;
 	}
-	__atomic_store_n(&hw->reset.disable_cmd, 0, __ATOMIC_RELAXED);
+	rte_atomic_store_explicit(&hw->reset.disable_cmd, 0, rte_memory_order_relaxed);
 
 	ret = hns3_cmd_query_firmware_version_and_capability(hw);
 	if (ret) {

@@ -790,7 +790,7 @@ static int hns3_cmd_poll_reply(struct hns3_hw *hw)
 	return 0;
 
 err_cmd_init:
-	__atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
+	rte_atomic_store_explicit(&hw->reset.disable_cmd, 1, rte_memory_order_relaxed);
 	return ret;
 }
 

@@ -819,7 +819,7 @@ static int hns3_cmd_poll_reply(struct hns3_hw *hw)
 	if (!hns->is_vf)
 		(void)hns3_firmware_compat_config(hw, false);
 
-	__atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
+	rte_atomic_store_explicit(&hw->reset.disable_cmd, 1, rte_memory_order_relaxed);
 
 	/*
 	 * A delay is added to ensure that the register cleanup operations

index 915e4eb..2f917fe 100644
@@ -648,7 +648,7 @@
 	 * and configured directly to the hardware in the RESET_STAGE_RESTORE
 	 * stage of the reset process.
 	 */
-	if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
+	if (rte_atomic_load_explicit(&hw->reset.resetting, rte_memory_order_relaxed) == 0) {
 		for (i = 0; i < hw->rss_ind_tbl_size; i++)
 			rss_cfg->rss_indirection_tbl[i] =
 							i % hw->alloc_rss_size;

index 9730b9a..327f6fe 100644
@@ -99,7 +99,7 @@ struct hns3_intr_state {
 };
 
 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
-						 uint64_t *levels);
+						 RTE_ATOMIC(uint64_t) *levels);
 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
 				    int on);

@@ -134,7 +134,7 @@ static int hns3_remove_mc_mac_addr(struct hns3_hw *hw,
 {
 	struct hns3_hw *hw = &hns->hw;
 
-	__atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
+	rte_atomic_store_explicit(&hw->reset.disable_cmd, 1, rte_memory_order_relaxed);
 	hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 	*vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 	hw->reset.stats.imp_cnt++;

@@ -148,7 +148,7 @@ static int hns3_remove_mc_mac_addr(struct hns3_hw *hw,
 {
 	struct hns3_hw *hw = &hns->hw;
 
-	__atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
+	rte_atomic_store_explicit(&hw->reset.disable_cmd, 1, rte_memory_order_relaxed);
 	hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 	*vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 	hw->reset.stats.global_cnt++;

@@ -1151,7 +1151,7 @@ static int hns3_remove_mc_mac_addr(struct hns3_hw *hw,
 	 * ensure that the hardware configuration remains unchanged before and
 	 * after reset.
 	 */
-	if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
+	if (rte_atomic_load_explicit(&hw->reset.resetting, rte_memory_order_relaxed) == 0) {
 		hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
 		hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
 	}

@@ -1175,7 +1175,7 @@ static int hns3_remove_mc_mac_addr(struct hns3_hw *hw,
 	 * we will restore configurations to hardware in hns3_restore_vlan_table
 	 * and hns3_restore_vlan_conf later.
 	 */
-	if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
+	if (rte_atomic_load_explicit(&hw->reset.resetting, rte_memory_order_relaxed) == 0) {
 		ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
 		if (ret) {
 			hns3_err(hw, "pvid set fail in pf, ret =%d", ret);

@@ -5059,7 +5059,7 @@ static int hns3_remove_mc_mac_addr(struct hns3_hw *hw,
 	int ret;
 
 	PMD_INIT_FUNC_TRACE();
-	if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
+	if (rte_atomic_load_explicit(&hw->reset.resetting, rte_memory_order_relaxed))
 		return -EBUSY;
 
 	rte_spinlock_lock(&hw->lock);

@@ -5150,7 +5150,7 @@ static int hns3_remove_mc_mac_addr(struct hns3_hw *hw,
 	 * during reset and is required to be released after the reset is
 	 * completed.
 	 */
-	if (__atomic_load_n(&hw->reset.resetting,  __ATOMIC_RELAXED) == 0)
+	if (rte_atomic_load_explicit(&hw->reset.resetting,  rte_memory_order_relaxed) == 0)
 		hns3_dev_release_mbufs(hns);
 
 	ret = hns3_cfg_mac_mode(hw, false);

@@ -5158,7 +5158,7 @@ static int hns3_remove_mc_mac_addr(struct hns3_hw *hw,
 		return ret;
 	hw->mac.link_status = RTE_ETH_LINK_DOWN;
 
-	if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
+	if (rte_atomic_load_explicit(&hw->reset.disable_cmd, rte_memory_order_relaxed) == 0) {
 		hns3_configure_all_mac_addr(hns, true);
 		ret = hns3_reset_all_tqps(hns);
 		if (ret) {

@@ -5184,7 +5184,7 @@ static int hns3_remove_mc_mac_addr(struct hns3_hw *hw,
 	hns3_stop_rxtx_datapath(dev);
 
 	rte_spinlock_lock(&hw->lock);
-	if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
+	if (rte_atomic_load_explicit(&hw->reset.resetting, rte_memory_order_relaxed) == 0) {
 		hns3_tm_dev_stop_proc(hw);
 		hns3_config_mac_tnl_int(hw, false);
 		hns3_stop_tqps(hw);

@@ -5577,7 +5577,7 @@ static int hns3_remove_mc_mac_addr(struct hns3_hw *hw,
 
 	last_req = hns3_get_reset_level(hns, &hw->reset.pending);
 	if (last_req == HNS3_NONE_RESET || last_req < new_req) {
-		__atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
+		rte_atomic_store_explicit(&hw->reset.disable_cmd, 1, rte_memory_order_relaxed);
 		hns3_schedule_delayed_reset(hns);
 		hns3_warn(hw, "High level reset detected, delay do reset");
 		return true;

@@ -5677,7 +5677,7 @@ static int hns3_remove_mc_mac_addr(struct hns3_hw *hw,
 }
 
 static enum hns3_reset_level
-hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
+hns3_get_reset_level(struct hns3_adapter *hns, RTE_ATOMIC(uint64_t) *levels)
 {
 	struct hns3_hw *hw = &hns->hw;
 	enum hns3_reset_level reset_level = HNS3_NONE_RESET;

@@ -5737,7 +5737,7 @@ static int hns3_remove_mc_mac_addr(struct hns3_hw *hw,
 		 * any mailbox handling or command to firmware is only valid
 		 * after hns3_cmd_init is called.
 		 */
-		__atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
+		rte_atomic_store_explicit(&hw->reset.disable_cmd, 1, rte_memory_order_relaxed);
 		hw->reset.stats.request_cnt++;
 		break;
 	case HNS3_IMP_RESET:

@@ -5792,7 +5792,7 @@ static int hns3_remove_mc_mac_addr(struct hns3_hw *hw,
 	 * from table space. Hence, for function reset software intervention is
 	 * required to delete the entries
 	 */
-	if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
+	if (rte_atomic_load_explicit(&hw->reset.disable_cmd, rte_memory_order_relaxed) == 0)
 		hns3_configure_all_mc_mac_addr(hns, true);
 	rte_spinlock_unlock(&hw->lock);
 

@@ -5913,10 +5913,10 @@ static int hns3_remove_mc_mac_addr(struct hns3_hw *hw,
 	 * The interrupt may have been lost. It is necessary to handle
 	 * the interrupt to recover from the error.
 	 */
-	if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
+	if (rte_atomic_load_explicit(&hw->reset.schedule, rte_memory_order_relaxed) ==
 			    SCHEDULE_DEFERRED) {
-		__atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
-				  __ATOMIC_RELAXED);
+		rte_atomic_store_explicit(&hw->reset.schedule, SCHEDULE_REQUESTED,
+				  rte_memory_order_relaxed);
 		hns3_err(hw, "Handling interrupts in delayed tasks");
 		hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
 		reset_level = hns3_get_reset_level(hns, &hw->reset.pending);

@@ -5925,7 +5925,7 @@ static int hns3_remove_mc_mac_addr(struct hns3_hw *hw,
 			hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 		}
 	}
-	__atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
+	rte_atomic_store_explicit(&hw->reset.schedule, SCHEDULE_NONE, rte_memory_order_relaxed);
 
 	/*
 	 * Check if there is any ongoing reset in the hardware. This status can

@@ -6576,7 +6576,7 @@ static int hns3_remove_mc_mac_addr(struct hns3_hw *hw,
 
 	hw->adapter_state = HNS3_NIC_INITIALIZED;
 
-	if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
+	if (rte_atomic_load_explicit(&hw->reset.schedule, rte_memory_order_relaxed) ==
 			    SCHEDULE_PENDING) {
 		hns3_err(hw, "Reschedule reset service after dev_init");
 		hns3_schedule_reset(hns);

index e70c5ff..4c0f076 100644
@@ -401,17 +401,17 @@ enum hns3_schedule {
 
 struct hns3_reset_data {
 	enum hns3_reset_stage stage;
-	uint16_t schedule;
+	RTE_ATOMIC(uint16_t) schedule;
 	/* Reset flag, covering the entire reset process */
-	uint16_t resetting;
+	RTE_ATOMIC(uint16_t) resetting;
 	/* Used to disable sending cmds during reset */
-	uint16_t disable_cmd;
+	RTE_ATOMIC(uint16_t) disable_cmd;
 	/* The reset level being processed */
 	enum hns3_reset_level level;
 	/* Reset level set, each bit represents a reset level */
-	uint64_t pending;
+	RTE_ATOMIC(uint64_t) pending;
 	/* Request reset level set, from interrupt or mailbox */
-	uint64_t request;
+	RTE_ATOMIC(uint64_t) request;
 	int attempts; /* Reset failure retry */
 	int retries;  /* Timeout failure retry in reset_post */
 	/*

@@ -499,7 +499,7 @@ struct hns3_hw {
 	 * by dev_set_link_up() or dev_start().
 	 */
 	bool set_link_down;
-	unsigned int secondary_cnt; /* Number of secondary processes init'd. */
+	RTE_ATOMIC(unsigned int) secondary_cnt; /* Number of secondary processes init'd. */
 	struct hns3_tqp_stats tqp_stats;
 	/* Include Mac stats | Rx stats | Tx stats */
 	struct hns3_mac_stats mac_stats;

@@ -844,7 +844,7 @@ struct hns3_vf {
 	struct hns3_adapter *adapter;
 
 	/* Whether PF support push link status change to VF */
-	uint16_t pf_push_lsc_cap;
+	RTE_ATOMIC(uint16_t) pf_push_lsc_cap;
 
 	/*
 	 * If PF support push link status change, VF still need send request to

@@ -853,7 +853,7 @@ struct hns3_vf {
 	 */
 	uint16_t req_link_info_cnt;
 
-	uint16_t poll_job_started; /* whether poll job is started */
+	RTE_ATOMIC(uint16_t) poll_job_started; /* whether poll job is started */
 };
 
 struct hns3_adapter {

@@ -997,32 +997,32 @@ static inline uint32_t hns3_read_reg(void *base, uint32_t reg)
 	hns3_read_reg((a)->io_base, (reg))
 
 static inline uint64_t
-hns3_atomic_test_bit(unsigned int nr, volatile uint64_t *addr)
+hns3_atomic_test_bit(unsigned int nr, volatile RTE_ATOMIC(uint64_t) *addr)
 {
 	uint64_t res;
 
-	res = (__atomic_load_n(addr, __ATOMIC_RELAXED) & (1UL << nr)) != 0;
+	res = (rte_atomic_load_explicit(addr, rte_memory_order_relaxed) & (1UL << nr)) != 0;
 	return res;
 }
 
 static inline void
-hns3_atomic_set_bit(unsigned int nr, volatile uint64_t *addr)
+hns3_atomic_set_bit(unsigned int nr, volatile RTE_ATOMIC(uint64_t) *addr)
 {
-	__atomic_fetch_or(addr, (1UL << nr), __ATOMIC_RELAXED);
+	rte_atomic_fetch_or_explicit(addr, (1UL << nr), rte_memory_order_relaxed);
 }
 
 static inline void
-hns3_atomic_clear_bit(unsigned int nr, volatile uint64_t *addr)
+hns3_atomic_clear_bit(unsigned int nr, volatile RTE_ATOMIC(uint64_t) *addr)
 {
-	__atomic_fetch_and(addr, ~(1UL << nr), __ATOMIC_RELAXED);
+	rte_atomic_fetch_and_explicit(addr, ~(1UL << nr), rte_memory_order_relaxed);
 }
 
 static inline uint64_t
-hns3_test_and_clear_bit(unsigned int nr, volatile uint64_t *addr)
+hns3_test_and_clear_bit(unsigned int nr, volatile RTE_ATOMIC(uint64_t) *addr)
 {
 	uint64_t mask = (1UL << nr);
 
-	return __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED) & mask;
+	return rte_atomic_fetch_and_explicit(addr, ~mask, rte_memory_order_relaxed) & mask;
 }
 
 int

202 lines not on this page · raw message

index 916bf30..26fa2eb 100644
@@ -2033,7 +2033,7 @@ enum hns3_hw_err_report_type {
 
 static int
 hns3_handle_hw_error(struct hns3_adapter *hns, struct hns3_cmd_desc *desc,
-		     int num, uint64_t *levels,
+		     int num, RTE_ATOMIC(uint64_t) *levels,
 		     enum hns3_hw_err_report_type err_type)
 {
 	const struct hns3_hw_error_desc *err = pf_ras_err_tbl;

@@ -2104,7 +2104,7 @@ enum hns3_hw_err_report_type {
 }
 
 void
-hns3_handle_msix_error(struct hns3_adapter *hns, uint64_t *levels)
+hns3_handle_msix_error(struct hns3_adapter *hns, RTE_ATOMIC(uint64_t) *levels)
 {
 	uint32_t mpf_bd_num, pf_bd_num, bd_num;
 	struct hns3_hw *hw = &hns->hw;

@@ -2151,7 +2151,7 @@ enum hns3_hw_err_report_type {
 }
 
 void
-hns3_handle_ras_error(struct hns3_adapter *hns, uint64_t *levels)
+hns3_handle_ras_error(struct hns3_adapter *hns, RTE_ATOMIC(uint64_t) *levels)
 {
 	uint32_t mpf_bd_num, pf_bd_num, bd_num;
 	struct hns3_hw *hw = &hns->hw;

@@ -2402,7 +2402,7 @@ enum hns3_hw_err_report_type {
 	hw->reset.request = 0;
 	hw->reset.pending = 0;
 	hw->reset.resetting = 0;
-	__atomic_store_n(&hw->reset.disable_cmd, 0, __ATOMIC_RELAXED);
+	rte_atomic_store_explicit(&hw->reset.disable_cmd, 0, rte_memory_order_relaxed);
 	hw->reset.wait_data = rte_zmalloc("wait_data",
 					  sizeof(struct hns3_wait_data), 0);
 	if (!hw->reset.wait_data) {

@@ -2419,8 +2419,8 @@ enum hns3_hw_err_report_type {
 
 	/* Reschedule the reset process after successful initialization */
 	if (hw->adapter_state == HNS3_NIC_UNINITIALIZED) {
-		__atomic_store_n(&hw->reset.schedule, SCHEDULE_PENDING,
-				 __ATOMIC_RELAXED);
+		rte_atomic_store_explicit(&hw->reset.schedule, SCHEDULE_PENDING,
+				 rte_memory_order_relaxed);
 		return;
 	}
 

@@ -2428,15 +2428,15 @@ enum hns3_hw_err_report_type {
 		return;
 
 	/* Schedule restart alarm if it is not scheduled yet */
-	if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
+	if (rte_atomic_load_explicit(&hw->reset.schedule, rte_memory_order_relaxed) ==
 			SCHEDULE_REQUESTED)
 		return;
-	if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
+	if (rte_atomic_load_explicit(&hw->reset.schedule, rte_memory_order_relaxed) ==
 			    SCHEDULE_DEFERRED)
 		rte_eal_alarm_cancel(hw->reset.ops->reset_service, hns);
 
-	__atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
-				 __ATOMIC_RELAXED);
+	rte_atomic_store_explicit(&hw->reset.schedule, SCHEDULE_REQUESTED,
+				 rte_memory_order_relaxed);
 
 	rte_eal_alarm_set(SWITCH_CONTEXT_US, hw->reset.ops->reset_service, hns);
 }

@@ -2453,11 +2453,11 @@ enum hns3_hw_err_report_type {
 		return;
 	}
 
-	if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) !=
+	if (rte_atomic_load_explicit(&hw->reset.schedule, rte_memory_order_relaxed) !=
 			    SCHEDULE_NONE)
 		return;
-	__atomic_store_n(&hw->reset.schedule, SCHEDULE_DEFERRED,
-			 __ATOMIC_RELAXED);
+	rte_atomic_store_explicit(&hw->reset.schedule, SCHEDULE_DEFERRED,
+			 rte_memory_order_relaxed);
 	rte_eal_alarm_set(DEFERRED_SCHED_US, hw->reset.ops->reset_service, hns);
 }
 

@@ -2537,7 +2537,7 @@ enum hns3_hw_err_report_type {
 }
 
 static void
-hns3_clear_reset_level(struct hns3_hw *hw, uint64_t *levels)
+hns3_clear_reset_level(struct hns3_hw *hw, RTE_ATOMIC(uint64_t) *levels)
 {
 	uint64_t merge_cnt = hw->reset.stats.merge_cnt;
 	uint64_t tmp;

@@ -2633,7 +2633,7 @@ enum hns3_hw_err_report_type {
 	 * Regardless of whether the execution is successful or not, the
 	 * flow after execution must be continued.
 	 */
-	if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED))
+	if (rte_atomic_load_explicit(&hw->reset.disable_cmd, rte_memory_order_relaxed))
 		(void)hns3_cmd_init(hw);
 reset_fail:
 	hw->reset.attempts = 0;

@@ -2661,7 +2661,7 @@ enum hns3_hw_err_report_type {
 	int ret;
 
 	if (hw->reset.stage == RESET_STAGE_NONE) {
-		__atomic_store_n(&hns->hw.reset.resetting, 1, __ATOMIC_RELAXED);
+		rte_atomic_store_explicit(&hns->hw.reset.resetting, 1, rte_memory_order_relaxed);
 		hw->reset.stage = RESET_STAGE_DOWN;
 		hns3_report_reset_begin(hw);
 		ret = hw->reset.ops->stop_service(hns);

@@ -2750,7 +2750,7 @@ enum hns3_hw_err_report_type {
 		hns3_notify_reset_ready(hw, false);
 		hns3_clear_reset_level(hw, &hw->reset.pending);
 		hns3_clear_reset_status(hw);
-		__atomic_store_n(&hns->hw.reset.resetting, 0, __ATOMIC_RELAXED);
+		rte_atomic_store_explicit(&hns->hw.reset.resetting, 0, rte_memory_order_relaxed);
 		hw->reset.attempts = 0;
 		hw->reset.stats.success_cnt++;
 		hw->reset.stage = RESET_STAGE_NONE;

@@ -2812,7 +2812,7 @@ enum hns3_hw_err_report_type {
 		hw->reset.mbuf_deferred_free = false;
 	}
 	rte_spinlock_unlock(&hw->lock);
-	__atomic_store_n(&hns->hw.reset.resetting, 0, __ATOMIC_RELAXED);
+	rte_atomic_store_explicit(&hns->hw.reset.resetting, 0, rte_memory_order_relaxed);
 	hw->reset.stage = RESET_STAGE_NONE;
 	hns3_clock_gettime(&tv);
 	timersub(&tv, &hw->reset.start_time, &tv_delta);

index aca1c07..1edb07d 100644
@@ -171,8 +171,8 @@ struct hns3_hw_error_desc {
 };
 
 int hns3_enable_hw_error_intr(struct hns3_adapter *hns, bool en);
-void hns3_handle_msix_error(struct hns3_adapter *hns, uint64_t *levels);
-void hns3_handle_ras_error(struct hns3_adapter *hns, uint64_t *levels);
+void hns3_handle_msix_error(struct hns3_adapter *hns, RTE_ATOMIC(uint64_t) *levels);
+void hns3_handle_ras_error(struct hns3_adapter *hns, RTE_ATOMIC(uint64_t) *levels);
 void hns3_config_mac_tnl_int(struct hns3_hw *hw, bool en);
 void hns3_handle_error(struct hns3_adapter *hns);
 

index 9cdbc16..10c6e3b 100644
@@ -65,7 +65,7 @@
 
 	mbx_time_limit = (uint32_t)hns->mbx_time_limit_ms * US_PER_MS;
 	while (wait_time < mbx_time_limit) {
-		if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED)) {
+		if (rte_atomic_load_explicit(&hw->reset.disable_cmd, rte_memory_order_relaxed)) {
 			hns3_err(hw, "Don't wait for mbx response because of "
 				 "disable_cmd");
 			return -EBUSY;

@@ -382,7 +382,7 @@
 	rte_spinlock_lock(&hw->cmq.crq.lock);
 
 	while (!hns3_cmd_crq_empty(hw)) {
-		if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED)) {
+		if (rte_atomic_load_explicit(&hw->reset.disable_cmd, rte_memory_order_relaxed)) {
 			rte_spinlock_unlock(&hw->cmq.crq.lock);
 			return;
 		}

@@ -457,7 +457,7 @@
 	}
 
 	while (!hns3_cmd_crq_empty(hw)) {
-		if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED)) {
+		if (rte_atomic_load_explicit(&hw->reset.disable_cmd, rte_memory_order_relaxed)) {
 			rte_spinlock_unlock(&hw->cmq.crq.lock);
 			return;
 		}

index 556f194..ba8f8ec 100644
@@ -151,7 +151,7 @@
 	int i;
 
 	if (rte_eal_process_type() == RTE_PROC_SECONDARY ||
-		__atomic_load_n(&hw->secondary_cnt, __ATOMIC_RELAXED) == 0)
+		rte_atomic_load_explicit(&hw->secondary_cnt, rte_memory_order_relaxed) == 0)
 		return;
 
 	if (!mp_req_type_is_valid(type)) {

@@ -277,7 +277,7 @@ void hns3_mp_req_stop_rxtx(struct rte_eth_dev *dev)
 				     ret);
 			return ret;
 		}
-		__atomic_fetch_add(&hw->secondary_cnt, 1, __ATOMIC_RELAXED);
+		rte_atomic_fetch_add_explicit(&hw->secondary_cnt, 1, rte_memory_order_relaxed);
 	} else {
 		ret = hns3_mp_init_primary();
 		if (ret) {

@@ -297,7 +297,7 @@ void hns3_mp_uninit(struct rte_eth_dev *dev)
 	struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 
 	if (rte_eal_process_type() != RTE_PROC_PRIMARY)
-		__atomic_fetch_sub(&hw->secondary_cnt, 1, __ATOMIC_RELAXED);
+		rte_atomic_fetch_sub_explicit(&hw->secondary_cnt, 1, rte_memory_order_relaxed);
 
 	process_data.eth_dev_cnt--;
 	if (process_data.eth_dev_cnt == 0) {

index 7e636a0..73a388b 100644
@@ -4464,7 +4464,7 @@
 	struct hns3_adapter *hns = eth_dev->data->dev_private;
 
 	if (hns->hw.adapter_state == HNS3_NIC_STARTED &&
-	    __atomic_load_n(&hns->hw.reset.resetting, __ATOMIC_RELAXED) == 0) {
+	    rte_atomic_load_explicit(&hns->hw.reset.resetting, rte_memory_order_relaxed) == 0) {
 		eth_dev->rx_pkt_burst = hns3_get_rx_function(eth_dev);
 		eth_dev->rx_descriptor_status = hns3_dev_rx_descriptor_status;
 		eth_dev->tx_pkt_burst = hw->set_link_down ?

@@ -4530,7 +4530,7 @@
 
 	rte_spinlock_lock(&hw->lock);
 
-	if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
+	if (rte_atomic_load_explicit(&hw->reset.resetting, rte_memory_order_relaxed)) {
 		hns3_err(hw, "fail to start Rx queue during resetting.");
 		rte_spinlock_unlock(&hw->lock);
 		return -EIO;

@@ -4586,7 +4586,7 @@
 
 	rte_spinlock_lock(&hw->lock);
 
-	if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
+	if (rte_atomic_load_explicit(&hw->reset.resetting, rte_memory_order_relaxed)) {
 		hns3_err(hw, "fail to stop Rx queue during resetting.");
 		rte_spinlock_unlock(&hw->lock);
 		return -EIO;

@@ -4615,7 +4615,7 @@
 
 	rte_spinlock_lock(&hw->lock);
 
-	if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
+	if (rte_atomic_load_explicit(&hw->reset.resetting, rte_memory_order_relaxed)) {
 		hns3_err(hw, "fail to start Tx queue during resetting.");
 		rte_spinlock_unlock(&hw->lock);
 		return -EIO;

@@ -4648,7 +4648,7 @@
 
 	rte_spinlock_lock(&hw->lock);
 
-	if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
+	if (rte_atomic_load_explicit(&hw->reset.resetting, rte_memory_order_relaxed)) {
 		hns3_err(hw, "fail to stop Tx queue during resetting.");
 		rte_spinlock_unlock(&hw->lock);
 		return -EIO;

index d969164..92a6685 100644
@@ -1051,7 +1051,7 @@
 	if (error == NULL)
 		return -EINVAL;
 
-	if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
+	if (rte_atomic_load_explicit(&hw->reset.resetting, rte_memory_order_relaxed)) {
 		error->type = RTE_TM_ERROR_TYPE_UNSPECIFIED;
 		error->message = "device is resetting";
 		/* don't goto fail_clear, user may try later */

@@ -1141,7 +1141,7 @@
 	if (error == NULL)
 		return -EINVAL;
 
-	if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
+	if (rte_atomic_load_explicit(&hw->reset.resetting, rte_memory_order_relaxed)) {
 		error->type = RTE_TM_ERROR_TYPE_UNSPECIFIED;
 		error->message = "device is resetting";
 		return -EBUSY;

index c7b3480..43f06fd 100644
@@ -107,7 +107,7 @@ struct bnxt_cp_ring_info {
 
 /**
  * Check validity of a completion ring entry. If the entry is valid, include a
- * C11 __ATOMIC_ACQUIRE fence to ensure that subsequent loads of fields in the
+ * C11 rte_memory_order_acquire fence to ensure that subsequent loads of fields in the
  * completion are not hoisted by the compiler or by the CPU to come before the
  * loading of the "valid" field.
  *

@@ -130,7 +130,7 @@ struct bnxt_cp_ring_info {
 	expected = !(raw_cons & ring_size);
 	valid = !!(rte_le_to_cpu_32(c->info3_v) & CMPL_BASE_V);
 	if (valid == expected) {
-		rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
+		rte_atomic_thread_fence(rte_memory_order_acquire);
 		return true;
 	}
 	return false;

index 77bc382..36e0ac3 100644
@@ -40,7 +40,7 @@ struct bnxt_rx_queue {
 	struct bnxt_rx_ring_info	*rx_ring;
 	struct bnxt_cp_ring_info	*cp_ring;
 	struct rte_mbuf			fake_mbuf;
-	uint64_t			rx_mbuf_alloc_fail;
+	RTE_ATOMIC(uint64_t)		rx_mbuf_alloc_fail;
 	uint8_t				need_realloc;
 	const struct rte_memzone *mz;
 };

index 3542975..ca5d2c6 100644
@@ -49,7 +49,8 @@ static inline int bnxt_alloc_rx_data(struct bnxt_rx_queue *rxq,
 	rx_buf = &rxr->rx_buf_ring[prod];
 	mbuf = __bnxt_alloc_rx_data(rxq->mb_pool);
 	if (!mbuf) {
-		__atomic_fetch_add(&rxq->rx_mbuf_alloc_fail, 1, __ATOMIC_RELAXED);
+		rte_atomic_fetch_add_explicit(&rxq->rx_mbuf_alloc_fail, 1,
+		    rte_memory_order_relaxed);
 		/* If buff has failed already, setting this again won't hurt */
 		rxq->need_realloc = 1;
 		return -ENOMEM;

@@ -86,7 +87,8 @@ static inline int bnxt_alloc_ag_data(struct bnxt_rx_queue *rxq,
 
 	mbuf = __bnxt_alloc_rx_data(rxq->mb_pool);
 	if (!mbuf) {
-		__atomic_fetch_add(&rxq->rx_mbuf_alloc_fail, 1, __ATOMIC_RELAXED);
+		rte_atomic_fetch_add_explicit(&rxq->rx_mbuf_alloc_fail, 1,
+		    rte_memory_order_relaxed);
 		/* If buff has failed already, setting this again won't hurt */
 		rxq->need_realloc = 1;
 		return -ENOMEM;

@@ -465,7 +467,8 @@ static inline struct rte_mbuf *bnxt_tpa_end(
 	struct rte_mbuf *new_data = __bnxt_alloc_rx_data(rxq->mb_pool);
 	RTE_ASSERT(new_data != NULL);
 	if (!new_data) {
-		__atomic_fetch_add(&rxq->rx_mbuf_alloc_fail, 1, __ATOMIC_RELAXED);
+		rte_atomic_fetch_add_explicit(&rxq->rx_mbuf_alloc_fail, 1,
+		    rte_memory_order_relaxed);
 		return NULL;
 	}
 	tpa_info->mbuf = new_data;

@@ -1677,8 +1680,8 @@ int bnxt_init_one_rx_ring(struct bnxt_rx_queue *rxq)
 				rxr->tpa_info[i].mbuf =
 					__bnxt_alloc_rx_data(rxq->mb_pool);
 				if (!rxr->tpa_info[i].mbuf) {
-					__atomic_fetch_add(&rxq->rx_mbuf_alloc_fail, 1,
-							__ATOMIC_RELAXED);
+					rte_atomic_fetch_add_explicit(&rxq->rx_mbuf_alloc_fail, 1,
+							rte_memory_order_relaxed);
 					return -ENOMEM;
 				}
 			}

index 775400f..04864e0 100644
@@ -240,7 +240,7 @@
 		rxcmp1[0] = vld1q_u32((void *)&cpr->cp_desc_ring[cons + 1]);
 
 		/* Use acquire fence to order loads of descriptor words. */
-		rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
+		rte_atomic_thread_fence(rte_memory_order_acquire);
 		/* Reload lower 64b of descriptors to make it ordered after info3_v. */
 		rxcmp1[3] = vreinterpretq_u32_u64(vld1q_lane_u64
 				((void *)&cpr->cp_desc_ring[cons + 7],

index 6a6feab..479f819 100644
@@ -663,7 +663,7 @@ static int bnxt_stats_get_ext(struct rte_eth_dev *eth_dev,
 
 		bnxt_fill_rte_eth_stats_ext(bnxt_stats, &ring_stats, i, true);
 		bnxt_stats->rx_nombuf +=
-				__atomic_load_n(&rxq->rx_mbuf_alloc_fail, __ATOMIC_RELAXED);
+		    rte_atomic_load_explicit(&rxq->rx_mbuf_alloc_fail, rte_memory_order_relaxed);
 	}
 
 	num_q_stats = RTE_MIN(bp->tx_cp_nr_rings,

@@ -724,7 +724,7 @@ int bnxt_stats_get_op(struct rte_eth_dev *eth_dev,
 
 		bnxt_fill_rte_eth_stats(bnxt_stats, &ring_stats, i, true);
 		bnxt_stats->rx_nombuf +=
-				__atomic_load_n(&rxq->rx_mbuf_alloc_fail, __ATOMIC_RELAXED);
+		    rte_atomic_load_explicit(&rxq->rx_mbuf_alloc_fail, rte_memory_order_relaxed);
 	}
 
 	num_q_stats = RTE_MIN(bp->tx_cp_nr_rings,

index ef19aa1..5b47e22 100644
@@ -300,8 +300,9 @@ struct rte_cpfl_xstats_name_off {
 
 	for (i = 0; i < dev->data->nb_rx_queues; i++) {
 		cpfl_rxq = dev->data->rx_queues[i];
-		mbuf_alloc_failed += __atomic_load_n(&cpfl_rxq->base.rx_stats.mbuf_alloc_failed,
-						     __ATOMIC_RELAXED);
+		mbuf_alloc_failed +=
+		    rte_atomic_load_explicit(&cpfl_rxq->base.rx_stats.mbuf_alloc_failed,
+		    rte_memory_order_relaxed);
 	}
 
 	return mbuf_alloc_failed;

@@ -349,7 +350,8 @@ struct rte_cpfl_xstats_name_off {
 
 	for (i = 0; i < dev->data->nb_rx_queues; i++) {
 		cpfl_rxq = dev->data->rx_queues[i];
-		__atomic_store_n(&cpfl_rxq->base.rx_stats.mbuf_alloc_failed, 0, __ATOMIC_RELAXED);
+		rte_atomic_store_explicit(&cpfl_rxq->base.rx_stats.mbuf_alloc_failed, 0,
+		    rte_memory_order_relaxed);
 	}
 }
 

index 268a130..4833180 100644
@@ -116,7 +116,7 @@ struct xsk_umem_info {
 	const struct rte_memzone *mz;
 	struct rte_mempool *mb_pool;
 	void *buffer;
-	uint8_t refcnt;
+	RTE_ATOMIC(uint8_t) refcnt;
 	uint32_t max_xsks;
 };
 

@@ -995,7 +995,8 @@ static int link_xdp_prog_with_dev(int ifindex, int fd, __u32 flags)
 			break;
 		xsk_socket__delete(rxq->xsk);
 
-		if (__atomic_fetch_sub(&rxq->umem->refcnt, 1, __ATOMIC_ACQUIRE) - 1 == 0)
+		if (rte_atomic_fetch_sub_explicit(&rxq->umem->refcnt, 1,
+		    rte_memory_order_acquire) - 1 == 0)
 			xdp_umem_destroy(rxq->umem);
 
 		/* free pkt_tx_queue */

@@ -1097,8 +1098,8 @@ static inline uintptr_t get_base_addr(struct rte_mempool *mp, uint64_t *align)
 					ret = -1;
 					goto out;
 				}
-				if (__atomic_load_n(&internals->rx_queues[i].umem->refcnt,
-						    __ATOMIC_ACQUIRE)) {
+				if (rte_atomic_load_explicit(&internals->rx_queues[i].umem->refcnt,
+						    rte_memory_order_acquire)) {
 					*umem = internals->rx_queues[i].umem;
 					goto out;
 				}

@@ -1131,11 +1132,11 @@ xsk_umem_info *xdp_umem_configure(struct pmd_internals *internals,
 			return NULL;
 
 		if (umem != NULL &&
-			__atomic_load_n(&umem->refcnt, __ATOMIC_ACQUIRE) <
+			rte_atomic_load_explicit(&umem->refcnt, rte_memory_order_acquire) <
 					umem->max_xsks) {
 			AF_XDP_LOG(INFO, "%s,qid%i sharing UMEM\n",
 					internals->if_name, rxq->xsk_queue_idx);
-			__atomic_fetch_add(&umem->refcnt, 1, __ATOMIC_ACQUIRE);
+			rte_atomic_fetch_add_explicit(&umem->refcnt, 1, rte_memory_order_acquire);
 		}
 	}
 

@@ -1177,7 +1178,7 @@ xsk_umem_info *xdp_umem_configure(struct pmd_internals *internals,
 						mb_pool->name, umem->max_xsks);
 		}
 
-		__atomic_store_n(&umem->refcnt, 1, __ATOMIC_RELEASE);
+		rte_atomic_store_explicit(&umem->refcnt, 1, rte_memory_order_release);
 	}
 
 	return umem;

@@ -1606,7 +1607,8 @@ struct msg_internal {
 	if (rxq->umem == NULL)
 		return -ENOMEM;
 	txq->umem = rxq->umem;
-	reserve_before = __atomic_load_n(&rxq->umem->refcnt, __ATOMIC_ACQUIRE) <= 1;
+	reserve_before = rte_atomic_load_explicit(&rxq->umem->refcnt,
+	    rte_memory_order_acquire) <= 1;
 
 #if defined(XDP_UMEM_UNALIGNED_CHUNK_FLAG)
 	ret = rte_pktmbuf_alloc_bulk(rxq->umem->mb_pool, fq_bufs, reserve_size);

@@ -1723,7 +1725,7 @@ struct msg_internal {
 out_xsk:
 	xsk_socket__delete(rxq->xsk);
 out_umem:
-	if (__atomic_fetch_sub(&rxq->umem->refcnt, 1, __ATOMIC_ACQUIRE) - 1 == 0)
+	if (rte_atomic_fetch_sub_explicit(&rxq->umem->refcnt, 1, rte_memory_order_acquire) - 1 == 0)
 		xdp_umem_destroy(rxq->umem);
 
 	return ret;

index ecf95cd..9422042 100644
@@ -98,7 +98,7 @@
 	 * This adds an extra local variable, but almost halves the
 	 * number of PCIe writes.
 	 */
-	val = __atomic_load_n(droq->pkts_sent_ism, __ATOMIC_RELAXED);
+	val = rte_atomic_load_explicit(droq->pkts_sent_ism, rte_memory_order_relaxed);
 
 	new_pkts = val - droq->pkts_sent_prev;
 	droq->pkts_sent_prev = val;

@@ -111,7 +111,8 @@
 		rte_mb();
 
 		rte_write64(OTX2_SDP_REQUEST_ISM, droq->pkts_sent_reg);
-		while (__atomic_load_n(droq->pkts_sent_ism, __ATOMIC_RELAXED) >= val) {
+		while (rte_atomic_load_explicit(droq->pkts_sent_ism,
+		    rte_memory_order_relaxed) >= val) {
 			rte_write64(OTX2_SDP_REQUEST_ISM, droq->pkts_sent_reg);
 			rte_mb();
 		}

index 233c8aa..e093140 100644
@@ -15,7 +15,7 @@
 	 * This adds an extra local variable, but almost halves the
 	 * number of PCIe writes.
 	 */
-	val = __atomic_load_n(iq->inst_cnt_ism, __ATOMIC_RELAXED);
+	val = rte_atomic_load_explicit(iq->inst_cnt_ism, rte_memory_order_relaxed);
 	iq->inst_cnt += val - iq->inst_cnt_prev;
 	iq->inst_cnt_prev = val;
 

@@ -27,7 +27,8 @@
 		rte_mb();
 
 		rte_write64(OTX2_SDP_REQUEST_ISM, iq->inst_cnt_reg);
-		while (__atomic_load_n(iq->inst_cnt_ism, __ATOMIC_RELAXED) >= val) {
+		while (rte_atomic_load_explicit(iq->inst_cnt_ism,
+		    rte_memory_order_relaxed) >= val) {
 			rte_write64(OTX2_SDP_REQUEST_ISM, iq->inst_cnt_reg);
 			rte_mb();
 		}

index 39f357e..39b28de 100644
@@ -150,10 +150,10 @@
 	rte_write64(ism_addr, (uint8_t *)otx_ep->hw_addr +
 		    CNXK_EP_R_IN_CNTS_ISM(iq_no));
 	iq->inst_cnt_ism =
-		(uint32_t *)((uint8_t *)otx_ep->ism_buffer_mz->addr
+		(uint32_t __rte_atomic *)((uint8_t *)otx_ep->ism_buffer_mz->addr
 			     + CNXK_EP_IQ_ISM_OFFSET(iq_no));
 	otx_ep_err("SDP_R[%d] INST Q ISM virt: %p, dma: 0x%" PRIX64, iq_no,
-		   (void *)iq->inst_cnt_ism, ism_addr);
+		   (void *)(uintptr_t)iq->inst_cnt_ism, ism_addr);
 	*iq->inst_cnt_ism = 0;
 	iq->inst_cnt_prev = 0;
 	iq->partial_ih = ((uint64_t)otx_ep->pkind) << 36;

@@ -235,10 +235,10 @@
 	rte_write64(ism_addr, (uint8_t *)otx_ep->hw_addr +
 		    CNXK_EP_R_OUT_CNTS_ISM(oq_no));
 	droq->pkts_sent_ism =
-		(uint32_t *)((uint8_t *)otx_ep->ism_buffer_mz->addr
+		(uint32_t __rte_atomic *)((uint8_t *)otx_ep->ism_buffer_mz->addr
 			     + CNXK_EP_OQ_ISM_OFFSET(oq_no));
 	otx_ep_err("SDP_R[%d] OQ ISM virt: %p dma: 0x%" PRIX64,
-		    oq_no, (void *)droq->pkts_sent_ism, ism_addr);
+		    oq_no, (void *)(uintptr_t)droq->pkts_sent_ism, ism_addr);
 	*droq->pkts_sent_ism = 0;
 	droq->pkts_sent_prev = 0;
 

index 25e0e5a..2aeebb4 100644
@@ -300,10 +300,10 @@ static int otx2_vf_enable_rxq_intr(struct otx_ep_device *otx_epvf,
 	oct_ep_write64(ism_addr, (uint8_t *)otx_ep->hw_addr +
 		    SDP_VF_R_IN_CNTS_ISM(iq_no));
 	iq->inst_cnt_ism =
-		(uint32_t *)((uint8_t *)otx_ep->ism_buffer_mz->addr
+		(uint32_t __rte_atomic *)((uint8_t *)otx_ep->ism_buffer_mz->addr
 			     + OTX2_EP_IQ_ISM_OFFSET(iq_no));
 	otx_ep_err("SDP_R[%d] INST Q ISM virt: %p, dma: 0x%x", iq_no,
-		   (void *)iq->inst_cnt_ism,
+		   (void *)(uintptr_t)iq->inst_cnt_ism,
 		   (unsigned int)ism_addr);
 	*iq->inst_cnt_ism = 0;
 	iq->inst_cnt_prev = 0;

@@ -386,10 +386,10 @@ static int otx2_vf_enable_rxq_intr(struct otx_ep_device *otx_epvf,
 	oct_ep_write64(ism_addr, (uint8_t *)otx_ep->hw_addr +
 		    SDP_VF_R_OUT_CNTS_ISM(oq_no));
 	droq->pkts_sent_ism =
-		(uint32_t *)((uint8_t *)otx_ep->ism_buffer_mz->addr
+		(uint32_t __rte_atomic *)((uint8_t *)otx_ep->ism_buffer_mz->addr
 			     + OTX2_EP_OQ_ISM_OFFSET(oq_no));
 	otx_ep_err("SDP_R[%d] OQ ISM virt: %p, dma: 0x%x", oq_no,
-		   (void *)droq->pkts_sent_ism,
+		   (void *)(uintptr_t)droq->pkts_sent_ism,
 		   (unsigned int)ism_addr);
 	*droq->pkts_sent_ism = 0;
 	droq->pkts_sent_prev = 0;

index 7776940..73eb0c9 100644
@@ -218,7 +218,7 @@ struct otx_ep_iq_config {
  */
 struct otx_ep_instr_queue {
 	/* Location in memory updated by SDP ISM */
-	uint32_t *inst_cnt_ism;
+	RTE_ATOMIC(uint32_t) *inst_cnt_ism;
 	struct rte_mbuf **mbuf_list;
 	/* Pointer to the Virtual Base addr of the input ring. */
 	uint8_t *base_addr;

@@ -413,7 +413,7 @@ struct otx_ep_droq {
 	uint8_t ism_ena;
 
 	/* Pointer to host memory copy of output packet count, set by ISM */
-	uint32_t *pkts_sent_ism;
+	RTE_ATOMIC(uint32_t) *pkts_sent_ism;
 	uint32_t pkts_sent_prev;
 
 	/* Statistics for this DROQ. */

index 59144e0..eb2d8c1 100644
@@ -475,7 +475,8 @@
 		rte_mb();
 
 		rte_write64(OTX2_SDP_REQUEST_ISM, iq->inst_cnt_reg);
-		while (__atomic_load_n(iq->inst_cnt_ism, __ATOMIC_RELAXED) >= val) {
+		while (rte_atomic_load_explicit(iq->inst_cnt_ism,
+		    rte_memory_order_relaxed) >= val) {
 			rte_write64(OTX2_SDP_REQUEST_ISM, iq->inst_cnt_reg);
 			rte_mb();
 		}

@@ -871,7 +872,8 @@
 		rte_mb();
 
 		rte_write64(OTX2_SDP_REQUEST_ISM, droq->pkts_sent_reg);
-		while (__atomic_load_n(droq->pkts_sent_ism, __ATOMIC_RELAXED) >= val) {
+		while (rte_atomic_load_explicit(droq->pkts_sent_ism,
+		    rte_memory_order_relaxed) >= val) {
 			rte_write64(OTX2_SDP_REQUEST_ISM, droq->pkts_sent_reg);
 			rte_mb();
 		}

index bec54fd..64d1666 100644
@@ -31,7 +31,7 @@
 /* Useful in stopping/closing event device if no of
  * eth ports are using it.
  */
-uint16_t evdev_refcnt;
+RTE_ATOMIC(uint16_t) evdev_refcnt;
 
 #define OCTEONTX_QLM_MODE_SGMII  7
 #define OCTEONTX_QLM_MODE_XFI   12

@@ -559,7 +559,7 @@ enum octeontx_link_speed {
 		return 0;
 
 	/* Stopping/closing event device once all eth ports are closed. */
-	if (__atomic_fetch_sub(&evdev_refcnt, 1, __ATOMIC_ACQUIRE) - 1 == 0) {
+	if (rte_atomic_fetch_sub_explicit(&evdev_refcnt, 1, rte_memory_order_acquire) - 1 == 0) {
 		rte_event_dev_stop(nic->evdev);
 		rte_event_dev_close(nic->evdev);
 	}

@@ -1593,7 +1593,7 @@ static void build_xstat_names(struct rte_eth_xstat_name *xstat_names)
 	nic->pko_vfid = pko_vfid;
 	nic->port_id = port;
 	nic->evdev = evdev;
-	__atomic_fetch_add(&evdev_refcnt, 1, __ATOMIC_ACQUIRE);
+	rte_atomic_fetch_add_explicit(&evdev_refcnt, 1, rte_memory_order_acquire);
 
 	res = octeontx_port_open(nic);
 	if (res < 0)

@@ -1844,7 +1844,7 @@ static void build_xstat_names(struct rte_eth_xstat_name *xstat_names)
 		}
 	}
 
-	__atomic_store_n(&evdev_refcnt, 0, __ATOMIC_RELEASE);
+	rte_atomic_store_explicit(&evdev_refcnt, 0, rte_memory_order_release);
 	/*
 	 * Do 1:1 links for ports & queues. All queues would be mapped to
 	 * one port. If there are more ports than queues, then some ports

index b709e26..8588b88 100644
@@ -55,7 +55,7 @@ void cxgbe_clip_release(struct rte_eth_dev *dev, struct clip_entry *ce)
 	int ret;
 
 	t4_os_lock(&ce->lock);
-	if (__atomic_fetch_sub(&ce->refcnt, 1, __ATOMIC_RELAXED) - 1 == 0) {
+	if (rte_atomic_fetch_sub_explicit(&ce->refcnt, 1, rte_memory_order_relaxed) - 1 == 0) {
 		ret = clip6_release_mbox(dev, ce->addr);
 		if (ret)
 			dev_debug(adap, "CLIP FW DEL CMD failed: %d", ret);

@@ -79,7 +79,7 @@ static struct clip_entry *find_or_alloc_clipe(struct clip_tbl *c,
 	unsigned int clipt_size = c->clipt_size;
 
 	for (e = &c->cl_list[0], end = &c->cl_list[clipt_size]; e != end; ++e) {
-		if (__atomic_load_n(&e->refcnt, __ATOMIC_RELAXED) == 0) {
+		if (rte_atomic_load_explicit(&e->refcnt, rte_memory_order_relaxed) == 0) {
 			if (!first_free)
 				first_free = e;
 		} else {

@@ -114,12 +114,12 @@ static struct clip_entry *t4_clip_alloc(struct rte_eth_dev *dev,
 	ce = find_or_alloc_clipe(ctbl, lip);
 	if (ce) {
 		t4_os_lock(&ce->lock);
-		if (__atomic_load_n(&ce->refcnt, __ATOMIC_RELAXED) == 0) {
+		if (rte_atomic_load_explicit(&ce->refcnt, rte_memory_order_relaxed) == 0) {
 			rte_memcpy(ce->addr, lip, sizeof(ce->addr));
 			if (v6) {
 				ce->type = FILTER_TYPE_IPV6;
-				__atomic_store_n(&ce->refcnt, 1,
-						 __ATOMIC_RELAXED);
+				rte_atomic_store_explicit(&ce->refcnt, 1,
+						 rte_memory_order_relaxed);
 				ret = clip6_get_mbox(dev, lip);
 				if (ret)
 					dev_debug(adap,

@@ -129,7 +129,7 @@ static struct clip_entry *t4_clip_alloc(struct rte_eth_dev *dev,
 				ce->type = FILTER_TYPE_IPV4;
 			}
 		} else {
-			__atomic_fetch_add(&ce->refcnt, 1, __ATOMIC_RELAXED);
+			rte_atomic_fetch_add_explicit(&ce->refcnt, 1, rte_memory_order_relaxed);
 		}
 		t4_os_unlock(&ce->lock);
 	}

index 3b2be66..439fcf6 100644
@@ -13,7 +13,7 @@ struct clip_entry {
 	enum filter_type type;       /* entry type */
 	u32 addr[4];                 /* IPV4 or IPV6 address */
 	rte_spinlock_t lock;         /* entry lock */
-	u32 refcnt;                  /* entry reference count */
+	RTE_ATOMIC(u32) refcnt;                  /* entry reference count */
 };
 
 struct clip_tbl {

index c479454..2ed21f2 100644
@@ -418,15 +418,15 @@ void cxgbe_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid,
 
 	if (t->tid_tab[tid]) {
 		t->tid_tab[tid] = NULL;
-		__atomic_fetch_sub(&t->conns_in_use, 1, __ATOMIC_RELAXED);
+		rte_atomic_fetch_sub_explicit(&t->conns_in_use, 1, rte_memory_order_relaxed);
 		if (t->hash_base && tid >= t->hash_base) {
 			if (family == FILTER_TYPE_IPV4)
-				__atomic_fetch_sub(&t->hash_tids_in_use, 1,
-						   __ATOMIC_RELAXED);
+				rte_atomic_fetch_sub_explicit(&t->hash_tids_in_use, 1,
+						   rte_memory_order_relaxed);
 		} else {
 			if (family == FILTER_TYPE_IPV4)
-				__atomic_fetch_sub(&t->tids_in_use, 1,
-						   __ATOMIC_RELAXED);
+				rte_atomic_fetch_sub_explicit(&t->tids_in_use, 1,
+						   rte_memory_order_relaxed);
 		}
 	}
 

@@ -448,15 +448,15 @@ void cxgbe_insert_tid(struct tid_info *t, void *data, unsigned int tid,
 	t->tid_tab[tid] = data;
 	if (t->hash_base && tid >= t->hash_base) {
 		if (family == FILTER_TYPE_IPV4)
-			__atomic_fetch_add(&t->hash_tids_in_use, 1,
-					   __ATOMIC_RELAXED);
+			rte_atomic_fetch_add_explicit(&t->hash_tids_in_use, 1,
+					   rte_memory_order_relaxed);
 	} else {
 		if (family == FILTER_TYPE_IPV4)
-			__atomic_fetch_add(&t->tids_in_use, 1,
-					   __ATOMIC_RELAXED);
+			rte_atomic_fetch_add_explicit(&t->tids_in_use, 1,
+					   rte_memory_order_relaxed);
 	}
 
-	__atomic_fetch_add(&t->conns_in_use, 1, __ATOMIC_RELAXED);
+	rte_atomic_fetch_add_explicit(&t->conns_in_use, 1, rte_memory_order_relaxed);
 }
 
 /**

index 33697c7..48a5ec0 100644
@@ -60,10 +60,10 @@ struct tid_info {
 	unsigned int atids_in_use;
 
 	/* TIDs in the TCAM */
-	u32 tids_in_use;
+	RTE_ATOMIC(u32) tids_in_use;
 	/* TIDs in the HASH */
-	u32 hash_tids_in_use;
-	u32 conns_in_use;
+	RTE_ATOMIC(u32) hash_tids_in_use;
+	RTE_ATOMIC(u32) conns_in_use;
 
 	rte_spinlock_t atid_lock __rte_cache_aligned;
 	rte_spinlock_t ftid_lock;

index 21f4019..ecb5fec 100644
@@ -14,8 +14,8 @@
  */
 void cxgbe_l2t_release(struct l2t_entry *e)
 {
-	if (__atomic_load_n(&e->refcnt, __ATOMIC_RELAXED) != 0)
-		__atomic_fetch_sub(&e->refcnt, 1, __ATOMIC_RELAXED);
+	if (rte_atomic_load_explicit(&e->refcnt, rte_memory_order_relaxed) != 0)
+		rte_atomic_fetch_sub_explicit(&e->refcnt, 1, rte_memory_order_relaxed);
 }
 
 /**

@@ -112,7 +112,7 @@ static struct l2t_entry *find_or_alloc_l2e(struct l2t_data *d, u16 vlan,
 	struct l2t_entry *first_free = NULL;
 
 	for (e = &d->l2tab[0], end = &d->l2tab[d->l2t_size]; e != end; ++e) {
-		if (__atomic_load_n(&e->refcnt, __ATOMIC_RELAXED) == 0) {
+		if (rte_atomic_load_explicit(&e->refcnt, rte_memory_order_relaxed) == 0) {
 			if (!first_free)
 				first_free = e;
 		} else {

@@ -151,18 +151,18 @@ static struct l2t_entry *t4_l2t_alloc_switching(struct rte_eth_dev *dev,
 	e = find_or_alloc_l2e(d, vlan, port, eth_addr);
 	if (e) {
 		t4_os_lock(&e->lock);
-		if (__atomic_load_n(&e->refcnt, __ATOMIC_RELAXED) == 0) {
+		if (rte_atomic_load_explicit(&e->refcnt, rte_memory_order_relaxed) == 0) {
 			e->state = L2T_STATE_SWITCHING;
 			e->vlan = vlan;
 			e->lport = port;
 			rte_memcpy(e->dmac, eth_addr, RTE_ETHER_ADDR_LEN);
-			__atomic_store_n(&e->refcnt, 1, __ATOMIC_RELAXED);
+			rte_atomic_store_explicit(&e->refcnt, 1, rte_memory_order_relaxed);
 			ret = write_l2e(dev, e, 0, !L2T_LPBK, !L2T_ARPMISS);
 			if (ret < 0)
 				dev_debug(adap, "Failed to write L2T entry: %d",
 					  ret);
 		} else {
-			__atomic_fetch_add(&e->refcnt, 1, __ATOMIC_RELAXED);
+			rte_atomic_fetch_add_explicit(&e->refcnt, 1, rte_memory_order_relaxed);
 		}
 		t4_os_unlock(&e->lock);
 	}

index e4c0ebe..67d0197 100644
@@ -30,7 +30,7 @@ struct l2t_entry {
 	u8  lport;                  /* destination port */
 	u8  dmac[RTE_ETHER_ADDR_LEN];   /* destination MAC address */
 	rte_spinlock_t lock;        /* entry lock */
-	u32 refcnt;                 /* entry reference count */
+	RTE_ATOMIC(u32) refcnt;                 /* entry reference count */
 };
 
 struct l2t_data {

index 8e0da9c..79a7daa 100644
@@ -76,7 +76,7 @@ int cxgbe_mpstcam_alloc(struct port_info *pi, const u8 *eth_addr,
 	t4_os_write_lock(&mpstcam->lock);
 	entry = cxgbe_mpstcam_lookup(adap->mpstcam, eth_addr, mask);
 	if (entry) {
-		__atomic_fetch_add(&entry->refcnt, 1, __ATOMIC_RELAXED);
+		rte_atomic_fetch_add_explicit(&entry->refcnt, 1, rte_memory_order_relaxed);
 		t4_os_write_unlock(&mpstcam->lock);
 		return entry->idx;
 	}

@@ -98,7 +98,7 @@ int cxgbe_mpstcam_alloc(struct port_info *pi, const u8 *eth_addr,
 	entry = &mpstcam->entry[ret];
 	memcpy(entry->eth_addr, eth_addr, RTE_ETHER_ADDR_LEN);
 	memcpy(entry->mask, mask, RTE_ETHER_ADDR_LEN);
-	__atomic_store_n(&entry->refcnt, 1, __ATOMIC_RELAXED);
+	rte_atomic_store_explicit(&entry->refcnt, 1, rte_memory_order_relaxed);
 	entry->state = MPS_ENTRY_USED;
 
 	if (cxgbe_update_free_idx(mpstcam))

@@ -147,7 +147,7 @@ int cxgbe_mpstcam_modify(struct port_info *pi, int idx, const u8 *addr)
 	 * provided value is -1
 	 */
 	if (entry->state == MPS_ENTRY_UNUSED) {
-		__atomic_store_n(&entry->refcnt, 1, __ATOMIC_RELAXED);
+		rte_atomic_store_explicit(&entry->refcnt, 1, rte_memory_order_relaxed);
 		entry->state = MPS_ENTRY_USED;
 	}
 

@@ -165,7 +165,7 @@ static inline void reset_mpstcam_entry(struct mps_tcam_entry *entry)
 {
 	memset(entry->eth_addr, 0, RTE_ETHER_ADDR_LEN);
 	memset(entry->mask, 0, RTE_ETHER_ADDR_LEN);
-	__atomic_store_n(&entry->refcnt, 0, __ATOMIC_RELAXED);
+	rte_atomic_store_explicit(&entry->refcnt, 0, rte_memory_order_relaxed);
 	entry->state = MPS_ENTRY_UNUSED;
 }
 

@@ -190,12 +190,13 @@ int cxgbe_mpstcam_remove(struct port_info *pi, u16 idx)
 		return -EINVAL;
 	}
 
-	if (__atomic_load_n(&entry->refcnt, __ATOMIC_RELAXED) == 1)
+	if (rte_atomic_load_explicit(&entry->refcnt, rte_memory_order_relaxed) == 1)
 		ret = t4_free_raw_mac_filt(adap, pi->viid, entry->eth_addr,
 					   entry->mask, idx, 1, pi->port_id,
 					   false);
 	else
-		ret = __atomic_fetch_sub(&entry->refcnt, 1, __ATOMIC_RELAXED) - 1;
+		ret = rte_atomic_fetch_sub_explicit(&entry->refcnt, 1,
+		    rte_memory_order_relaxed) - 1;
 
 	if (ret == 0) {
 		reset_mpstcam_entry(entry);

@@ -222,7 +223,7 @@ int cxgbe_mpstcam_rawf_enable(struct port_info *pi)
 	t4_os_write_lock(&t->lock);
 	rawf_idx = adap->params.rawf_start + pi->port_id;
 	entry = &t->entry[rawf_idx];
-	if (__atomic_load_n(&entry->refcnt, __ATOMIC_RELAXED) == 1)
+	if (rte_atomic_load_explicit(&entry->refcnt, rte_memory_order_relaxed) == 1)
 		goto out_unlock;
 
 	ret = t4_alloc_raw_mac_filt(adap, pi->viid, entry->eth_addr,

@@ -231,7 +232,7 @@ int cxgbe_mpstcam_rawf_enable(struct port_info *pi)
 	if (ret < 0)
 		goto out_unlock;
 
-	__atomic_store_n(&entry->refcnt, 1, __ATOMIC_RELAXED);
+	rte_atomic_store_explicit(&entry->refcnt, 1, rte_memory_order_relaxed);
 
 out_unlock:
 	t4_os_write_unlock(&t->lock);

@@ -253,7 +254,7 @@ int cxgbe_mpstcam_rawf_disable(struct port_info *pi)
 	t4_os_write_lock(&t->lock);
 	rawf_idx = adap->params.rawf_start + pi->port_id;
 	entry = &t->entry[rawf_idx];
-	if (__atomic_load_n(&entry->refcnt, __ATOMIC_RELAXED) != 1)
+	if (rte_atomic_load_explicit(&entry->refcnt, rte_memory_order_relaxed) != 1)
 		goto out_unlock;
 
 	ret = t4_free_raw_mac_filt(adap, pi->viid, entry->eth_addr,

@@ -262,7 +263,7 @@ int cxgbe_mpstcam_rawf_disable(struct port_info *pi)
 	if (ret < 0)
 		goto out_unlock;
 
-	__atomic_store_n(&entry->refcnt, 0, __ATOMIC_RELAXED);
+	rte_atomic_store_explicit(&entry->refcnt, 0, rte_memory_order_relaxed);
 
 out_unlock:
 	t4_os_write_unlock(&t->lock);

index 363786b..4b421f7 100644
@@ -29,7 +29,7 @@ struct mps_tcam_entry {
 	u8 mask[RTE_ETHER_ADDR_LEN];
 
 	struct mpstcam_table *mpstcam; /* backptr */
-	u32 refcnt;
+	RTE_ATOMIC(u32) refcnt;
 };
 
 struct mpstcam_table {

index 4e14a73..2f961c1 100644
@@ -119,7 +119,7 @@ static struct smt_entry *find_or_alloc_smte(struct smt_data *s, u8 *smac)
 	struct smt_entry *e, *end, *first_free = NULL;
 
 	for (e = &s->smtab[0], end = &s->smtab[s->smt_size]; e != end; ++e) {
-		if (__atomic_load_n(&e->refcnt, __ATOMIC_RELAXED) == 0) {
+		if (rte_atomic_load_explicit(&e->refcnt, rte_memory_order_relaxed) == 0) {
 			if (!first_free)
 				first_free = e;
 		} else {

@@ -156,7 +156,7 @@ static struct smt_entry *t4_smt_alloc_switching(struct rte_eth_dev *dev,
 	e = find_or_alloc_smte(s, smac);
 	if (e) {
 		t4_os_lock(&e->lock);
-		if (__atomic_load_n(&e->refcnt, __ATOMIC_RELAXED) == 0) {
+		if (rte_atomic_load_explicit(&e->refcnt, rte_memory_order_relaxed) == 0) {
 			e->pfvf = pfvf;
 			rte_memcpy(e->src_mac, smac, RTE_ETHER_ADDR_LEN);
 			ret = write_smt_entry(dev, e);

@@ -168,9 +168,9 @@ static struct smt_entry *t4_smt_alloc_switching(struct rte_eth_dev *dev,
 				goto out_write_unlock;
 			}
 			e->state = SMT_STATE_SWITCHING;
-			__atomic_store_n(&e->refcnt, 1, __ATOMIC_RELAXED);
+			rte_atomic_store_explicit(&e->refcnt, 1, rte_memory_order_relaxed);
 		} else {
-			__atomic_fetch_add(&e->refcnt, 1, __ATOMIC_RELAXED);
+			rte_atomic_fetch_add_explicit(&e->refcnt, 1, rte_memory_order_relaxed);
 		}
 		t4_os_unlock(&e->lock);
 	}

@@ -195,8 +195,8 @@ struct smt_entry *cxgbe_smt_alloc_switching(struct rte_eth_dev *dev, u8 *smac)
 
 void cxgbe_smt_release(struct smt_entry *e)
 {
-	if (__atomic_load_n(&e->refcnt, __ATOMIC_RELAXED) != 0)
-		__atomic_fetch_sub(&e->refcnt, 1, __ATOMIC_RELAXED);
+	if (rte_atomic_load_explicit(&e->refcnt, rte_memory_order_relaxed) != 0)
+		rte_atomic_fetch_sub_explicit(&e->refcnt, 1, rte_memory_order_relaxed);
 }
 
 /**

index 531810e..8b378ae 100644
@@ -23,7 +23,7 @@ struct smt_entry {
 	u16 pfvf;
 	u16 hw_idx;
 	u8 src_mac[RTE_ETHER_ADDR_LEN];
-	u32 refcnt;
+	RTE_ATOMIC(u32) refcnt;
 	rte_spinlock_t lock;
 };
 

index a3702f4..c0ee0d5 100644
@@ -135,7 +135,7 @@ struct gve_dma_mem {
 static inline void *
 gve_alloc_dma_mem(struct gve_dma_mem *mem, u64 size)
 {
-	static uint16_t gve_dma_memzone_id;
+	static RTE_ATOMIC(uint16_t) gve_dma_memzone_id;
 	const struct rte_memzone *mz = NULL;
 	char z_name[RTE_MEMZONE_NAMESIZE];
 

@@ -143,7 +143,7 @@ struct gve_dma_mem {
 		return NULL;
 
 	snprintf(z_name, sizeof(z_name), "gve_dma_%u",
-		 __atomic_fetch_add(&gve_dma_memzone_id, 1, __ATOMIC_RELAXED));
+		 rte_atomic_fetch_add_explicit(&gve_dma_memzone_id, 1, rte_memory_order_relaxed));
 	mz = rte_memzone_reserve_aligned(z_name, size, SOCKET_ID_ANY,
 					 RTE_MEMZONE_IOVA_CONTIG,
 					 PAGE_SIZE);

index cb72c69..ccaa218 100644
@@ -169,9 +169,9 @@ typedef struct __rte_packed __rte_aligned(128)
 	uint32_t cookie;			/**< MEMIF_COOKIE */
 	uint16_t flags;				/**< flags */
 #define MEMIF_RING_FLAG_MASK_INT 1		/**< disable interrupt mode */
-	uint16_t head;			/**< pointer to ring buffer head */
+	RTE_ATOMIC(uint16_t) head;			/**< pointer to ring buffer head */
 	MEMIF_CACHELINE_ALIGN_MARK(cacheline1);
-	uint16_t tail;			/**< pointer to ring buffer tail */
+	RTE_ATOMIC(uint16_t) tail;			/**< pointer to ring buffer tail */
 	MEMIF_CACHELINE_ALIGN_MARK(cacheline2);
 	memif_desc_t desc[0];			/**< buffer descriptors */
 } memif_ring_t;

156 lines not on this page · raw message

index ba17295..a32da84 100644
@@ -131,8 +131,8 @@
 	 * And it does not depend on different stores/loads in other threads.
 	 * Paired with relaxed ordering in counter increment.
 	 */
-	__atomic_store(&p->reset.pkts_bytes.int128,
-		       &p->value.pkts_bytes.int128, __ATOMIC_RELAXED);
+	rte_atomic_store_explicit(&p->reset.pkts_bytes.int128,
+		       p->value.pkts_bytes.int128, rte_memory_order_relaxed);
 	p->generation_count = generation_count;
 
 	p->ft_switch_hit_counter = counterp->ft_switch_hit_counter;

@@ -142,7 +142,7 @@
 	 * at the beginning of delete operation. Release ordering is
 	 * paired with acquire ordering on load in counter increment operation.
 	 */
-	__atomic_store_n(&p->inuse, true, __ATOMIC_RELEASE);
+	rte_atomic_store_explicit(&p->inuse, true, rte_memory_order_release);
 
 	sfc_info(sa, "enabled MAE counter 0x%x-#%u with reset pkts=%" PRIu64
 		 " bytes=%" PRIu64, counterp->type, mae_counter.id,

@@ -189,7 +189,7 @@
 	 * paired with acquire ordering on load in counter increment operation.
 	 */
 	p = &counters->mae_counters[mae_counter->id];
-	__atomic_store_n(&p->inuse, false, __ATOMIC_RELEASE);
+	rte_atomic_store_explicit(&p->inuse, false, rte_memory_order_release);
 
 	rc = efx_mae_counters_free_type(sa->nic, counter->type, 1, &unused,
 					mae_counter, NULL);

@@ -228,7 +228,7 @@
 	 * Acquire ordering is paired with release ordering in counter add
 	 * and delete operations.
 	 */
-	__atomic_load(&p->inuse, &inuse, __ATOMIC_ACQUIRE);
+	inuse = rte_atomic_load_explicit(&p->inuse, rte_memory_order_acquire);
 	if (!inuse) {
 		/*
 		 * Two possible cases include:

@@ -258,15 +258,15 @@
 	 * And it does not depend on different stores/loads in other threads.
 	 * Paired with relaxed ordering on counter reset.
 	 */
-	__atomic_store(&p->value.pkts_bytes,
-		       &cnt_val.pkts_bytes, __ATOMIC_RELAXED);
+	rte_atomic_store_explicit(&p->value.pkts_bytes,
+		       cnt_val.pkts_bytes, rte_memory_order_relaxed);
 
 	if (p->ft_switch_hit_counter != NULL) {
 		uint64_t ft_switch_hit_counter;
 
 		ft_switch_hit_counter = *p->ft_switch_hit_counter + pkts;
-		__atomic_store_n(p->ft_switch_hit_counter, ft_switch_hit_counter,
-				 __ATOMIC_RELAXED);
+		rte_atomic_store_explicit(p->ft_switch_hit_counter, ft_switch_hit_counter,
+				 rte_memory_order_relaxed);
 	}
 
 	sfc_info(sa, "update MAE counter 0x%x-#%u: pkts+%" PRIu64 "=%" PRIu64

@@ -498,8 +498,8 @@
 		&sa->mae.counter_registry;
 	int32_t rc;
 
-	while (__atomic_load_n(&counter_registry->polling.thread.run,
-			       __ATOMIC_ACQUIRE)) {
+	while (rte_atomic_load_explicit(&counter_registry->polling.thread.run,
+			       rte_memory_order_acquire)) {
 		rc = sfc_mae_counter_poll_packets(sa);
 		if (rc == 0) {
 			/*

@@ -684,8 +684,8 @@
 	int rc;
 
 	/* Ensure that flag is set before attempting to join thread */
-	__atomic_store_n(&counter_registry->polling.thread.run, false,
-			 __ATOMIC_RELEASE);
+	rte_atomic_store_explicit(&counter_registry->polling.thread.run, false,
+			 rte_memory_order_release);
 
 	rc = rte_thread_join(counter_registry->polling.thread.id, NULL);
 	if (rc != 0)

@@ -1024,8 +1024,8 @@
 	 * And it does not depend on different stores/loads in other threads.
 	 * Paired with relaxed ordering in counter increment.
 	 */
-	value.pkts_bytes.int128 = __atomic_load_n(&p->value.pkts_bytes.int128,
-						  __ATOMIC_RELAXED);
+	value.pkts_bytes.int128 = rte_atomic_load_explicit(&p->value.pkts_bytes.int128,
+						  rte_memory_order_relaxed);
 
 	data->hits_set = 1;
 	data->hits = value.pkts - p->reset.pkts;

index ff13795..7275901 100644
@@ -83,7 +83,7 @@
 	 * Release ordering enforces marker set after data is populated.
 	 * Paired with acquire ordering in sfc_repr_proxy_mbox_handle().
 	 */
-	__atomic_store_n(&mbox->write_marker, true, __ATOMIC_RELEASE);
+	rte_atomic_store_explicit(&mbox->write_marker, true, rte_memory_order_release);
 
 	/*
 	 * Wait for the representor routine to process the request.

@@ -94,7 +94,7 @@
 		 * Paired with release ordering in sfc_repr_proxy_mbox_handle()
 		 * on acknowledge write.
 		 */
-		if (__atomic_load_n(&mbox->ack, __ATOMIC_ACQUIRE))
+		if (rte_atomic_load_explicit(&mbox->ack, rte_memory_order_acquire))
 			break;
 
 		rte_delay_ms(1);

@@ -119,7 +119,7 @@
 	 * Paired with release ordering in sfc_repr_proxy_mbox_send()
 	 * on marker set.
 	 */
-	if (!__atomic_load_n(&mbox->write_marker, __ATOMIC_ACQUIRE))
+	if (!rte_atomic_load_explicit(&mbox->write_marker, rte_memory_order_acquire))
 		return;
 
 	mbox->write_marker = false;

@@ -146,7 +146,7 @@
 	 * Paired with acquire ordering in sfc_repr_proxy_mbox_send()
 	 * on acknowledge read.
 	 */
-	__atomic_store_n(&mbox->ack, true, __ATOMIC_RELEASE);
+	rte_atomic_store_explicit(&mbox->ack, true, rte_memory_order_release);
 }
 
 static void

index 597e14d..25c2b9e 100644
@@ -51,8 +51,8 @@
 	 * Store the result atomically to guarantee that the reader
 	 * core sees both counter updates together.
 	 */
-	__atomic_store_n(&st->pkts_bytes.int128, result.pkts_bytes.int128,
-			 __ATOMIC_RELAXED);
+	rte_atomic_store_explicit(&st->pkts_bytes.int128, result.pkts_bytes.int128,
+			 rte_memory_order_relaxed);
 #else
 	st->pkts += pkts;
 	st->bytes += bytes;

@@ -66,8 +66,8 @@
 sfc_pkts_bytes_get(const union sfc_pkts_bytes *st, union sfc_pkts_bytes *result)
 {
 #if SFC_SW_STATS_ATOMIC
-	result->pkts_bytes.int128 = __atomic_load_n(&st->pkts_bytes.int128,
-						    __ATOMIC_RELAXED);
+	result->pkts_bytes.int128 = rte_atomic_load_explicit(&st->pkts_bytes.int128,
+						    rte_memory_order_relaxed);
 #else
 	*result = *st;
 #endif

index defa551..2cb6a99 100644
@@ -374,8 +374,8 @@
 	NICVF_RX_ASSERT((unsigned int)to_fill <= (qlen_mask -
 		(nicvf_addr_read(rbdr->rbdr_status) & NICVF_RBDR_COUNT_MASK)));
 
-	next_tail = __atomic_fetch_add(&rbdr->next_tail, to_fill,
-					__ATOMIC_ACQUIRE);
+	next_tail = rte_atomic_fetch_add_explicit(&rbdr->next_tail, to_fill,
+					rte_memory_order_acquire);
 	ltail = next_tail;
 	for (i = 0; i < to_fill; i++) {
 		struct rbdr_entry_t *entry = desc + (ltail & qlen_mask);

@@ -385,9 +385,10 @@
 		ltail++;
 	}
 
-	rte_wait_until_equal_32(&rbdr->tail, next_tail, __ATOMIC_RELAXED);
+	rte_wait_until_equal_32((uint32_t *)(uintptr_t)&rbdr->tail, next_tail,
+	    rte_memory_order_relaxed);
 
-	__atomic_store_n(&rbdr->tail, ltail, __ATOMIC_RELEASE);
+	rte_atomic_store_explicit(&rbdr->tail, ltail, rte_memory_order_release);
 	nicvf_addr_write(door, to_fill);
 	return to_fill;
 }

index 13cf8fe..6507898 100644
@@ -20,8 +20,8 @@ struct nicvf_rbdr {
 	struct rbdr_entry_t *desc;
 	nicvf_iova_addr_t phys;
 	uint32_t buffsz;
-	uint32_t tail;
-	uint32_t next_tail;
+	RTE_ATOMIC(uint32_t) tail;
+	RTE_ATOMIC(uint32_t) next_tail;
 	uint32_t head;
 	uint32_t qlen_mask;
 } __rte_cache_aligned;

index e848c0b..2a25751 100644
@@ -59,7 +59,7 @@ struct vring_used_elem {
 
 struct vring_used {
 	uint16_t flags;
-	uint16_t idx;
+	RTE_ATOMIC(uint16_t) idx;
 	struct vring_used_elem ring[];
 };
 

@@ -70,7 +70,7 @@ struct vring_packed_desc {
 	uint64_t addr;
 	uint32_t len;
 	uint16_t id;
-	uint16_t flags;
+	RTE_ATOMIC(uint16_t) flags;
 };
 
 #define RING_EVENT_FLAGS_ENABLE 0x0

index 4fdfe70..24e2b2c 100644
@@ -948,7 +948,7 @@ int virtio_user_stop_device(struct virtio_user_dev *dev)
 static inline int
 desc_is_avail(struct vring_packed_desc *desc, bool wrap_counter)
 {
-	uint16_t flags = __atomic_load_n(&desc->flags, __ATOMIC_ACQUIRE);
+	uint16_t flags = rte_atomic_load_explicit(&desc->flags, rte_memory_order_acquire);
 
 	return wrap_counter == !!(flags & VRING_PACKED_DESC_F_AVAIL) &&
 		wrap_counter != !!(flags & VRING_PACKED_DESC_F_USED);

@@ -1037,8 +1037,8 @@ int virtio_user_stop_device(struct virtio_user_dev *dev)
 		if (vq->used_wrap_counter)
 			flags |= VRING_PACKED_DESC_F_AVAIL_USED;
 
-		__atomic_store_n(&vring->desc[vq->used_idx].flags, flags,
-				 __ATOMIC_RELEASE);
+		rte_atomic_store_explicit(&vring->desc[vq->used_idx].flags, flags,
+				 rte_memory_order_release);
 
 		vq->used_idx += n_descs;
 		if (vq->used_idx >= dev->queue_size) {

@@ -1057,9 +1057,9 @@ int virtio_user_stop_device(struct virtio_user_dev *dev)
 	struct vring *vring = &dev->vrings.split[queue_idx];
 
 	/* Consume avail ring, using used ring idx as first one */
-	while (__atomic_load_n(&vring->used->idx, __ATOMIC_RELAXED)
+	while (rte_atomic_load_explicit(&vring->used->idx, rte_memory_order_relaxed)
 	       != vring->avail->idx) {
-		avail_idx = __atomic_load_n(&vring->used->idx, __ATOMIC_RELAXED)
+		avail_idx = rte_atomic_load_explicit(&vring->used->idx, rte_memory_order_relaxed)
 			    & (vring->num - 1);
 		desc_idx = vring->avail->ring[avail_idx];
 

@@ -1070,7 +1070,7 @@ int virtio_user_stop_device(struct virtio_user_dev *dev)
 		uep->id = desc_idx;
 		uep->len = n_descs;
 
-		__atomic_fetch_add(&vring->used->idx, 1, __ATOMIC_RELAXED);
+		rte_atomic_fetch_add_explicit(&vring->used->idx, 1, rte_memory_order_relaxed);
 	}
 }
 

index 5d0c039..b7bbdde 100644
@@ -37,7 +37,7 @@
 virtio_mb(uint8_t weak_barriers)
 {
 	if (weak_barriers)
-		rte_atomic_thread_fence(__ATOMIC_SEQ_CST);
+		rte_atomic_thread_fence(rte_memory_order_seq_cst);
 	else
 		rte_mb();
 }

@@ -46,7 +46,7 @@
 virtio_rmb(uint8_t weak_barriers)
 {
 	if (weak_barriers)
-		rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
+		rte_atomic_thread_fence(rte_memory_order_acquire);
 	else
 		rte_io_rmb();
 }

@@ -55,7 +55,7 @@
 virtio_wmb(uint8_t weak_barriers)
 {
 	if (weak_barriers)
-		rte_atomic_thread_fence(__ATOMIC_RELEASE);
+		rte_atomic_thread_fence(rte_memory_order_release);
 	else
 		rte_io_wmb();
 }

@@ -67,12 +67,12 @@
 	uint16_t flags;
 
 	if (weak_barriers) {
-/* x86 prefers to using rte_io_rmb over __atomic_load_n as it reports
+/* x86 prefers to using rte_io_rmb over rte_atomic_load_explicit as it reports
  * a better perf(~1.5%), which comes from the saved branch by the compiler.
  * The if and else branch are identical  on the platforms except Arm.
  */
 #ifdef RTE_ARCH_ARM
-		flags = __atomic_load_n(&dp->flags, __ATOMIC_ACQUIRE);
+		flags = rte_atomic_load_explicit(&dp->flags, rte_memory_order_acquire);
 #else
 		flags = dp->flags;
 		rte_io_rmb();

@@ -90,12 +90,12 @@
 			      uint16_t flags, uint8_t weak_barriers)
 {
 	if (weak_barriers) {
-/* x86 prefers to using rte_io_wmb over __atomic_store_n as it reports
+/* x86 prefers to using rte_io_wmb over rte_atomic_store_explicit as it reports
  * a better perf(~1.5%), which comes from the saved branch by the compiler.
  * The if and else branch are identical on the platforms except Arm.
  */
 #ifdef RTE_ARCH_ARM
-		__atomic_store_n(&dp->flags, flags, __ATOMIC_RELEASE);
+		rte_atomic_store_explicit(&dp->flags, flags, rte_memory_order_release);
 #else
 		rte_io_wmb();
 		dp->flags = flags;

@@ -425,7 +425,7 @@ struct virtqueue *virtqueue_alloc(struct virtio_hw *hw, uint16_t index,
 
 	if (vq->hw->weak_barriers) {
 	/**
-	 * x86 prefers to using rte_smp_rmb over __atomic_load_n as it
+	 * x86 prefers to using rte_smp_rmb over rte_atomic_load_explicit as it
 	 * reports a slightly better perf, which comes from the saved
 	 * branch by the compiler.
 	 * The if and else branches are identical with the smp and io

@@ -435,8 +435,8 @@ struct virtqueue *virtqueue_alloc(struct virtio_hw *hw, uint16_t index,
 		idx = vq->vq_split.ring.used->idx;
 		rte_smp_rmb();
 #else
-		idx = __atomic_load_n(&(vq)->vq_split.ring.used->idx,
-				__ATOMIC_ACQUIRE);
+		idx = rte_atomic_load_explicit(&(vq)->vq_split.ring.used->idx,
+				rte_memory_order_acquire);
 #endif
 	} else {
 		idx = vq->vq_split.ring.used->idx;

@@ -454,7 +454,7 @@ void vq_ring_free_inorder(struct virtqueue *vq, uint16_t desc_idx,
 vq_update_avail_idx(struct virtqueue *vq)
 {
 	if (vq->hw->weak_barriers) {
-	/* x86 prefers to using rte_smp_wmb over __atomic_store_n as
+	/* x86 prefers to using rte_smp_wmb over rte_atomic_store_explicit as
 	 * it reports a slightly better perf, which comes from the
 	 * saved branch by the compiler.
 	 * The if and else branches are identical with the smp and

@@ -464,8 +464,8 @@ void vq_ring_free_inorder(struct virtqueue *vq, uint16_t desc_idx,
 		rte_smp_wmb();
 		vq->vq_split.ring.avail->idx = vq->vq_avail_idx;
 #else
-		__atomic_store_n(&vq->vq_split.ring.avail->idx,
-				 vq->vq_avail_idx, __ATOMIC_RELEASE);
+		rte_atomic_store_explicit(&vq->vq_split.ring.avail->idx,
+				 vq->vq_avail_idx, rte_memory_order_release);
 #endif
 	} else {
 		rte_io_wmb();

@@ -528,8 +528,8 @@ void vq_ring_free_inorder(struct virtqueue *vq, uint16_t desc_idx,
 #ifdef RTE_LIBRTE_VIRTIO_DEBUG_DUMP
 #define VIRTQUEUE_DUMP(vq) do { \
 	uint16_t used_idx, nused; \
-	used_idx = __atomic_load_n(&(vq)->vq_split.ring.used->idx, \
-				   __ATOMIC_RELAXED); \
+	used_idx = rte_atomic_load_explicit(&(vq)->vq_split.ring.used->idx, \
+				   rte_memory_order_relaxed); \
 	nused = (uint16_t)(used_idx - (vq)->vq_used_cons_idx); \
 	if (virtio_with_packed_queue((vq)->hw)) { \
 		PMD_INIT_LOG(DEBUG, \

@@ -546,7 +546,7 @@ void vq_ring_free_inorder(struct virtqueue *vq, uint16_t desc_idx,
 	  " avail.flags=0x%x; used.flags=0x%x", \
 	  (vq)->vq_nentries, (vq)->vq_free_cnt, nused, (vq)->vq_desc_head_idx, \
 	  (vq)->vq_split.ring.avail->idx, (vq)->vq_used_cons_idx, \
-	  __atomic_load_n(&(vq)->vq_split.ring.used->idx, __ATOMIC_RELAXED), \
+	  rte_atomic_load_explicit(&(vq)->vq_split.ring.used->idx, rte_memory_order_relaxed), \
 	  (vq)->vq_split.ring.avail->flags, (vq)->vq_split.ring.used->flags); \
 } while (0)
 #else

index 7adb6e3..c2cd295 100644
@@ -1004,7 +1004,7 @@ u16 hinic_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, u16 nb_pkts)
 	while (pkts < nb_pkts) {
 		 /* 2. current ci is done */
 		rx_cqe = &rxq->rx_cqe[sw_ci];
-		status = __atomic_load_n(&rx_cqe->status, __ATOMIC_ACQUIRE);
+		status = rte_atomic_load_explicit(&rx_cqe->status, rte_memory_order_acquire);
 		if (!HINIC_GET_RX_DONE_BE(status))
 			break;
 

index 5c30339..d77ef51 100644
@@ -29,7 +29,7 @@ struct hinic_rq_ctrl {
 };
 
 struct hinic_rq_cqe {
-	u32 status;
+	RTE_ATOMIC(u32) status;
 	u32 vlan_len;
 	u32 offload_type;
 	u32 rss_hash;

index 86151c9..1df4d6b 100644
@@ -259,8 +259,8 @@ struct rte_idpf_xstats_name_off {
 
 	for (i = 0; i < dev->data->nb_rx_queues; i++) {
 		rxq = dev->data->rx_queues[i];
-		mbuf_alloc_failed += __atomic_load_n(&rxq->rx_stats.mbuf_alloc_failed,
-						     __ATOMIC_RELAXED);
+		mbuf_alloc_failed += rte_atomic_load_explicit(&rxq->rx_stats.mbuf_alloc_failed,
+						     rte_memory_order_relaxed);
 	}
 
 	return mbuf_alloc_failed;

@@ -308,7 +308,8 @@ struct rte_idpf_xstats_name_off {
 
 	for (i = 0; i < dev->data->nb_rx_queues; i++) {
 		rxq = dev->data->rx_queues[i];
-		__atomic_store_n(&rxq->rx_stats.mbuf_alloc_failed, 0, __ATOMIC_RELAXED);
+		rte_atomic_store_explicit(&rxq->rx_stats.mbuf_alloc_failed, 0,
+		    rte_memory_order_relaxed);
 	}
 }
 

index 2edeb38..abd1186 100644
@@ -51,11 +51,11 @@ void osal_poll_mode_dpc(osal_int_ptr_t hwfn_cookie)
 /* Counter to track current memzone allocated */
 static uint16_t ecore_mz_count;
 
-static uint32_t ref_cnt;
+static RTE_ATOMIC(uint32_t) ref_cnt;
 
 int ecore_mz_mapping_alloc(void)
 {
-	if (__atomic_fetch_add(&ref_cnt, 1, __ATOMIC_RELAXED) == 0) {
+	if (rte_atomic_fetch_add_explicit(&ref_cnt, 1, rte_memory_order_relaxed) == 0) {
 		ecore_mz_mapping = rte_calloc("ecore_mz_map",
 				rte_memzone_max_get(), sizeof(struct rte_memzone *), 0);
 	}

@@ -68,7 +68,7 @@ int ecore_mz_mapping_alloc(void)
 
 void ecore_mz_mapping_free(void)
 {
-	if (__atomic_fetch_sub(&ref_cnt, 1, __ATOMIC_RELAXED) - 1 == 0) {
+	if (rte_atomic_fetch_sub_explicit(&ref_cnt, 1, rte_memory_order_relaxed) - 1 == 0) {
 		rte_free(ecore_mz_mapping);
 		ecore_mz_mapping = NULL;
 	}

index 48953dd..b16f5d5 100644
@@ -44,8 +44,8 @@ enum dev_action {
 
 struct ring_queue {
 	struct rte_ring *rng;
-	uint64_t rx_pkts;
-	uint64_t tx_pkts;
+	RTE_ATOMIC(uint64_t) rx_pkts;
+	RTE_ATOMIC(uint64_t) tx_pkts;
 };
 
 struct pmd_internals {

@@ -82,7 +82,7 @@ struct pmd_internals {
 	if (r->rng->flags & RING_F_SC_DEQ)
 		r->rx_pkts += nb_rx;
 	else
-		__atomic_fetch_add(&r->rx_pkts, nb_rx, __ATOMIC_RELAXED);
+		rte_atomic_fetch_add_explicit(&r->rx_pkts, nb_rx, rte_memory_order_relaxed);
 	return nb_rx;
 }
 

@@ -96,7 +96,7 @@ struct pmd_internals {
 	if (r->rng->flags & RING_F_SP_ENQ)
 		r->tx_pkts += nb_tx;
 	else
-		__atomic_fetch_add(&r->tx_pkts, nb_tx, __ATOMIC_RELAXED);
+		rte_atomic_fetch_add_explicit(&r->tx_pkts, nb_tx, rte_memory_order_relaxed);
 	return nb_tx;
 }
 

index f900384..98c39a5 100644
@@ -261,8 +261,8 @@
 	uint32_t timeout = 0;
 
 	/* Check and wait all close tasks done. */
-	while (__atomic_load_n(&priv->dev_close_progress,
-		__ATOMIC_RELAXED) != 0 && timeout < 1000) {
+	while (rte_atomic_load_explicit(&priv->dev_close_progress,
+		rte_memory_order_relaxed) != 0 && timeout < 1000) {
 		rte_delay_us_sleep(10000);
 		timeout++;
 	}

@@ -294,8 +294,8 @@
 			priv->last_c_thrd_idx = 0;
 		else
 			priv->last_c_thrd_idx++;
-		__atomic_store_n(&priv->dev_close_progress,
-			1, __ATOMIC_RELAXED);
+		rte_atomic_store_explicit(&priv->dev_close_progress,
+			1, rte_memory_order_relaxed);
 		if (mlx5_vdpa_task_add(priv,
 			priv->last_c_thrd_idx,
 			MLX5_VDPA_TASK_DEV_CLOSE_NOWAIT,

@@ -319,8 +319,8 @@
 	if (!priv->connected)
 		mlx5_vdpa_dev_cache_clean(priv);
 	priv->vid = 0;
-	__atomic_store_n(&priv->dev_close_progress, 0,
-		__ATOMIC_RELAXED);
+	rte_atomic_store_explicit(&priv->dev_close_progress, 0,
+		rte_memory_order_relaxed);
 	priv->state = MLX5_VDPA_STATE_PROBED;
 	DRV_LOG(INFO, "vDPA device %d was closed.", vid);
 	return ret;