Dino PCI and I/O spaces (fwd)

|Alan Cox wrote:
|> > > accesses. There seems to be no way to do byte sized config accesses, do
|> > > I just read 32bits mask and write 32bits ?
|> > 
|> > I thought Dino will forward the byte enables to the PCI bus.
|> > PCI-PCI bridge numbering I think depends on this.
|> 
|> So how do I set those. The documentaiton also says the low two bits of
|> the register read back as 0. I guess that doesnt actually imply that the
|> write of it has no affect. 
|
|The PCI_CONFIG_ADDR register (offset 0x64) is used to source the
|word address. So it's not surprising the lower order bits are RO.
|
|"Byte enables" are GSC and PCI bus signals - not register contents.
|The PA processor generates byte enable signals on the GSC bus and
|Dino forwards those for the appropriate bytes (swapped to match
|the swapping/endian conversion done for the PCI_CONFIG_DATA register.)
|The byte enable signals are taken when a processor read/write targets
|the PCI_CONFIG_DATA register (offset 0x68). The contents of PCI_CONFIG_ADDR
|and bytes enable signals from GSC bus are combined to generate a read/write
|transaction on the PCI bus.
|
|(Disclaimer: I'm not as certain of the above as it sounds though I
|believe it's correct - remember, I'm a SW engineer :^)
|

Grant has it right. I've watchedd Dino with a full logic analyzer on both GSC and PCI... The 4 byte enables get swapped as Grant described and if you do a single byte access, a single byte pops out the other side.

-Bill

Thanks. I'll go and change my PCI code to reflect reality

Alan