PIIX rewrite patch, pre-final

Hi!

This is a rewrite of the PIIX IDE timing driver. It should give slightly better performance (+4% was measured), and also replaces the slc90c66 Efar Victory66 driver, because the Victory66 is mostly a PIIX clone.

It has been tested on PIIX4 only. Please anyone with a PIIX or ICH chip, and if anyone has the Victory66 one even moreso, test this if you can.

The patch is against 2.5.6 + the patches I sent earlier, for a complete patch against clean 2.5.6 see

http://twilight.ucw.cz/ide-via-amd-piix-timing-8-pre-final.diff

Killed code good code. :)

--
Vojtech Pavlik
SuSE Labs

This will benifit PIIX3 chipsets? :)

Quoted 21 lines

Hi!

This is a rewrite of the PIIX IDE timing driver. It should give slightly better performance (+4% was measured), and also replaces the slc90c66 Efar Victory66 driver, because the Victory66 is mostly a PIIX clone.

It has been tested on PIIX4 only. Please anyone with a PIIX or ICH chip, and if anyone has the Victory66 one even moreso, test this if you can.

The patch is against 2.5.6 + the patches I sent earlier, for a complete patch against clean 2.5.6 see

http://twilight.ucw.cz/ide-via-amd-piix-timing-8-pre-final.diff

Killed code good code. :)

--
Vojtech Pavlik
SuSE Labs

Quoted 1 line

This will benifit PIIX3 chipsets? :)

It should.

Quoted 2 lines · Vojtech Pavlik

Quoted 1 line

This will benifit PIIX3 chipsets? :)

It should.

Are you aware of the batches of broken PIIX3 chips ?

Ciao,
Dani

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Daniela Engert, systems engineer at MEDAV GmbH
Gräfenberger Str. 34, 91080 Uttenreuth, Germany
Phone ++49-9131-583-348, Fax ++49-9131-583-11

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Quoted 2 lines · Vojtech Pavlik

Quoted 1 line

This will benifit PIIX3 chipsets? :)

It should.

Are you aware of the batches of broken PIIX3 chips ?

Quoted 3 lines · Daniela Engert

Quoted 1 line · Vojtech Pavlik

Quoted 1 line

This will benifit PIIX3 chipsets? :)

Quoted 3 lines

Quoted 1 line

It should.

Are you aware of the batches of broken PIIX3 chips ?

I don't know of any IDE-related errata for the PIIX3 chip. At least Intel didn't publish any and there doesn't seem to be any workarounds in the original piix.c code, only a statement stating that the PIIX3 UDMA is broken, however, as far as I know, PIIX3 isn't UDMA capable at all.

Quoted 3 lines · Daniela Engert

Quoted 1 line · Vojtech Pavlik

Quoted 1 line

This will benifit PIIX3 chipsets? :)

Quoted 3 lines

Quoted 1 line

It should.

Are you aware of the batches of broken PIIX3 chips ?

I don't know of any IDE-related errata for the PIIX3 chip. At least Intel didn't publish any and there doesn't seem to be any workarounds in the original piix.c code, only a statement stating that the PIIX3 UDMA is broken, however, as far as I know, PIIX3 isn't UDMA capable at all.

Quoted 1 line

Are you aware of the batches of broken PIIX3 chips ?

I don't know of any IDE-related errata for the PIIX3 chip. At least Intel didn't publish any and there doesn't seem to be any workarounds in the original piix.c code, only a statement stating that the PIIX3 UDMA is broken, however, as far as I know, PIIX3 isn't UDMA capable at all.

(Hmm, perhaps some BIOSes enable UDMA on PIIX3, that'd explain it ... though I believe that's quite improbable).

In what way are those batches broken?

0x1078 Cyrix
0x0102 CX5530 x x x x x - - - x

known bugs:
- all: busmaster transfers need to be 16 byte aligned instead of wor=
d
aligned.

0x1166 ServerWorks
0x0211 OSB4 x x ? ? x - - - x
0x0212 CSB5

     < 0x92			      x    x	?    ?	   x   x   -   -    -
    >=3D 0x92			      x    x	?    ?	   x   x   x   -    -

known bugs:
- OSB4: at least some chip revisions can't do Ultra DMA mode 1 and a=
bove

- CSB5: no host side cable type detection.

Quoted 8 lines · Vojtech Pavlik

Quoted 6 lines · Daniela Engert

Quoted 2 lines · Vojtech Pavlik

Quoted 1 line

This will benifit PIIX3 chipsets? :)

It should.

Are you aware of the batches of broken PIIX3 chips ?

Quoted 4 lines

I don't know of any IDE-related errata for the PIIX3 chip. At least Intel didn't publish any and there doesn't seem to be any workarounds in the original piix.c code, only a statement stating that the PIIX3 UDMA is broken, however, as far as I know, PIIX3 isn't UDMA capable at all.

27296302.pdf 82371SB (PIIX3) Timing Specification
29765804.pdf INTEL 82371FB (PIIX) and 82371SB (PIIX3) SPECIFICATION UPDATE

The PIIX3 bug is real, I have several user reports about it!

Vendor

 | Device
 | | Revision			       ATA	ATAPI	     ATA66  ATA133
 | | | south/host bridge id	     PIO  DMA  PIO  DMA  ATA33 | ATA100|   Docs
 | | | | south/host bridge rev.     32bit  |  32bit  |	   |   |   |   |  avail
 | | | | |			      |    |	|    |	   |   |   |   |    |

v v v v v v v v v v v v v v

0x8086 Intel

   0x1230 PIIX		      x    x	x    x	   -   -   -   -    x
     < 02			      x    -	x    -	   -   -   -   -    x

       0x84C4 Orion
	 < 04			      x    -	x    -	   -   -   -   -    x

   0x7010 PIIX3 		      x    x	x    x	   -   -   -   -    x
   0x7111 PIIX4 		      x    x	x    x	   x   -   -   -    x
   0x7199 PIIX4 MX		      x    x	x    x	   x   -   -   -    x
   0x84CA PIIX4 NX		      x    x	x    x	   x   -   -   -    x

   0x2411 ICH			      x    x	x    x	   x   x   -   -    x
   0x7601 ICH			      x    x	x    x	   x   x   -   -    x

   0x2421 ICH0		      x    x	x    x	   x   -   -   -    x
   0x244B ICH2		      x    x	x    x	   x   x   x   -    x
   0x244A ICH2 mobile		      x    x	x    x	   x   x   x   -    x
   0x248B ICH3		      x    x	x    x	   x   x   x   -    x
   0x248A ICH3 mobile		      x    x	x    x	   x   x   x   -    x

known bugs:
- PIIX3: some chips 'forget' to assert the IRQ sometimes. These chips are not detectable in advance.

0x1106 VIA
0x1571 571 x x x x - - - - -

   0x0571 571
       0x0586
	 < 0x20  586		      x    x	x    x	   -   -   -   -    -

	 >=0x20  586A/B 	      x    x	x    x	   x   -   -   -    x

       0x0596
	 < 0x10  596/A		      x    x	x    x	   x   -   -   -    x
	 < 0x10  596B		      x    x	x    x	   x   x   -   -    x

       0x0686
	 < 0x10  686		      x    x	x    x	   x   -   -   -    -
	 < 0x40  686A		      x    x	x    x	   x   x   -   -    x
	 >=0x40  686B		      x    x	x    x	   x   x   x   -    -

       0x8231	 VT8231 	      x    x	x    x	   x   x   x   -    -
       0x3074	 VT8233 	      x    x	x    x	   x   x   x   -    -

       0x3109	 VT8233c	      x    x	x    x	   x   x   x   -    -
       0x3147	 VT8233a	      x    x	x    x	   x   x   x   x    -

known bugs:
- all: no host side cable type detection.

- all: the busmaster 'active' bit doesn't match the actual busmaster state.
- 596B: don't touch the busmaster registers too early after interrupt don't touch taskfile registers before stopping the busmaster!
- 686 rev 40/41 and VT8231 rev 10/11 have the PCI corruption bug!

--------------------------------------------------------------------------------
0x1022 AMD

   0x7401 AMD 751		      x    x	x    x	   x   -   -   -    -
   0x7409 AMD 756		      x    x	x    x	   x   x   -   -    x
   0x7411 AMD 766  MP		      x    x	x    x	   x   x   x   -    x
   0x7441 AMD 768  MPX	      x    x	x    x	   x   x   x   -    x

0x7469 AMD 8111 x x x x x x x - -

known bugs:
- 756: no host side cable type detection.
- 756: SingleWord DMA doesn't work on early chip revisions.
- 766: read/write prefetches must be disabled to defeat infinite PCI bus retries.

--------------------------------------------------------------------------------
0x1055 SMSC
0x9130 SLC90E66 ? x ? ? x x - - x

--------------------------------------------------------------------------------
0x10DE Nvidia
0x01BC nForce x x x x x x x - -

known bugs:
- nForce: no host side cable type detection.

Quoted 8 lines

Vendor

 | Device
 | | Revision		       ATA	ATAPI	     ATA66  ATA133
 | | | south/host bridge id	     PIO  DMA  PIO  DMA  ATA33 | ATA100|   Docs
 | | | | south/host bridge rev.  32bit  |  32bit  |	   |   |   |   |  avail
 | | | | |			      |    |	|    |	   |   |   |   |    |

v v v v v v v v v v v v v v

Quoted 3 lines

0x8086 Intel

   0x1230 PIIX		      x    x	x    x	   -   -   -   -    x
     < 02			      x    -	x    -	   -   -   -   -    x

I suppose this means on PIIXes with rev 00 and 01 of the IDE controller DMA transfers don't work reliably, right?

Quoted 2 lines

       0x84C4 Orion
	 < 04			      x    -	x    -	   -   -   -   -    x

And this means that if there is an 84c4 PCI bridge in the system with rev less than 04 (04 is OK), then DMA transfers are broken again.

Quoted 1 line

   0x84CA PIIX4 NX		      x    x	x    x	   x   -   -   -    x

This one confuses me, because the 0x84ca chip doesn't seem to have any IDE capability. Is this id by any chance taken from the linux kernel?

Quoted 1 line

0x7601 ICH x x x x x x - - x

This one is actually a PIIX5, not ICH.

Quoted 3 lines

known bugs:
- PIIX3: some chips 'forget' to assert the IRQ sometimes. These chips are not detectable in advance.

Is there any workaround for that? Or there isn't to do anything about the bug and we just have to live with it ...

Quoted 2 lines

0x1106 VIA
0x1571 571 x x x x - - - - -

Irq unmasking during PIO transfers is known to cause problems on these. Also, some have wrong ISA bridge vendor ID of 1107.

Quoted 3 lines

   0x0571 571
       0x0586
	 < 0x20  586		      x    x	x    x	   -   -   -   -    -

I have docs on this one.

Quoted 1 line

	 >=0x20  586A/B 	      x    x	x    x	   x   -   -   -    x

00..1f 586
20..2f 586a
30..3f 586b
40..46 586b 3040 silicon
Has a bug where the preq# til ddack# bit must be cleared or can cause spontaneous reboots.
47..4f 586b 3041 silicon

Quoted 3 lines

       0x0596
	 < 0x10  596/A		      x    x	x    x	   x   -   -   -    x
	 < 0x10  596B		      x    x	x    x	   x   x   -   -    x

That probably should be >= 10

Quoted 4 lines

       0x0686
	 < 0x10  686		      x    x	x    x	   x   -   -   -    -
	 < 0x40  686A		      x    x	x    x	   x   x   -   -    x
	 >=0x40  686B		      x    x	x    x	   x   x   x   -    -

I have docs here as well.

Quoted 2 lines

       0x8231	 VT8231 	      x    x	x    x	   x   x   x   -    -
       0x3074	 VT8233 	      x    x	x    x	   x   x   x   -    -

And for this, too.

Quoted 5 lines

       0x3109	 VT8233c	      x    x	x    x	   x   x   x   -    -
       0x3147	 VT8233a	      x    x	x    x	   x   x   x   x    -

known bugs:
- all: no host side cable type detection.

Not true, for the UDMA100 and UDMA133 capable ones, there are defined bits in the UDMA_TIMING register. Not all BIOSes use those, though.

Quoted 6 lines

--------------------------------------------------------------------------------
0x10DE Nvidia
0x01BC nForce x x x x x x x - -

known bugs:
- nForce: no host side cable type detection.

Do you have any info on this one? I'd really like to have a Linux driver for it ...

Quoted 7 lines

00..1f 586
20..2f 586a
30..3f 586b
40..46 586b 3040 silicon
Has a bug where the preq# til ddack# bit must be cleared or can cause spontaneous reboots.
47..4f 586b 3041 silicon

True. I leave this particular setup to the BIOS which is supposed to take care of such idiosyncrasies...

Quoted 8 lines

Quoted 5 lines

       0x3109	 VT8233c	      x    x	x    x	   x   x   x   -    -
       0x3147	 VT8233a	      x    x	x    x	   x   x   x   x    -

known bugs:
- all: no host side cable type detection.

Not true, for the UDMA100 and UDMA133 capable ones, there are defined bits in the UDMA_TIMING register. Not all BIOSes use those, though.

Interesting. None of the user reports ever indicated that.

Quoted 7 lines

Quoted 6 lines

--------------------------------------------------------------------------------
0x10DE Nvidia
0x01BC nForce x x x x x x x - -

known bugs:
- nForce: no host side cable type detection.

Quoted 2 lines

Do you have any info on this one? I'd really like to have a Linux driver for it ...

I have no docs, but my father's machine has this chip built in :-) My driver is running it just fine. In fact, this is a clone of the ATA/100 capable AMD IDE chip cell with all config register addresses shifted up by 0x10.

I'm looking forward to the new ATI chipset, let's bet where their IDE cell is licenced from :-)

Quoted 1 line · Daniela Engert

The PIIX3 bug is real, I have several user reports about it!

Thanks A LOT for the tables, added are some comments from me ...

Quoted 11 lines

Vendor

 | Device
 | | Revision			       ATA	ATAPI	     ATA66  ATA133
 | | | south/host bridge id	     PIO  DMA  PIO  DMA  ATA33 | ATA100|   Docs
 | | | | south/host bridge rev.     32bit  |  32bit  |	   |   |   |   |  avail
 | | | | |			      |    |	|    |	   |   |   |   |    |

v v v v v v v v v v v v v v

0x8086 Intel

   0x1230 PIIX		      x    x	x    x	   -   -   -   -    x
     < 02			      x    -	x    -	   -   -   -   -    x

I suppose this means on PIIXes with rev 00 and 01 of the IDE controller DMA transfers don't work reliably, right?

Quoted 2 lines

       0x84C4 Orion
	 < 04			      x    -	x    -	   -   -   -   -    x

And this means that if there is an 84c4 PCI bridge in the system with rev less than 04 (04 is OK), then DMA transfers are broken again.

diff -urN linux-2.5.6-timing/drivers/ide/Config.in linux-2.5.6-piix/drivers/ide/Config.in

drivers/ide/Config.in +1 -4

@@ -67,10 +67,7 @@
   	    dep_bool '    HPT34X chipset support' CONFIG_BLK_DEV_HPT34X $CONFIG_BLK_DEV_IDEDMA_PCI
 	    dep_mbool '      HPT34X AUTODMA support (WIP)' CONFIG_HPT34X_AUTODMA $CONFIG_BLK_DEV_HPT34X $CONFIG_IDEDMA_PCI_WIP
 	    dep_bool '    HPT366 chipset support' CONFIG_BLK_DEV_HPT366 $CONFIG_BLK_DEV_IDEDMA_PCI
-	    if [ "$CONFIG_X86" = "y" -o "$CONFIG_IA64" = "y" ]; then
-	       dep_mbool '    Intel PIIXn chipsets support' CONFIG_BLK_DEV_PIIX $CONFIG_BLK_DEV_IDEDMA_PCI
-	       dep_mbool '      PIIXn Tuning support' CONFIG_PIIX_TUNING $CONFIG_BLK_DEV_PIIX $CONFIG_IDEDMA_PCI_AUTO
-	    fi
+	    dep_bool '    Intel PIIX, ICH and Efar Victory66 chipsets support' CONFIG_BLK_DEV_PIIX $CONFIG_BLK_DEV_IDEDMA_PCI
 	    if [ "$CONFIG_MIPS_ITE8172" = "y" -o "$CONFIG_MIPS_IVR" = "y" ]; then
 	       dep_mbool '    IT8172 IDE support' CONFIG_BLK_DEV_IT8172 $CONFIG_BLK_DEV_IDEDMA_PCI
 	       dep_mbool '      IT8172 IDE Tuning support' CONFIG_IT8172_TUNING $CONFIG_BLK_DEV_IT8172 $CONFIG_IDEDMA_PCI_AUTO

On Thu, Mar 14, 2002 at 12:14:49AM +0100, Vojtech Pavlik wrote:

[snip]

Quoted 16 lines

diff -urN linux-2.5.6-timing/drivers/ide/Config.in linux-2.5.6-piix/drivers/ide/Config.in

drivers/ide/Config.in +1 -4

@@ -67,10 +67,7 @@
   	    dep_bool '    HPT34X chipset support' CONFIG_BLK_DEV_HPT34X $CONFIG_BLK_DEV_IDEDMA_PCI
 	    dep_mbool '      HPT34X AUTODMA support (WIP)' CONFIG_HPT34X_AUTODMA $CONFIG_BLK_DEV_HPT34X $CONFIG_IDEDMA_PCI_WIP
 	    dep_bool '    HPT366 chipset support' CONFIG_BLK_DEV_HPT366 $CONFIG_BLK_DEV_IDEDMA_PCI
-	    if [ "$CONFIG_X86" = "y" -o "$CONFIG_IA64" = "y" ]; then
-	       dep_mbool '    Intel PIIXn chipsets support' CONFIG_BLK_DEV_PIIX $CONFIG_BLK_DEV_IDEDMA_PCI
-	       dep_mbool '      PIIXn Tuning support' CONFIG_PIIX_TUNING $CONFIG_BLK_DEV_PIIX $CONFIG_IDEDMA_PCI_AUTO
-	    fi
+	    dep_bool '    Intel PIIX, ICH and Efar Victory66 chipsets support' CONFIG_BLK_DEV_PIIX $CONFIG_BLK_DEV_IDEDMA_PCI
 	    if [ "$CONFIG_MIPS_ITE8172" = "y" -o "$CONFIG_MIPS_IVR" = "y" ]; then
 	       dep_mbool '    IT8172 IDE support' CONFIG_BLK_DEV_IT8172 $CONFIG_BLK_DEV_IDEDMA_PCI
 	       dep_mbool '      IT8172 IDE Tuning support' CONFIG_IT8172_TUNING $CONFIG_BLK_DEV_IT8172 $CONFIG_IDEDMA_PCI_AUTO

drivers/ide/Config.in line 85

Quoted 7 lines

drivers/ide/Config.in +0 -1

@@ -83,7 +80,6 @@
 	    dep_bool '      Special FastTrak Feature' CONFIG_PDC202XX_FORCE $CONFIG_BLK_DEV_PDC202XX
 	    dep_bool '    ServerWorks OSB4/CSB5 chipsets support' CONFIG_BLK_DEV_SVWKS $CONFIG_BLK_DEV_IDEDMA_PCI $CONFIG_X86
 	    dep_bool '    SiS5513 chipset support' CONFIG_BLK_DEV_SIS5513 $CONFIG_BLK_DEV_IDEDMA_PCI $CONFIG_X86
-	    dep_bool '    SLC90E66 chipset support' CONFIG_BLK_DEV_SLC90E66 $CONFIG_BLK_DEV_IDEDMA_PCI $CONFIG_X86
 	    dep_bool '    Tekram TRM290 chipset support (EXPERIMENTAL)' CONFIG_BLK_DEV_TRM290 $CONFIG_BLK_DEV_IDEDMA_PCI
 	    dep_bool '    VIA82CXXX chipset support' CONFIG_BLK_DEV_VIA82CXXX $CONFIG_BLK_DEV_IDEDMA_PCI
          fi

This reminds (and I'm about to submit a patch to fix it..) but the above is wrong, and should look like:
if [ "$CONFIG_X86" = "y" -o "$CONFIG_IA64" = "y" ]; then
dep_bool ' Intel PIIX, ICH and Efar Victory66 chipsets support' CONFIG_BLK_DEV_PIIX $CONFIG_BLK_DEV_IDEDMA_PCI
fi

Unless the Efar Victory66 is showing up in other arches now...