INTEL 845G Chipset IDE Quandry

I am having trouble enabling DMA on a recently
installed motherboard. (Intel D845GBVL - 845g chipset). I am running a fresh RedHat7.3 install and have tried the stock RH kernel, and I'm up to 2.4.19-pre9. I have a CD burner and DVD drive attached which operated with DMA on an older
845 mobo. If I run hdparm -d1 /dev/hd(a or c),
I now get:

HDIO_SET_DMA failed: Operation not permitted

Here is a snippet from dmesg:

ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
PCI_IDE: unknown IDE controller on PCI bus 00 device f9, VID=8086, DID=24cb
PCI: Device 00:1f.1 not available because of resource collisions
PCI_IDE: (ide_setup_pci_device:) Could not enable device.

Here is some lspci

00:00.0 Host bridge: Intel Corp.: Unknown device 2560 (rev 01) 00:01.0 PCI bridge: Intel Corp.: Unknown device 2561 (rev 01) 00:1d.0 USB Controller: Intel Corp.: Unknown device 24c2 (rev 01) 00:1d.1 USB Controller: Intel Corp.: Unknown device 24c4 (rev 01) 00:1d.2 USB Controller: Intel Corp.: Unknown device 24c7 (rev 01) 00:1e.0 PCI bridge: Intel Corp. 82801BA/CA PCI Bridge (rev 81) 00:1f.0 ISA bridge: Intel Corp.: Unknown device 24c0 (rev 01) 00:1f.1 IDE interface: Intel Corp.: Unknown device 24cb (rev 01)

I followed some recent threads, and tried fixes to similiar problems but I'm still locked out.

Aside from this glitch everything else seems to run fine. Could someone give my a hand? Am I missing something simple, is my bios borked, or do I need a patch to support the newer chipset?

Thanks,

Tony

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If you look with lspci -v you will find your BIOS has mismapped or forgotten to map some of the control register space for that device.

Alan

Alan,

This is one of the versions of INTEL which has extra bandwidth if you want wanted to the async IO. Meaning the device could be set faster than the host when reading from the host. However when writing to the host the device "must" be set to match. The buffer is not capable of safely handling the extra push.

So in 2.4 we will properly time the host, unlike 2.5 which has elected to overdrive the hardware.

The effect is the following. "LINUS are you listening?"

Ultra DMA 100 uses 4 data clocks to transfer "X" amount of data. Ultra DMA 133 uses 3 data clocks to transfer "X" amount of data.

So if a bad host trys to push the limits, it ends up missing a data strobe and the DATA goes away quietly without warning. NICE!

Maybe now people will understand why 2.5 is falling apart and it is not Martin's fault. He is just getting bad information and bad patches. He actual has nearly the same model I was working on to use fucntion pointers in the style of "MiniPort (tm)". I will explain why this is desired later.

Cheers,

Andre Hedrick
LAD Storage Consulting Group

PS AntonA, my promise to you to inform Linus of one of the major design flaws of 2.5 is now met.

I need to add "24cb" to the list of hosts.

Andre Hedrick
LAD Storage Consulting Group