CPU/cache detection wrong
I too have incorrect CPU/cache detection using 2.4.20-pre7-ac3. I seem to recall it working correctly on 2.4.19-ac1 (this was the version in which the ac did not get added by the patch). Anyway I have a tualatin PIII with a 512K L2 cache. I inserted the printk in setup.c that Alan asked for earlier in the thread and got three outputs (it's a two processor machine). I have edited everything but the printk output and the CPU:... lines. Things are working fine with the kernel command line cachesize=512.
David
Sep 30 12:56:02 janus kernel: Cache info byte: 01 Sep 30 12:56:02 janus kernel: Cache info byte: 02 Sep 30 12:56:02 janus kernel: Cache info byte: 03 Sep 30 12:56:02 janus kernel: Cache info byte: 00 Sep 30 12:56:02 janus kernel: Cache info byte: 00 Sep 30 12:56:02 janus last message repeated 6 times Sep 30 12:56:02 janus kernel: Cache info byte: 83 Sep 30 12:56:02 janus kernel: Cache info byte: 08 Sep 30 12:56:02 janus kernel: Cache info byte: 04 Sep 30 12:56:02 janus kernel: Cache info byte: 0C Sep 30 12:56:02 janus kernel: CPU: L1 I cache: 16K, L1 D cache: 16K Sep 30 12:56:02 janus kernel: CPU: L2 cache: 256K ........................................................... Sep 30 12:56:02 janus kernel: Cache info byte: 01 Sep 30 12:56:02 janus kernel: Cache info byte: 02 Sep 30 12:56:02 janus kernel: Cache info byte: 03 Sep 30 12:56:02 janus kernel: Cache info byte: 00 Sep 30 12:56:02 janus last message repeated 7 times Sep 30 12:56:02 janus kernel: Cache info byte: 83 Sep 30 12:56:02 janus kernel: Cache info byte: 08 Sep 30 12:56:02 janus kernel: Cache info byte: 04 Sep 30 12:56:02 janus kernel: Cache info byte: 0C Sep 30 12:56:02 janus kernel: CPU: L1 I cache: 16K, L1 D cache: 16K Sep 30 12:56:02 janus kernel: CPU: L2 cache: 256K ..................................................................................... Sep 30 12:56:02 janus kernel: Cache info byte: 01 Sep 30 12:56:02 janus kernel: Cache info byte: 02 Sep 30 12:56:02 janus kernel: Cache info byte: 03 Sep 30 12:56:02 janus kernel: Cache info byte: 00 Sep 30 12:56:02 janus last message repeated 7 times Sep 30 12:56:02 janus kernel: Cache info byte: 83 Sep 30 12:56:02 janus kernel: Cache info byte: 08 Sep 30 12:56:02 janus kernel: Cache info byte: 04 Sep 30 12:56:02 janus kernel: Cache info byte: 0C Sep 30 12:56:02 janus kernel: CPU: L1 I cache: 16K, L1 D cache: 16K Sep 30 12:56:02 janus kernel: CPU: L2 cache: 256K
Quoted 4 lines · David L. DeGeorge
I too have incorrect CPU/cache detection using 2.4.20-pre7-ac3. I seem to recall it working correctly on 2.4.19-ac1 (this was the version in which the ac did not get added by the patch). Anyway I have a tualatin PIII with a 512K L2 cache.
Some of the tualatins have an errata which makes L2 cache sizing impossible. They actually report they have 0K L2 cache. By checking the CPU model, we can guess we have at least 256K (which is where Linux got that number from in your case). But this however means the 512K models will report as 256K too.
To work around it, boot with cachesize=512 and all will be good.
Dave
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| Dave Jones. http://www.codemonkey.org.uk
Quoted 6 lines · Dave Jones
Some of the tualatins have an errata which makes L2 cache sizing impossible. They actually report they have 0K L2 cache. By checking the CPU model, we can guess we have at least 256K (which is where Linux got that number from in your case). But this however means the 512K models will report as 256K too.
To work around it, boot with cachesize=512 and all will be good.
Strange -- why not to default to 256K and override it with the value
obtained from a cache descriptor if != 0, then?
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+ Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: [email protected], PGP key available +
Quoted 9 lines · Maciej W. Rozycki
Quoted 6 lines
Some of the tualatins have an errata which makes L2 cache sizing impossible. They actually report they have 0K L2 cache. By checking the CPU model, we can guess we have at least 256K (which is where Linux got that number from in your case). But this however means the 512K models will report as 256K too.
To work around it, boot with cachesize=512 and all will be good.Strange -- why not to default to 256K and override it with the value
obtained from a cache descriptor if != 0, then?
Because the cache descriptor IS zero. So we default to 256K.
Dave
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| Dave Jones. http://www.codemonkey.org.uk
Quoted 11 lines · Dave Jones
Quoted 9 lines
Quoted 6 lines
Some of the tualatins have an errata which makes L2 cache sizing impossible. They actually report they have 0K L2 cache. By checking the CPU model, we can guess we have at least 256K (which is where Linux got that number from in your case). But this however means the 512K models will report as 256K too.
To work around it, boot with cachesize=512 and all will be good.Strange -- why not to default to 256K and override it with the value
obtained from a cache descriptor if != 0, then?Because the cache descriptor IS zero. So we default to 256K.
You wrote "some of", so I suppose others are OK. I meant those others.
Anyway -- is it a new problem? I can't see it documented in the current P3 spec update. That's weird -- Intel might hesitate documenting weirdnesses of their chips, however they tend to include such simple and obvious errata in the update.
The spec actually states the L2 descriptor for the P3 may be as follows:
- 0x43 -- 512kB, unified,
- 0x82 -- 256kB, 8-way set associative,
- 0x83 -- 512kB, 8-way set associative.
The last descriptor is omitted from the list of known types in cache_table in 2.4.20-pre8 -- could it be the culprit?
Maciej
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+ Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: [email protected], PGP key available +
Quoted 4 lines · Maciej W. Rozycki
Quoted 3 lines
Quoted 2 lines
Strange -- why not to default to 256K and override it with the value
obtained from a cache descriptor if != 0, then?Because the cache descriptor IS zero. So we default to 256K.
You wrote "some of", so I suppose others are OK.
Yes, one stepping only afaik. Though the test in the kernel checks for 6.11,x with l2==0 just to be sure.
Quoted 6 lines
I meant those others.
Anyway -- is it a new problem? I can't see it documented in the current P3 spec update. That's weird -- Intel might hesitate documenting weirdnesses of their chips, however they tend to include such simple and obvious errata in the update.
Quoted 8 lines
The spec actually states the L2 descriptor for the P3 may be as follows:
-
0x43-- 512kB, unified,
-0x82-- 256kB, 8-way set associative,
-0x83-- 512kB, 8-way set associative.The last descriptor is omitted from the list of known types in
cache_tablein 2.4.20-pre8 -- could it be the culprit?
Added in last nights patch. IIRC, the errata meant there was no descriptor at all iirc.
TBH, I can't recall which document I read about this in, as it was a few months back now. I'll look through old mails when I get chance and see if I can get to the bottom of it.
It's possible that this was reported to me, and it is the case you describe (missing descriptor), but the old code should have picked apart the descriptors in a different way to the new table-lookup, so that *should* have worked ok if the descriptor was correct.
Dave
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| Dave Jones. http://www.codemonkey.org.uk