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generic device DMA implementation

PATCH Adam J. Richter 2 participants 2 messages Dec 28, 2002 – Dec 29, 2002

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On 2002-12-17 Manfred Spraul wrote the following, which I am taking out of order:

Review

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+Warnings:  Memory coherency operates at a granularity called the cache
+line width. [...]

That's a description of "inconsistent" memory. "Consistent"
memory does not have the cache line problems. It is uncached. Architectures that cannot allocate memory with this property cannot allocate consistent memory, and accomodating what I think motivated James to take a whack at this.

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The driver must use the normal memory barrier instructions even in coherent memory.

I know Documentation/DMA-mapping.txt says that, and I
understand that wmb() is necessary with consistent memory, but I wonder if rmb() really is, at least if you've declared the data structures in question as volatile to prevent reordering of reads by the compiler.

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- kmalloc (32,GFP_KERNEL) returns a 32-byte object, even if the cache line size is 128 bytes. The 4 objects in the cache line could be used by four different users. - sendfile() with an odd offset.

+1 Insightful

I think we could use a GFP_ flag for kmallocs that are
intended for DMA (typically networking and USB packets) that would cause the memory allocation to be aligned and rounded up to a multiple of cache line size. There probably are only a dozen or so such kmallocs, but I think it's enough so that having a kmalloc flag would result in a smaller kernel than without it.

As you've pointed out with your sendfile() example, the
problem you've identified goes beyond kmalloc. I'm still mulling it over, but it's worth noting that it is not a new problem introduced by the generic DMA interface. Thanks for raising it though. I hadn't thought of it before.

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Quoted 5 lines · Adam J. Richter

I know Documentation/DMA-mapping.txt says that, and I
understand that wmb() is necessary with consistent memory, but I wonder if rmb() really is, at least if you've declared the data structures in question as volatile to prevent reordering of reads by the compiler.

Compiler ordering != Processor to memory ordering != PCI device view ordering

volatile may not be enough.

Alan