Skip to contentSkip to conversation

backport AMD K7 MCE changes.

PATCH Dave Jones 1 participant 1 message Oct 3, 2003

lore
Share & tools
lore

Dave Jones

author
#0 lore raw

We're still accessing MCE bank 0 on Athlons in 2.4 when we shouldn't. (We don't enable it, but we still check it in the exception handler) This is fixed differently in 2.6, but is a minimal change to reproduce the same effect.

Dave

arch/i386/kernel/bluesmoke.c renamed from arch/i386/kernel/bluesmoke.c~ +7 -3
@@ -16,6 +16,7 @@
  */
 
 static int banks;
+static int startbank;
 
 static void intel_machine_check(struct pt_regs * regs, long error_code)
 {

@@ -30,7 +31,7 @@
 
 	printk(KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n", smp_processor_id(), mcgsth, mcgstl);
 	
-	for(i=0;i<banks;i++)
+	for(i=startbank;i<banks;i++)
 	{
 		rdmsr(MSR_IA32_MC0_STATUS+i*4,low, high);
 		if(high&(1<<31))

@@ -219,10 +220,13 @@
 	{
 		case X86_VENDOR_AMD:
 			/*
-			 *	AMD K7 machine check is Intel like
+			 *	AMD K7/K8 machine check is Intel like.
 			 */
-			if(c->x86 == 6 || c->x86 == 15)
+			
+			if(c->x86 == 6 || c->x86 == 15) {
+				startbank = 1;
 				intel_mcheck_init(c);
+			}
 			break;
 		case X86_VENDOR_INTEL:
 			intel_mcheck_init(c);
Signature · 1 line
 Dave Jones     http://www.codemonkey.org.uk