minor changes to qla1280 driver
Subsystems (2)
PATCH 1/1 minor changes to qla1280 driver
On one of our big machines we found a problem with posted writes while running AIM.
Two writes of the Request Queue In pointer went out of order, making the chip think that it had a queue wrap.
I took advantage of this opportunity to add relaxed reads, which helps the Altix. It should not affect other arches. All reads are relaxed except for the read of the Semaphore register.
Thanks
jeremy
# This is a BitKeeper generated patch for the following project:
# Project Name: Linux kernel tree
# This patch format is intended for GNU patch command version 2.5 or higher. # This patch includes the following deltas:
# ChangeSet 1.1784 -> 1.1785
# drivers/scsi/qla1280.h 1.24 -> 1.25
# drivers/scsi/qla1280.c 1.55 -> 1.56
#
# The following is the BitKeeper ChangeSet Log
# --------------------------------------------
# 04/04/22 [email protected] 1.1785
# Add missing posted write flush and relaxed PIO reads.
# --------------------------------------------
#
drivers/scsi/qla1280.c +4 -1
@@ -3371,6 +3371,7 @@ sp->flags |=SRB_SENT ; ha->actthreads++;WRT_REG_WORD (®->mailbox4, ha->req_ring_index); + (void )RD_REG_WORD (®->mailbox4);/* PCI posted write flush */ out:if (status)
@@ -3639,6 +3640,7 @@ sp->flags |=SRB_SENT ; ha->actthreads++;WRT_REG_WORD (®->mailbox4, ha->req_ring_index); + (void )RD_REG_WORD (®->mailbox4);/* PCI posted write flush */ out:if (status)
@@ -3750,6 +3752,7 @@/* Set chip new ring index. */ WRT_REG_WORD (®->mailbox4, ha->req_ring_index); + (void )RD_REG_WORD (®->mailbox4);/* PCI posted write flush */ LEAVE ("qla1280_isp_cmd" ); }
@@ -3788,7 +3791,7 @@/* Check for mailbox interrupt. */ - mailbox[0 ] =RD_REG_WORD (®->semaphore); + mailbox[0 ] =RD_REG_WORD_dmasync (®->semaphore);if (mailbox[0 ] &BIT_0 ) {/* Get mailbox data. */
drivers/scsi/qla1280.h +2 -1
@@ -57,7 +57,8 @@#define BIT_31 0x80000000#if MEMORY_MAPPED_IO -#define RD_REG_WORD (addr) readw(addr) +#define RD_REG_WORD (addr) readw_relaxed(addr) +#define RD_REG_WORD_dmasync (addr) readw(addr)#define WRT_REG_WORD (addr, data) writew(data, addr)#else /* MEMORY_MAPPED_IO */ #define RD_REG_WORD (addr) inw((unsigned long)addr)