Add C3 support to P4-M / ICH-M chipsets
RFC PATCH 1/1 Add C3 support to P4-M / ICH-M chipsets
Hi,
The following patch adds C3 (Deep Sleep) support to a Pentium 4-M / ICH-M combinations by overriding the FADT's idea of PM2_CNT and ARB_DIS.
Note: the patch as it is is meant for initial testing only. Using it for anything serious is asking for troubles (possibly fs corruption if something goes wrong). You have been warned.
Rationale: There seems to be a number of OEMs who forget to supply the proper PM2_CNT block address in the FADT, while at the same time supplying proper P_LVL3_LAT. If we stick to the specification, this means that C3 is supported only through WBINVD instruction. As it turns out, such an implementation is tricky and unreliable. However, the ICH3-M docs explicitly specify the location of the PM2_CNT block and the ARB_DIS needed to disable bus master arbitration for C3. Moreover, speedstep-ich uses the hardcoded ARB_DIS location to control SpeedStep transitions for all ICH-M chipsets. Therefore, overriding the ARB_DIS location with a hardcoded value (PMBASE + 0x20, according to the spec and speedstep-ich.c) should be quite harmless and yield working C3.
What are the requirements?
- Intel Pentium 4-M processor
- ICH3-M southbridge (though it may work with other ICH-M chipsets)
- FADT version 1 (i.e. 32-bit, AFAIK)
- valid (i.e. < 1000) P_LVL3_LAT entry in FADT
- invalid (i.e. 0) PM2_CNT_BLK and PM2_CNT_LEN
Please use acpitbl < /proc/acpi/fadt from pmtools package to verify you meet all the reqs.
Note: it should be fairly trivial to both override the P_LVL3_LAT value (not that I recommend that) and to move the code so that it works for FADT version 2.
What are the benefits?
On my system (P4-M 1.7 GHz on a i845MP+ICH3-M chipset), C3 reduces idle power consumption by about 1.5 W (some 7% of idle power consumption) and idle temperature by about 3-4°C, which in turn facilitates passive cooling and allows for greater power savings. YMMV, however.
Future?
It seems that in spite of what the ACPI spec says, some ICH-M chipsets have a 7-byte long PBLK to support DeeperSleep (C4). With ARB_DIS present, C4 implementation seems fairly trivial (assuming the patch to extend the processor module's support beyond C3 ever gets merged). Additionally, there are other chipset-specific features that could be implemented to improve power savings. Now, for the tricky part:
1) Is it actually worth it? Do the power savings justify the effort? Are there many people who might benefit from this patch?
2) Are there any chances on merging such chipset-specific quirks? Obviously, not in the current form, but possibly as a separate object surrounded by pci_find_subsys() or anything appropriate?
Any comments are welcome.
Best regards,
Signature · 28 lines
Karol 'sziwan' Kozimor sziwan-DETuoxkZsSqrDJvtcaxF/[email protected] --- a/drivers/acpi/tables/tbconvrt.c 2004-05-18 10:53:34.000000000 +0200 +++ b/drivers/acpi/tables/tbconvrt.c 2004-05-18 10:53:10.000000000 +0200 @@ -257,6 +257,14 @@ acpi_tb_convert_fadt1 ( local_fadt->iapc_boot_arch = BAF_LEGACY_DEVICES; /* + * Override PM2_CNT_BLK and PM2_CNT_LEN to get proper ARB_DIS address; + * valid for ICH-M chipsets. + */ + local_fadt->V1_pm2_cnt_blk = (acpi_physical_address) + (local_fadt->V1_pm1a_evt_blk + 0x20); + local_fadt->pm2_cnt_len = 0x1; + + /* * Convert the V1.0 block addresses to V2.0 GAS structures */ acpi_tb_init_generic_address (&local_fadt->xpm1a_evt_blk, local_fadt->pm1_evt_len, ------------------------------------------------------- This SF.Net email is sponsored by: SourceForge.net Broadband Sign-up now for SourceForge Broadband and get the fastest 6.0/768 connection for only $19.95/mo for the first 3 months! http://ads.osdn.com/?ad_id=2562&alloc_id=6184&op=click
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Quoted 7 lines · Karol Kozimor
Now, for the tricky part:
1) Is it actually worth it? Do the power savings justify the effort? Are there many people who might benefit from this patch?
2) Are there any chances on merging such chipset-specific quirks? Obviously, not in the current form, but possibly as a separate object surrounded bypci_find_subsys()or anything appropriate?
Karol,
Good hunting ont he chip set spect etc.
But lets wait till after we have a _CST based implementation in place and then see if the workarounds are still necessary then.
thanks,
-Len
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Quoted 4 lines · Len Brown
Quoted 2 lines · Karol Kozimor
Now, for the tricky part:
Quoted 8 lines
Quoted 5 lines
1) Is it actually worth it? Do the power savings justify the effort? Are there many people who might benefit from this patch?
2) Are there any chances on merging such chipset-specific quirks? Obviously, not in the current form, but possibly as a separate object surrounded bypci_find_subsys()or anything appropriate?Karol,
Good hunting ont he chip set spect etc.
IIRC, there is trouble with C3 on a ICH3m, though I do not remember exactly if that is true. I will look at the specs update.
Quoted 2 lines
But lets wait till after we have a
_CSTbased implementation in place and then see if the workarounds are still necessary then.
I doubt this will work. At least my patch do require ARB_DIS, as well for those writen by Dominik IIRC.
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Bruno Ducrot -- Which is worse: ignorance or apathy? -- Don't know. Don't care. ------------------------------------------------------- This SF.Net email is sponsored by: Oracle 10g Get certified on the hottest thing ever to hit the market... Oracle 10g. Take an Oracle 10g class now, and we'll give you the exam FREE. http://ads.osdn.com/?ad_id=3149&alloc_id=8166&op=click
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Thus wrote Bruno Ducrot:
Quoted 2 lines
IIRC, there is trouble with C3 on a ICH3m, though I do not remember exactly if that is true. I will look at the specs update.
As far as I remember, the only one was when running IO-APIC and it affected both C2 and C3. Most BIOSes already disable APIC on laptops, and those that don't probably still use C2, so the patch doesn't really change anything with respect to them.
Best regards,
Signature · 9 lines
Karol 'sziwan' Kozimor sziwan-DETuoxkZsSqrDJvtcaxF/[email protected] ------------------------------------------------------- This SF.Net email is sponsored by: Oracle 10g Get certified on the hottest thing ever to hit the market... Oracle 10g. Take an Oracle 10g class now, and we'll give you the exam FREE. http://ads.osdn.com/?ad_id=3149&alloc_id=8166&op=click
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Quoted 8 lines · Karol Kozimor
Thus wrote Bruno Ducrot:
Quoted 2 lines
IIRC, there is trouble with C3 on a ICH3m, though I do not remember exactly if that is true. I will look at the specs update.
As far as I remember, the only one was when running IO-APIC and it affected both C2 and C3. Most BIOSes already disable APIC on laptops, and those that don't probably still use C2, so the patch doesn't really change anything with respect to them.
Sound like you are correct. For the patch itself though, there is at least those troubles:
- There is systems where you really don't support bus master arbitration.
- you assume that DIS_ARB is at PMBASE + 0x20, which is true only for a subset of chipsets. Actually, there are more for which it's at 0x22 I believe (and this is not an offset relative to PMBASE).
Cheers,
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Bruno Ducrot -- Which is worse: ignorance or apathy? -- Don't know. Don't care. ------------------------------------------------------- This SF.Net email is sponsored by: Oracle 10g Get certified on the hottest thing ever to hit the market... Oracle 10g. Take an Oracle 10g class now, and we'll give you the exam FREE. http://ads.osdn.com/?ad_id=3149&alloc_id=8166&op=click
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Thus wrote Bruno Ducrot:
Quoted 7 lines
Sound like you are correct. For the patch itself though, there is at least those troubles:
- There is systems where you really don't support bus master arbitration.
- you assume thatDIS_ARBis at PMBASE +0x20, which is true only for a subset of chipsets. Actually, there are more for which it's at0x22I believe (and this is not an offset relative to PMBASE).
Yes, that's why I stated that the patch is for ICH3-M, and possibly other ICH-M chipsets in the original mail. I don't know a thing on how C3 is done on other processors and chipsets. I'm willing to learn and implement that (hence my questions about a more general solution for chipset-specific stuff) provided there are potential users. So far, nobody except you and Len has answered. I might try rephrasing the original mail and post it to lkml now that I'm fairly certain the patch doesn't cause any corruption on my system though.
Best regards,
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Karol 'sziwan' Kozimor sziwan-DETuoxkZsSqrDJvtcaxF/[email protected] ------------------------------------------------------- This SF.Net email is sponsored by: Oracle 10g Get certified on the hottest thing ever to hit the market... Oracle 10g. Take an Oracle 10g class now, and we'll give you the exam FREE. http://ads.osdn.com/?ad_id=3149&alloc_id=8166&op=click