eicon/s_4bri: replace schedule_timeout()

@@ -104,13 +104,13 @@ static void reset_qBri_hardware (PISDN_A
 
 	qBriReset = (word volatile *)DIVA_OS_MEM_ATTACH_PROM(IoAdapter);
 	WRITE_WORD(qBriReset, READ_WORD(qBriReset) | PLX9054_SOFT_RESET) ;
-	diva_os_wait (1) ;
+	msleep (1) ;
 	WRITE_WORD(qBriReset, READ_WORD(qBriReset) & ~PLX9054_SOFT_RESET) ;
-	diva_os_wait (1);
+	msleep (1);
 	WRITE_WORD(qBriReset, READ_WORD(qBriReset) | PLX9054_RELOAD_EEPROM) ;
-	diva_os_wait (1) ;
+	msleep (1);
 	WRITE_WORD(qBriReset, READ_WORD(qBriReset) & ~PLX9054_RELOAD_EEPROM) ;
-	diva_os_wait (1);
+	msleep (1);
 	DIVA_OS_MEM_DETACH_PROM(IoAdapter, qBriReset);
 
 	qBriCntrl = DIVA_OS_MEM_ATTACH_CTLREG(IoAdapter);

@@ -132,9 +132,9 @@ void start_qBri_hardware (PISDN_ADAPTER 
 	p = (byte volatile *)DIVA_OS_MEM_ATTACH_CTLREG(IoAdapter);
 	qBriReset = &p[(DIVA_4BRI_REVISION(IoAdapter)) ? (MQ2_BREG_RISC) : (MQ_BREG_RISC)];
 	WRITE_DWORD(qBriReset, MQ_RISC_COLD_RESET_MASK) ;
-	diva_os_wait (2) ;
+	msleep (2) ;
 	WRITE_DWORD(qBriReset, MQ_RISC_WARM_RESET_MASK | MQ_RISC_COLD_RESET_MASK) ;
-	diva_os_wait (10) ;
+	msleep (10) ;
 	DIVA_OS_MEM_DETACH_CTLREG(IoAdapter, p);
 
 	DBG_TRC(("started processor @ addr 0x%08lx", qBriReset))

@@ -316,7 +316,7 @@ int qBri_FPGA_download (PISDN_ADAPTER Io
  */
 	WRITE_WORD(addr, baseval & ~FPGA_PROG) ; /* PROGRAM low pulse */
 	WRITE_WORD(addr, baseval) ;              /* release */
-	diva_os_wait (50) ;  /* wait until FPGA finished internal memory clear */
+	msleep (50) ;  /* wait until FPGA finished internal memory clear */
 /*
  *	check done pin, must be low
  */

@@ -345,7 +345,7 @@ int qBri_FPGA_download (PISDN_ADAPTER Io
 		}
 	}
 	xdiFreeFile (File) ;
-	diva_os_wait (100) ;
+	msleep (100) ;
 	val = READ_WORD(addr) ;
 
 	DIVA_OS_MEM_DETACH_PROM(IoAdapter, addr);

@@ -837,7 +837,7 @@ static int load_qBri_hardware (PISDN_ADA
  */
 	for ( i = 0 ; i < 300 ; ++i )
 	{
-		diva_os_wait (10) ;
+		msleep (10) ;
 
 		if ( signature[0] == 0x4447 )
 		{

@@ -104,13 +104,13 @@ static void reset_qBri_hardware (PISDN_A
 
 	qBriReset = (word volatile *)DIVA_OS_MEM_ATTACH_PROM(IoAdapter);
 	WRITE_WORD(qBriReset, READ_WORD(qBriReset) | PLX9054_SOFT_RESET) ;
-	diva_os_wait (1) ;
+	mdelay (1) ;
 	WRITE_WORD(qBriReset, READ_WORD(qBriReset) & ~PLX9054_SOFT_RESET) ;
-	diva_os_wait (1);
+	mdelay (1);
 	WRITE_WORD(qBriReset, READ_WORD(qBriReset) | PLX9054_RELOAD_EEPROM) ;
-	diva_os_wait (1) ;
+	mdelay (1);
 	WRITE_WORD(qBriReset, READ_WORD(qBriReset) & ~PLX9054_RELOAD_EEPROM) ;
-	diva_os_wait (1);
+	mdelay (1);
 	DIVA_OS_MEM_DETACH_PROM(IoAdapter, qBriReset);
 
 	qBriCntrl = DIVA_OS_MEM_ATTACH_CTLREG(IoAdapter);

@@ -132,9 +132,9 @@ void start_qBri_hardware (PISDN_ADAPTER 
 	p = (byte volatile *)DIVA_OS_MEM_ATTACH_CTLREG(IoAdapter);
 	qBriReset = &p[(DIVA_4BRI_REVISION(IoAdapter)) ? (MQ2_BREG_RISC) : (MQ_BREG_RISC)];
 	WRITE_DWORD(qBriReset, MQ_RISC_COLD_RESET_MASK) ;
-	diva_os_wait (2) ;
+	mdelay (2) ;
 	WRITE_DWORD(qBriReset, MQ_RISC_WARM_RESET_MASK | MQ_RISC_COLD_RESET_MASK) ;
-	diva_os_wait (10) ;
+	mdelay (10) ;
 	DIVA_OS_MEM_DETACH_CTLREG(IoAdapter, p);
 
 	DBG_TRC(("started processor @ addr 0x%08lx", qBriReset))

@@ -316,7 +316,7 @@ int qBri_FPGA_download (PISDN_ADAPTER Io
  */
 	WRITE_WORD(addr, baseval & ~FPGA_PROG) ; /* PROGRAM low pulse */
 	WRITE_WORD(addr, baseval) ;              /* release */
-	diva_os_wait (50) ;  /* wait until FPGA finished internal memory clear */
+	mdelay (50) ;  /* wait until FPGA finished internal memory clear */
 /*
  *	check done pin, must be low
  */

@@ -345,7 +345,7 @@ int qBri_FPGA_download (PISDN_ADAPTER Io
 		}
 	}
 	xdiFreeFile (File) ;
-	diva_os_wait (100) ;
+	mdelay (100) ;
 	val = READ_WORD(addr) ;
 
 	DIVA_OS_MEM_DETACH_PROM(IoAdapter, addr);

@@ -837,7 +837,7 @@ static int load_qBri_hardware (PISDN_ADA
  */
 	for ( i = 0 ; i < 300 ; ++i )
 	{
-		diva_os_wait (10) ;
+		mdelay (10) ;
 
 		if ( signature[0] == 0x4447 )
 		{