cpu features.
PATCH 1/1 cpu features.
Hi,
Attached patch fix/add several cpu features.
refs:
[1] Intel Processor Identification and the CPUID instruction Application Note 485.
http://developer.intel.ru/download/design/Xeon/applnots/24161826.pdf
[2] http://www.sandpile.org/ia32/cpuid.htm
Signature · 3 lines
/* Copyright (C) 2003, SCO, Inc. This is valuable Intellectual Property. */
#define say(x) lie(x)arch/i386/kernel/cpu/proc.c renamed from arch/i386/kernel/cpu/proc.c.orig +2 -2
@@ -44,8 +44,8 @@NULL ,NULL ,NULL ,NULL ,NULL ,NULL ,NULL ,NULL ,/* Intel-defined (#2) */ -"pni" ,NULL ,NULL ,"monitor" ,"ds_cpl" ,NULL ,NULL ,"tm2" , -"est" ,NULL ,"cid" ,NULL ,NULL ,NULL ,NULL ,NULL , +"sse3" ,NULL ,NULL ,"monitor" ,"ds_cpl" ,NULL ,NULL ,"est" , +"tm2" ,NULL ,"cid" ,NULL ,NULL ,NULL ,"xtpr" ,NULL ,NULL ,NULL ,NULL ,NULL ,NULL ,NULL ,NULL ,NULL , NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
arch/x86_64/kernel/setup.c renamed from arch/x86_64/kernel/setup.c.orig +2 -2
@@ -1042,8 +1042,8 @@NULL ,NULL ,NULL ,NULL ,NULL ,NULL ,NULL ,NULL ,/* Intel-defined (#2) */ -"pni" ,NULL ,NULL ,"monitor" ,"ds_cpl" ,NULL ,NULL ,"tm2" , -"est" ,NULL ,"cid" ,NULL ,NULL ,"cmpxchg16b" ,NULL ,NULL , +"sse3" ,NULL ,NULL ,"monitor" ,"ds_cpl" ,NULL ,NULL ,"est" , +"tm2" ,NULL ,"cid" ,NULL ,NULL ,"cx16" ,"xtpr" ,NULL ,NULL ,NULL ,NULL ,NULL ,NULL ,NULL ,NULL ,NULL , NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, };
include/asm-i386/cpufeature.h renamed from include/asm-i386/cpufeature.h.orig +6 -2
@@ -71,9 +71,13 @@#define X86_FEATURE_P4 (3*32+ 7)/* P4 */ /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ -#define X86_FEATURE_EST (4*32+ 7)/* Enhanced SpeedStep */ +#define X86_FEATURE_XMM3 (4*32+ 0)/* Streaming SIMD Extensions-3 */ #define X86_FEATURE_MWAIT (4*32+ 3)/* Monitor/Mwait support */ - +#define X86_FEATURE_DSCPL (4*32+ 4)/* CPL Qualified Debug Store */ +#define X86_FEATURE_EST (4*32+ 7)/* Enhanced SpeedStep */ +#define X86_FEATURE_TM2 (4*32+ 8)/* Thermal Monitor 2 */ +#define X86_FEATURE_CID (4*32+10)/* Context ID */ +#define X86_FEATURE_XTPR (4*32+14)/* Send Task Priority Messages */ /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ #define X86_FEATURE_XSTORE (5*32+ 2)/* on-CPU RNG present (xstore insn) */
include/asm-x86_64/cpufeature.h renamed from include/asm-x86_64/cpufeature.h.orig +7 -1
@@ -63,8 +63,14 @@#define X86_FEATURE_K8_C (3*32+ 4)/* C stepping K8 */ /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ -#define X86_FEATURE_EST (4*32+ 7)/* Enhanced SpeedStep */ +#define X86_FEATURE_XMM3 (4*32+ 0)/* Streaming SIMD Extensions-3 */ #define X86_FEATURE_MWAIT (4*32+ 3)/* Monitor/Mwait support */ +#define X86_FEATURE_DSCPL (4*32+ 4)/* CPL Qualified Debug Store */ +#define X86_FEATURE_EST (4*32+ 7)/* Enhanced SpeedStep */ +#define X86_FEATURE_TM2 (4*32+ 8)/* Thermal Monitor 2 */ +#define X86_FEATURE_CID (4*32+10)/* Context ID */ +#define X86_FEATURE_CX16 (4*32+13)/* CMPXCHG16B */ +#define X86_FEATURE_XTPR (4*32+14)/* Send Task Priority Messages */ #define cpu_has (c, bit) test_bit(bit, (c)->x86_capability)#define boot_cpu_has (bit) test_bit(bit, boot_cpu_data.x86_capability)