C2/C3 don't do anything
Hi all,
I've been playing with Dynamic Tick, where the system timer is stopped for the idle ticks. This allows the system to stay in sleep mode inbetween the skipped ticks. [1] The most recent patch for dynamic-tick is [2]
This works fine on ARM OMAP, but on my i386 boxes I've noticed that only hlt works, C2 and C3 just spin in a busy loop and consume more power than C1 with hlt!
I've done an idle module few years ago that enables C2 for dual Athlon boxes [3], and that involved enabling it in the southbridge.
I thought the current ACPI code enables this already? But it does not seem to be the case?
Should we have some extra code to scan the southbridges, or what is the official way of handling that? It would be nice to get it enabled...
At least my Crusoe based laptop with ALi 1533 chipset and Ali M7101 PMU does not get enabled. (Does anybody have docs to enable it on 1533/1535/7101???)
Cheers,
Tony
[1] http://lkml.org/lkml/2005/1/27/270
[2] http://lkml.org/lkml/2005/1/27/270
[3] http://muru.com/linux/amd-smp-idle/
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Hi,
Quoted 5 lines · Tony Lindgren
I've done an idle module few years ago that enables C2 for dual Athlon boxes [3], and that involved enabling it in the southbridge.
I thought the current ACPI code enables this already? But it does not seem to be the case?
AFAIK, if there is no initialization method included in the ACPI table, the ACPI code does _not_ currently enables some special, vendor-specific bit in southbridges.
Quoted 1 line
Should we have some extra code to scan the southbridges,
Definitely. There is already some "errata" handling in the processor module, possibly this could get extended.
Dominik
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Thus wrote Dominik Brodowski:
Quoted 6 lines
Quoted 5 lines
I've done an idle module few years ago that enables C2 for dual Athlon boxes [3], and that involved enabling it in the southbridge.
I thought the current ACPI code enables this already? But it does not seem to be the case?
Quoted 8 lines
AFAIK, if there is no initialization method included in the ACPI table, the ACPI code does _not_ currently enables some special, vendor-specific bit in southbridges.
Quoted 1 line
Should we have some extra code to scan the southbridges,
Definitely. There is already some "errata" handling in the processor module, possibly this could get extended.
I'm still using the patch to enable C3 on ICHx-M I once posted. Basically, it provided a valid PM2_CNT_BLK address in case the OEM had forgotten to do that, which in turn enabled C3 by providing a valid ARB_DIS address (provided P_LVL3_LAT is valid).
It might be worthwile to add some quirks, possibly opt-in by a commandline option.
Best regards,
Signature · 9 lines
Karol 'sziwan' Kozimor sziwan-DETuoxkZsSqrDJvtcaxF/[email protected] ------------------------------------------------------- This SF.Net email is sponsored by: IntelliVIEW -- Interactive Reporting Tool for open source databases. Create drag-&-drop reports. Save time by over 75%! Publish reports on the web. Export to DOC, XLS, RTF, etc. Download a FREE copy at http://www.intelliview.com/go/osdn_nl
Quoted 10 lines · Karol Kozimor
Thus wrote Dominik Brodowski:
Quoted 9 lines
Quoted 5 lines
I've done an idle module few years ago that enables C2 for dual Athlon boxes [3], and that involved enabling it in the southbridge.
I thought the current ACPI code enables this already? But it does not seem to be the case?
AFAIK, if there is no initialization method included in the ACPI table, the ACPI code does _not_ currently enables some special, vendor-specific bit in southbridges.
OK, can you point me to the file to add printk's in the ACPI code where the initialization happens? I'm not too familiar with ACPI code...
Quoted 9 lines
Quoted 4 lines
Quoted 1 line
Should we have some extra code to scan the southbridges,
Definitely. There is already some "errata" handling in the processor module, possibly this could get extended.
I'm still using the patch to enable C3 on ICHx-M I once posted. Basically, it provided a valid
PM2_CNT_BLKaddress in case the OEM had forgotten to do that, which in turn enabled C3 by providing a validARB_DISaddress (providedP_LVL3_LATis valid).
I have some code for the amd76x_pm module that can be modified for scanning various southbridges. And then add functions for the to enable them. I don't know when I'll have time to play with that though.
This could be a separate module to start with, and then get integrated into the ACPI code later on.
Quoted 2 lines
It might be worthwile to add some quirks, possibly opt-in by a commandline option.
Or it could be an ACPI southbridge module?
Tony
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Quoted 10 lines · Tony Lindgren
Quoted 9 lines
Quoted 4 lines
Quoted 1 line
Should we have some extra code to scan the southbridges,
Definitely. There is already some "errata" handling in the processor module, possibly this could get extended.
I'm still using the patch to enable C3 on ICHx-M I once posted. Basically, it provided a valid
PM2_CNT_BLKaddress in case the OEM had forgotten to do that, which in turn enabled C3 by providing a validARB_DISaddress (providedP_LVL3_LATis valid).
Quoted 7 lines
I have some code for the
amd76x_pmmodule that can be modified for scanning various southbridges. And then add functions for the to enable them. I don't know when I'll have time to play with that though.This could be a separate module to start with, and then get integrated into the ACPI code later on.
Or this could be an extension of drivers/acpi/processor_core.c::acpi_processor_errata() from the beginning. Len, what do you think?
Dominik
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