Infrastructure for interrupt handling.

diff -r 96a4c0de6e53 -r 2d6fd3bba3c2 tools/ioemu/exec-all.h
@@ -573,7 +573,7 @@
 }
 #endif
 
-//#define DEBUG_UNUSED_IOPORT
-//#define DEBUG_IOPORT
+#define DEBUG_UNUSED_IOPORT
+#define DEBUG_IOPORT
 #define TARGET_VMX
 

diff -r 96a4c0de6e53 -r 2d6fd3bba3c2 tools/ioemu/hw/i8259.c
@@ -22,12 +22,16 @@
  * THE SOFTWARE.
  */
 #include "vl.h"
+#include "xc.h"
+#include <io/ioreq.h>
 
 /* debug PIC */
 //#define DEBUG_PIC
 
 //#define DEBUG_IRQ_LATENCY
 #define DEBUG_IRQ_COUNT
+
+extern void pit_reset_vmx_vectors();
 
 typedef struct PicState {
     uint8_t last_irr; /* edge detection */

@@ -121,6 +125,26 @@
     }
 }
 
+/* pic[1] is connected to pin2 of pic[0] */
+#define CASCADE_IRQ 2
+
+static void shared_page_update()
+{
+    extern shared_iopage_t *shared_page;
+    uint8_t * pmask = (uint8_t *)&(shared_page->sp_global.pic_mask[0]);
+    int           index;
+
+    index = pics[0].irq_base/8;
+    pmask[index] = pics[0].imr;
+    index = pics[1].irq_base/8;
+
+    if ( pics[0].imr &  (1 << CASCADE_IRQ) ) {
+        pmask[index] = 0xff;
+    } else {
+        pmask[index] = pics[1].imr;
+    }
+}
+
 /* raise irq to CPU if necessary. must be called every time the active
    irq may change */
 static void pic_update_irq(void)

@@ -150,14 +174,18 @@
 #endif
         cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
     }
+    shared_page_update();
 }
 
 #ifdef DEBUG_IRQ_LATENCY
 int64_t irq_time[16];
 #endif
 
+extern void ioapic_legacy_irq(int irq, int level);
+
 void pic_set_irq(int irq, int level)
 {
+    ioapic_legacy_irq(irq, level);
 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
     if (level != irq_level[irq]) {
 #if defined(DEBUG_PIC)

@@ -255,6 +283,7 @@
     tmp = s->elcr_mask;
     memset(s, 0, sizeof(PicState));
     s->elcr_mask = tmp;
+    shared_page_update();
 }
 
 static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)

diff -r 96a4c0de6e53 -r 2d6fd3bba3c2 tools/ioemu/target-i386-dm/helper2.c
@@ -320,7 +320,7 @@
 
 	// Send a message on the event channel. Add the vector to the shared mem
 	// page.
-	intr = &(shared_page->vcpu_iodata[0].vp_intr[0]);
+	intr = &(shared_page->sp_global.pic_intr[0]);
 	atomic_set_bit(vector, intr);
         if (loglevel & CPU_LOG_INT)
                 fprintf(logfile, "injecting vector: %x\n", vector);

@@ -345,11 +345,11 @@
 	FD_ZERO(&rfds);
 
 	while (1) {
-            if (vm_running) {
-                if (shutdown_requested) {
-                    break;
+                if (vm_running) {
+                    if (shutdown_requested) {
+                        break;
+                    }
                 }
-            }
 
 		/* Wait up to one seconds. */
 		tv.tv_sec = 0;

@@ -370,14 +370,19 @@
 #endif
 
 		main_loop_wait(0);
-
+#ifdef APIC_SUPPORT
+		ioapic_update_EOI();
+#endif
 		cpu_timer_handler(env);
 		if (env->interrupt_request & CPU_INTERRUPT_HARD) {
                         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 			vector = cpu_get_pic_interrupt(env); 
 			do_interrupt(env, vector);
 		}
-
+#ifdef APIC_SUPPORT
+		if (ioapic_has_intr())
+                    do_ioapic();
+#endif
 		if (env->send_event) {
 			int ret;
 			ret = xc_evtchn_send(xc_handle, ioreq_port);

diff -r 96a4c0de6e53 -r 2d6fd3bba3c2 xen/include/asm-x86/vmx.h
@@ -339,14 +339,19 @@
     return (cr0 & X86_CR0_PE) && (cr0 & X86_CR0_PG);
 }
 
+static inline shared_iopage_t *get_sp(struct domain *d)
+{
+    return (shared_iopage_t *) d->arch.vmx_platform.shared_page_va;
+}
+
 static inline vcpu_iodata_t *get_vio(struct domain *d, unsigned long cpu)
 {
-    return &((shared_iopage_t *) d->arch.vmx_platform.shared_page_va)->vcpu_iodata[cpu];
+    return &get_sp(d)->vcpu_iodata[cpu];
 }
 
 static inline int iopacket_port(struct domain *d)
 {
-    return ((shared_iopage_t *) d->arch.vmx_platform.shared_page_va)->sp_global.eport;
+    return get_sp(d)->sp_global.eport;
 }
 
 #endif /* __ASM_X86_VMX_H__ */

diff -r 96a4c0de6e53 -r 2d6fd3bba3c2 xen/arch/x86/vmx_vmcs.c
@@ -153,6 +153,8 @@
     p = map_domain_page(mpfn);
     d->domain->arch.vmx_platform.shared_page_va = (unsigned long)p;
 
+   VMX_DBG_LOG(DBG_LEVEL_1, "eport: %x\n", iopacket_port(d->domain));
+
    clear_bit(iopacket_port(d->domain), 
              &d->domain->shared_info->evtchn_mask[0]);
 

diff -r 96a4c0de6e53 -r 2d6fd3bba3c2 xen/include/asm-x86/vmx_virpit.h
@@ -20,7 +20,7 @@
     int vector;				/* the pit irq vector */
     unsigned int period;		/* the frequency. e.g. 10ms*/
     unsigned int channel;		/* the pit channel, counter 0~2 */
-    unsigned long *intr_bitmap;
+    u64  *intr_bitmap;
     unsigned int pending_intr_nr;	/* the couner for pending timer interrupts */
     unsigned long long inject_point;	/* the time inject virt intr */
     struct ac_timer pit_timer;		/* periodic timer for mode 2*/

diff -r 96a4c0de6e53 -r 2d6fd3bba3c2 tools/ioemu/hw/pc.c
@@ -543,6 +543,9 @@
             pci_ne2000_init(pci_bus, &nd_table[i]);
         }
         pci_piix3_ide_init(pci_bus, bs_table);
+#ifdef APIC_SUPPORT
+        IOAPICInit();
+#endif
     } else {
         nb_nics1 = nb_nics;
         if (nb_nics1 > NE2000_NB_MAX)

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diff -r 96a4c0de6e53 -r 2d6fd3bba3c2 xen/arch/x86/vmx_intercept.c
@@ -213,7 +213,8 @@
 {
     vcpu_iodata_t * vio = get_vio(d->domain, d->vcpu_id);
     ioreq_t *p = &vio->vp_ioreq;
-    unsigned long *intr = &(vio->vp_intr[0]);
+    shared_iopage_t *sp = get_sp(d->domain);
+    u64 *intr = &(sp->sp_global.pic_intr[0]);
     struct vmx_virpit_t *vpit = &(d->domain->arch.vmx_platform.vmx_pit);
     int rw_mode;
 

diff -r 96a4c0de6e53 -r 2d6fd3bba3c2 tools/ioemu/hw/pci.c
@@ -53,6 +53,7 @@
 static int pci_irq_index;
 static uint32_t pci_irq_levels[4][PCI_IRQ_WORDS];
 static PCIBus *first_bus;
+extern FILE *logfile;
 
 static PCIBus *pci_register_bus(void)
 {

@@ -569,13 +570,26 @@
     pci_conf[0xae] = 0x00;
 }
 
+#define PIIX_CONFIG_XBCS 0x4f
+void piix3_write_config(PCIDevice *d,
+  uint32_t address, uint32_t val, int len)
+{
+    if ((PIIX3State *)d != piix3_state){
+        fprintf(logfile, "piix3_write_config: error PCIDevice\n");
+        return;
+    }
+
+    pci_default_write_config(d, address, val, len);
+}
+
+
 void piix3_init(PCIBus *bus)
 {
     PIIX3State *d;
     uint8_t *pci_conf;
 
     d = (PIIX3State *)pci_register_device(bus, "PIIX3", sizeof(PIIX3State),
-                                          -1, NULL, NULL);
+                                          -1, NULL, piix3_write_config);
     register_savevm("PIIX3", 0, 1, generic_pci_save, generic_pci_load, d);
 
     piix3_state = d;

diff -r 96a4c0de6e53 -r 2d6fd3bba3c2 xen/include/public/io/ioreq.h
@@ -49,14 +49,11 @@
 
 #define MAX_VECTOR    256
 #define BITS_PER_BYTE   8
-#define INTR_LEN        (MAX_VECTOR/(BITS_PER_BYTE * sizeof(unsigned long)))
+#define INTR_LEN        (MAX_VECTOR/(BITS_PER_BYTE * sizeof(u64)))
 
-/* We only track the master PIC state here */
 typedef struct {
-    uint16_t irr; /* interrupt request register */
-    uint16_t imr; /* interrupt mask register */
-    uint16_t isr; /* interrupt service register */
-
+    u64   pic_intr[INTR_LEN];
+    u64   pic_mask[INTR_LEN];
     int     eport; /* Event channel port */
 } global_iodata_t;
 

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