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Fix Cobalt PCI cache line sizes

PATCH Applied Peter Horton 2 participants 2 messages Jan 29, 2006 – Jan 30, 2006 MIPS

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Peter Horton

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#0 lore raw

PATCH 1/1 Fix Cobalt PCI cache line sizes

Correct cache line sizes.

P.

arch/mips/pci/fixup-cobalt.c +2 -2
Index: linux.git/arch/mips/pci/fixup-cobalt.c
===================================================================
@@ -52,7 +52,7 @@
 	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lt);
 	if (lt < 64)
 		pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
-	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7);
+	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
 }
 
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,

@@ -69,7 +69,7 @@
 	 * host bridge.
 	 */
 	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
-	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7);
+	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
 
 	/*
 	 * The code described by the comment below has been removed
Applied
#1 lore raw
Quoted 1 line · Peter Horton

Correct cache line sizes.

Thanks, applied.

Ralf

PS: If you would please add the Signed-off-by lines also in the future.