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S3C2412 TACLS rate calculation fix

PATCH In review Ben Dooks 3 participants 3 messages Feb 13, 2007

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Memory technology devices (MTD) Arm Samsung Exynos NAND flash
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Ben Dooks

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#0 lore raw

PATCH 1/1 S3C2412 TACLS rate calculation fix

The TALCs value on the S3C2412 value does not have an +1 adjustment unlike the S3C2410 and S3C2440.

The TALCs value on the S3C2440 is only 2 bits instead of three, so change it to a maximum of 4.

Re-work of an patch by Matt Reimer <[email protected]>

Signed-off-by Ben Dooks <[email protected]>
drivers/mtd/nand/s3c2410.c +11 -6
diff -urpN -X ../dontdiff linux-2.6.20-rmk-12feb2007/drivers/mtd/nand/s3c2410.c linux-2.6.20-rmk-12feb2007-bjd1/drivers/mtd/nand/s3c2410.c
@@ -183,15 +183,17 @@ static int s3c2410_nand_inithw(struct s3
 {
 	struct s3c2410_platform_nand *plat = to_nand_plat(pdev);
 	unsigned long clkrate = clk_get_rate(info->clk);
-	int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4;
+	int tacls_max = (info->cpu_type == TYPE_S3C2440) ? 3 : 7;
+	int tacls_adj = (info->cpu_type == TYPE_S3C2412) ? 0 : -1;
 	int tacls, twrph0, twrph1;
 	unsigned long cfg = 0;
 
 	/* calculate the timing information for the controller */
 
 	clkrate /= 1000;	/* turn clock into kHz for ease of use */
+	tacls_max -= tacls_adj;
 
-	if (plat != NULL) {
+	if (plat != NULL) {	
 		tacls = s3c_nand_calc_rate(plat->tacls, clkrate, tacls_max);
 		twrph0 = s3c_nand_calc_rate(plat->twrph0, clkrate, 8);
 		twrph1 = s3c_nand_calc_rate(plat->twrph1, clkrate, 8);

@@ -207,20 +209,23 @@ static int s3c2410_nand_inithw(struct s3
 		return -EINVAL;
 	}
 
-	dev_info(info->device, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n",
-	       tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate), twrph1, to_ns(twrph1, clkrate));
+	dev_info(info->device,
+		 "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n",
+		 tacls, to_ns(tacls, clkrate),
+		 twrph0, to_ns(twrph0, clkrate),
+		 twrph1, to_ns(twrph1, clkrate));
 
  	switch (info->cpu_type) {
  	case TYPE_S3C2410:
 		cfg = S3C2410_NFCONF_EN;
-		cfg |= S3C2410_NFCONF_TACLS(tacls - 1);
+		cfg |= S3C2410_NFCONF_TACLS(tacls + tacls_adj);
 		cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
 		cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
 		break;
 
  	case TYPE_S3C2440:
  	case TYPE_S3C2412:
-		cfg = S3C2440_NFCONF_TACLS(tacls - 1);
+		cfg = S3C2440_NFCONF_TACLS(tacls + tacls_adj);
 		cfg |= S3C2440_NFCONF_TWRPH0(twrph0 - 1);
 		cfg |= S3C2440_NFCONF_TWRPH1(twrph1 - 1);
#1 lore raw
Quoted 9 lines · Ben Dooks <ben <at> fluff.org.uk> writes:

The TALCs value on the S3C2412 value does not have an +1 adjustment unlike the S3C2410 and S3C2440.

The TALCs value on the S3C2440 is only 2 bits instead of three, so change it to a maximum of 4.

Re-work of an patch by Matt Reimer <mreimer <at> vpop.net>

Doesn't we lose the part that allow tacls to be 0 ?

Matthieu

#2 lore raw
Quoted 6 lines · Matthieu CASTET
Quoted 4 lines · Ben Dooks <ben <at> fluff.org.uk> writes:

The TALCs value on the S3C2412 value does not have an +1 adjustment unlike the S3C2410 and S3C2440.

Quoted 6 lines
Quoted 5 lines

The TALCs value on the S3C2440 is only 2 bits instead of three, so change it to a maximum of 4.

Re-work of an patch by Matt Reimer <mreimer <at> vpop.net>

Doesn't we lose the part that allow tacls to be 0 ?

Yes, we need that so 2410 can use 0 (which translates to 10 ns).

Also, I sent another patch that seems to have gotten hung up by the ml:

drivers/mtd/nand/s3c2410.c.patched Tue Jan 30 12:15:08 2007 renamed from drivers/mtd/nand/s3c2410.c Tue Jan 30 12:15:08 2007 +2 -1
@@ -159,7 +159,8 @@ static int s3c_nand_calc_rate(int wanted
       int result;
 
       result = (wanted * clk) / NS_IN_KHZ;
-       result++;
+       if (((wanted * clk) % NS_IN_KHZ) != 0)
+               result++;
 
       pr_debug("result %d from %ld, %d\n", result, clk, wanted);

(Thanks the in-line clue Ben.)

Matt