Intel IOMMU Support

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Index: linux-2.6.21-rc5/include/acpi/actbl1.h
===================================================================
@@ -257,7 +257,8 @@
 struct acpi_table_dmar {
 	struct acpi_table_header header;	/* Common ACPI table header */
 	u8 width;		/* Host Address Width */
-	u8 reserved[11];
+	u8 flags;
+	u8 reserved[10];
 };
 
 /* DMAR subtable header */

@@ -265,8 +266,6 @@
 struct acpi_dmar_header {
 	u16 type;
 	u16 length;
-	u8 flags;
-	u8 reserved[3];
 };
 
 /* Values for subtable type in struct acpi_dmar_header */

@@ -274,13 +273,15 @@
 enum acpi_dmar_type {
 	ACPI_DMAR_TYPE_HARDWARE_UNIT = 0,
 	ACPI_DMAR_TYPE_RESERVED_MEMORY = 1,
-	ACPI_DMAR_TYPE_RESERVED = 2	/* 2 and greater are reserved */
+	ACPI_DMAR_TYPE_ATSR = 2,
+	ACPI_DMAR_TYPE_RESERVED = 3	/* 3 and greater are reserved */
 };
 
 struct acpi_dmar_device_scope {
 	u8 entry_type;
 	u8 length;
-	u8 segment;
+	u16 reserved;
+	u8 enumeration_id;
 	u8 bus;
 };
 

@@ -290,7 +291,14 @@
 	ACPI_DMAR_SCOPE_TYPE_NOT_USED = 0,
 	ACPI_DMAR_SCOPE_TYPE_ENDPOINT = 1,
 	ACPI_DMAR_SCOPE_TYPE_BRIDGE = 2,
-	ACPI_DMAR_SCOPE_TYPE_RESERVED = 3	/* 3 and greater are reserved */
+	ACPI_DMAR_SCOPE_TYPE_IOAPIC = 3,
+	ACPI_DMAR_SCOPE_TYPE_HPET = 4,
+	ACPI_DMAR_SCOPE_TYPE_RESERVED = 5	/* 5 and greater are reserved */
+};
+
+struct acpi_dmar_pci_path {
+	u8 dev;
+	u8 fn;
 };
 
 /*

@@ -301,6 +309,9 @@
 
 struct acpi_dmar_hardware_unit {
 	struct acpi_dmar_header header;
+	u8 flags;
+	u8 reserved;
+	u16 segment;
 	u64 address;		/* Register Base Address */
 };
 

@@ -312,7 +323,9 @@
 
 struct acpi_dmar_reserved_memory {
 	struct acpi_dmar_header header;
-	u64 address;		/* 4_k aligned base address */
+	u16 reserved;
+	u16 segment;
+	u64 base_address;		/* 4_k aligned base address */
 	u64 end_address;	/* 4_k aligned limit address */
 };
 

Index: 2.6.21-rc6/drivers/pci/pci.h
===================================================================
@@ -90,3 +90,4 @@ pci_match_one_device(const struct pci_de
 	return NULL;
 }
 
+struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev);

Index: 2.6.21-rc6/drivers/pci/probe.c
===================================================================
@@ -822,6 +822,19 @@ static void pci_release_dev(struct devic
 	kfree(pci_dev);
 }
 
+static void set_pcie_port_type(struct pci_dev *pdev)
+{
+	int pos;
+	u16 reg16;
+
+	pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
+	if (!pos)
+		return;
+	pdev->is_pcie = 1;
+	pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
+	pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
+}
+
 /**
  * pci_cfg_space_size - get the configuration space size of the PCI device.
  * @dev: PCI device

@@ -919,6 +932,7 @@ pci_scan_device(struct pci_bus *bus, int
 	dev->device = (l >> 16) & 0xffff;
 	dev->cfg_size = pci_cfg_space_size(dev);
 	dev->error_state = pci_channel_io_normal;
+	set_pcie_port_type(dev);
 
 	/* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
 	   set this higher, assuming the system even supports it.  */

Index: 2.6.21-rc6/drivers/pci/search.c
===================================================================
@@ -14,6 +14,36 @@
 #include "pci.h"
 
 DECLARE_RWSEM(pci_bus_sem);
+/*
+ * find the upstream PCIE-to-PCI bridge of a PCI device
+ * if the device is PCIE, return NULL
+ * if the device isn't connected to a PCIE bridge (that is its parent is a
+ * legacy PCI bridge and the bridge is directly connected to bus 0), return its
+ * parent
+ */
+struct pci_dev *
+pci_find_upstream_pcie_bridge(struct pci_dev *pdev)
+{
+	struct pci_dev *tmp = NULL;
+
+	if (pdev->is_pcie)
+		return NULL;
+	while (1) {
+		if (!pdev->bus->self)
+			break;
+		pdev = pdev->bus->self;
+		/* a p2p bridge */
+		if (!pdev->is_pcie) {
+			tmp = pdev;
+			continue;
+		}
+		/* PCI device should connect to a PCIE bridge */
+		BUG_ON(pdev->pcie_type != PCI_EXP_TYPE_PCI_BRIDGE);
+		return pdev;
+	}
+
+	return tmp;
+}
 
 static struct pci_bus *
 pci_do_find_bus(struct pci_bus* bus, unsigned char busnr)

Index: 2.6.21-rc6/include/linux/pci.h
===================================================================
@@ -126,6 +126,7 @@ struct pci_dev {
 	unsigned short	subsystem_device;
 	unsigned int	class;		/* 3 bytes: (base,sub,prog-if) */
 	u8		hdr_type;	/* PCI header type (`multi' flag masked out) */
+	u8		pcie_type;	/* PCI-E device/port type */
 	u8		rom_base_reg;	/* which config register controls the ROM */
 	u8		pin;  		/* which interrupt pin this device uses */
 

@@ -168,6 +169,7 @@ struct pci_dev {
 	unsigned int 	msi_enabled:1;
 	unsigned int	msix_enabled:1;
 	unsigned int	is_managed:1;
+	unsigned int	is_pcie:1;
 	atomic_t	enable_cnt;	/* pci_enable_device has been called */
 
 	u32		saved_config_space[16]; /* config space saved at suspend time */

Index: 2.6.21-rc6/arch/x86_64/kernel/io_apic.c
===================================================================
@@ -32,6 +32,7 @@
 #include <linux/sysdev.h>
 #include <linux/msi.h>
 #include <linux/htirq.h>
+#include <linux/intel-iommu.h>
 #ifdef CONFIG_ACPI
 #include <acpi/acpi_bus.h>
 #endif

@@ -2002,8 +2003,64 @@ void arch_teardown_msi_irq(unsigned int 
 	destroy_irq(irq);
 }
 
-#endif /* CONFIG_PCI_MSI */
+#ifdef CONFIG_DMAR
+#ifdef CONFIG_SMP
+static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
+{
+	struct irq_cfg *cfg = irq_cfg + irq;
+	struct msi_msg msg;
+	unsigned int dest;
+	cpumask_t tmp;
+
+	cpus_and(tmp, mask, cpu_online_map);
+	if (cpus_empty(tmp))
+		return;
+
+	if (assign_irq_vector(irq, mask))
+		return;
+
+	cpus_and(tmp, cfg->domain, mask);
+	dest = cpu_mask_to_apicid(tmp);
+
+	dmar_msi_read(irq, &msg);
+
+	msg.data &= ~MSI_DATA_VECTOR_MASK;
+	msg.data |= MSI_DATA_VECTOR(cfg->vector);
+	msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
+	msg.address_lo |= MSI_ADDR_DEST_ID(dest);
+
+	dmar_msi_write(irq, &msg);
+	irq_desc[irq].affinity = mask;
+}
+#endif /* CONFIG_SMP */
+
+struct irq_chip dmar_msi_type = {
+	.name = "DMAR_MSI",
+	.unmask = dmar_msi_unmask,
+	.mask = dmar_msi_mask,
+	.ack = ack_apic_edge,
+#ifdef CONFIG_SMP
+	.set_affinity = dmar_msi_set_affinity,
+#endif
+	.retrigger = ioapic_retrigger_irq,
+};
+
+int arch_setup_dmar_msi(unsigned int irq)
+{
+	int ret;
+	struct msi_msg msg;
+
+	ret = msi_compose_msg(NULL, irq, &msg);
+	if (ret < 0)
+		return ret;
+	dmar_msi_write(irq, &msg);
+	set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
+		"edge");
+	return 0;
+}
+#endif
 
+#endif /* CONFIG_PCI_MSI */
 /*
  * Hypertransport interrupt support
  */

Index: 2.6.21-rc6/arch/x86_64/kernel/pci-dma.c
===================================================================
@@ -7,6 +7,7 @@
 #include <linux/string.h>
 #include <linux/pci.h>
 #include <linux/module.h>
+#include <linux/intel-iommu.h>
 #include <asm/io.h>
 #include <asm/proto.h>
 #include <asm/calgary.h>

@@ -303,6 +304,10 @@ void __init pci_iommu_alloc(void)
 	detect_calgary();
 #endif
 
+#ifdef CONFIG_DMAR
+	detect_intel_iommu();
+#endif
+
 #ifdef CONFIG_SWIOTLB
 	pci_swiotlb_init();
 #endif

@@ -314,6 +319,10 @@ static int __init pci_iommu_init(void)
 	calgary_iommu_init();
 #endif
 
+#ifdef CONFIG_DMAR
+	intel_iommu_init();
+#endif
+
 #ifdef CONFIG_IOMMU
 	gart_iommu_init();
 #endif

Index: 2.6.21-rc6/arch/x86_64/mm/pageattr.c
===================================================================
@@ -61,10 +61,10 @@ static struct page *split_large_page(uns
 	return base;
 } 
 
-static void cache_flush_page(void *adr)
+void clflush_cache_range(void *adr, int size)
 {
 	int i;
-	for (i = 0; i < PAGE_SIZE; i += boot_cpu_data.x86_clflush_size)
+	for (i = 0; i < size; i += boot_cpu_data.x86_clflush_size)
 		asm volatile("clflush (%0)" :: "r" (adr + i));
 }
 

@@ -80,7 +80,7 @@ static void flush_kernel_map(void *arg)
 	list_for_each_entry(pg, l, lru) {
 		void *adr = page_address(pg);
 		if (cpu_has_clflush)
-			cache_flush_page(adr);
+			clflush_cache_range(adr, PAGE_SIZE);
 		__flush_tlb_one(adr);
 	}
 }

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Index: 2.6.21-rc6/include/asm-x86_64/cacheflush.h
===================================================================
@@ -27,6 +27,7 @@
 void global_flush_tlb(void); 
 int change_page_attr(struct page *page, int numpages, pgprot_t prot);
 int change_page_attr_addr(unsigned long addr, int numpages, pgprot_t prot);
+void clflush_cache_range(void *addr, int size);
 
 #ifdef CONFIG_DEBUG_RODATA
 void mark_rodata_ro(void);

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Index: 2.6.21-rc6/drivers/pci/intel-iommu.c
===================================================================
@@ -84,7 +84,7 @@ struct iommu {
 	struct sys_device sysdev;
 };
 
-static int dmar_disabled;
+static int dmar_disabled, dmar_force_rw;
 
 static char *get_fault_reason(u8 fault_reason)
 {

@@ -102,6 +102,9 @@ static int __init intel_iommu_setup(char
 		if (!strncmp(str, "off", 3)) {
 			dmar_disabled = 1;
 			printk(KERN_INFO"Intel-IOMMU: disabled\n");
+		} else if (!strncmp(str, "forcerw", 7)) {
+			dmar_force_rw = 1;
+			printk(KERN_INFO"Intel-IOMMU: force R/W for W/O mapping\n");
 		}
 		str += strcspn(str, ",");
 		while (*str == ',')

@@ -1720,7 +1723,12 @@ static dma_addr_t __intel_map_single(str
 			goto error;
 	}
 
-	if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL)
+	/*
+	 * Check if DMAR supports zero-length reads on write only
+	 * mappings..
+	 */
+	if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
+			!cap_zlr(domain->iommu->cap) || dmar_force_rw)
 		prot |= DMA_PTE_READ;
 	if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
 		prot |= DMA_PTE_WRITE;

Index: 2.6.21-rc6/include/linux/intel-iommu.h
===================================================================
@@ -79,6 +79,7 @@
 #define cap_max_fault_reg_offset(c) \
 	(cap_fault_reg_offset(c) + cap_num_fault_regs(c) * 16)
 
+#define cap_zlr(c)		(((c) >> 22) & 1)
 #define cap_isoch(c)		(((c) >> 23) & 1)
 #define cap_mgaw(c)		((((c) >> 16) & 0x3f) + 1)
 #define cap_sagaw(c)		(((c) >> 8) & 0x1f)

Index: 2.6.21-rc6/arch/x86_64/kernel/e820.c
===================================================================
@@ -730,3 +730,22 @@ __init void e820_setup_gap(void)
 	printk(KERN_INFO "Allocating PCI resources starting at %lx (gap: %lx:%lx)\n",
 		pci_mem_start, gapstart, gapsize);
 }
+
+int __init arch_get_ram_range(int slot, u64 *addr, u64 *size)
+{
+	int i;
+
+	if (slot < 0 || slot >= e820.nr_map)
+		return -1;
+	for (i = slot; i < e820.nr_map; i++) {
+		if(e820.map[i].type != E820_RAM)
+			continue;
+		break;
+	}
+	if (i == e820.nr_map || e820.map[i].addr > (max_pfn << PAGE_SHIFT))
+		return -1;
+	*addr = e820.map[i].addr;
+	*size = min_t(u64, e820.map[i].size + e820.map[i].addr,
+		max_pfn << PAGE_SHIFT) - *addr;
+	return i + 1;
+}

Index: 2.6.21-rc6/drivers/pci/dmar.h
===================================================================
@@ -35,6 +35,7 @@ struct dmar_drhd_unit {
 	int	devices_cnt;
 	u8	include_all:1;
 	struct iommu *iommu;
+	int	ignored:1; /* the drhd should be ignored */
 };
 
 struct dmar_rmrr_unit {

226 lines not on this page · raw message

Index: 2.6.21-rc6/include/linux/intel-iommu.h
===================================================================
@@ -263,6 +263,8 @@ extern void dmar_msi_read(int irq, struc
 extern void dmar_msi_write(int irq, struct msi_msg *msg);
 extern int arch_setup_dmar_msi(unsigned int irq);
 
+extern int arch_get_ram_range(int slot, u64 *addr, u64 *size);
+
 extern int init_dmars(void);
 extern void detect_intel_iommu(void);
 extern int early_dmar_detect(void);

Index: linux-2.6.21-rc5/drivers/pci/intel-iommu.c
===================================================================
@@ -37,6 +37,8 @@
 #include "pci.h"
 
 #define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
+#define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
+
 #define IOAPIC_RANGE_START	(0xfee00000)
 #define IOAPIC_RANGE_END	(0xfeefffff)
 #define IOAPIC_RANGE_SIZE	(IOAPIC_RANGE_END - IOAPIC_RANGE_START + 1)

@@ -87,6 +89,7 @@
 
 static int dmar_disabled, dmar_force_rw;
 static int dmar_map_gfx = 1, dmar_no_gfx_identity_map = 1;
+static int dmar_fix_isa = 1;
 
 static char *get_fault_reason(u8 fault_reason)
 {

@@ -113,6 +116,9 @@
 		} else if (!strncmp(str, "gfx_workaround", 14)) {
 			dmar_no_gfx_identity_map = 0;
 			printk(KERN_INFO"Intel-IOMMU: do 1-1 mapping whole physical memory for GFX device\n");
+		} else if (!strncmp(str, "noisamap", 8)) {
+			dmar_fix_isa = 0;
+			printk (KERN_INFO"Intel-IOMMU: Turning off 16M unity map for LPC\n");
 		}
 
 		str += strcspn(str, ",");

@@ -1582,6 +1588,25 @@
 	}
 }
 
+static void iommu_prepare_isa(void)
+{
+	struct pci_dev *pdev = NULL;
+	int ret;
+
+	if (!dmar_fix_isa)
+		return;
+
+	pdev = pci_get_class (PCI_CLASS_BRIDGE_ISA << 8, NULL);
+	if (!pdev)
+		return;
+
+	printk (KERN_INFO "IOMMU: Prepare 0-16M unity mapping for LPC\n");
+	ret = iommu_prepare_identity_map(pdev, 0, 16*1024*1024);
+
+	if (ret)
+		printk ("IOMMU: Failed to create 0-64M identity map, Floppy might not work\n");
+
+}
 int __init init_dmars(void)
 {
 	struct dmar_drhd_unit *drhd;

@@ -1638,6 +1663,7 @@
 	end_for_each_rmrr_device(rmrr, pdev)
 
 	iommu_prepare_gfx_mapping();
+	iommu_prepare_isa();
 
 	/*
 	 * for each drhd

Index: linux-2.6.21-rc5/drivers/pci/intel-iommu.c
===================================================================
@@ -90,6 +90,7 @@
 static int dmar_disabled, dmar_force_rw;
 static int dmar_map_gfx = 1, dmar_no_gfx_identity_map = 1;
 static int dmar_fix_isa = 1;
+static u64 dmar_preserve_iova_mask;
 
 static char *get_fault_reason(u8 fault_reason)
 {

@@ -119,6 +120,32 @@
 		} else if (!strncmp(str, "noisamap", 8)) {
 			dmar_fix_isa = 0;
 			printk (KERN_INFO"Intel-IOMMU: Turning off 16M unity map for LPC\n");
+ 		} else if (!strncmp(str, "preserve_", 9)) {
+ 			if (!strncmp(str + 9, "4g", 2) ||
+ 			    !strncmp(str + 9, "4G", 2))
+ 				dmar_preserve_iova_mask = DMA_32BIT_MASK;
+ 			else if (!strncmp(str + 9, "2g", 2) ||
+ 				!strncmp(str + 9, "2G", 2))
+ 				dmar_preserve_iova_mask = DMA_31BIT_MASK;
+ 			else if (!strncmp(str + 9, "1g", 2) ||
+ 			         !strncmp(str + 9, "1G", 2))
+ 				dmar_preserve_iova_mask = DMA_30BIT_MASK;
+ 			else if (!strncmp(str + 9, "512m", 2) ||
+ 			         !strncmp(str + 9, "512M", 2))
+ 				dmar_preserve_iova_mask = DMA_29BIT_MASK;
+ 			else if (!strncmp(str + 9, "256m", 4) ||
+ 			         !strncmp(str + 9, "256M", 4))
+ 				dmar_preserve_iova_mask = DMA_28BIT_MASK;
+ 			else if (!strncmp(str + 9, "16m", 3) ||
+ 			         !strncmp(str + 9, "16M", 3))
+ 				dmar_preserve_iova_mask = DMA_24BIT_MASK;
+			if (dmar_preserve_iova_mask)
+				printk(KERN_INFO
+				"DMAR: Preserved IOVA mask 0x%Lx for devices "
+				"sharing domain\n", dmar_preserve_iova_mask);
+			else
+				printk(KERN_ERR"DMAR: Unsuppored preserve mask"
+					" provided");
 		}
 
 		str += strcspn(str, ",");

@@ -1723,7 +1750,6 @@
 			last_addr : IOVA_START_ADDR);
 	}
 	return last_addr;
-
 }
 #endif
 

@@ -1751,13 +1777,14 @@
 
 	/*
 	 * If the device shares a domain with other devices and the device can
-	 * handle > 4G DMA, let the device use DMA address started from 4G, so to
-	 * leave rooms for other devices
+	 * can handle higher address, leave rooms for devices that cant
+	 * address high address ranges.
 	 */
 	if ((domain->flags & DOMAIN_FLAG_MULTIPLE_DEVICES) &&
-			pdev->dma_mask > DMA_32BIT_MASK)
+ 			dmar_preserve_iova_mask &&
+ 			(pdev->dma_mask > dmar_preserve_iova_mask))
 		iova = alloc_iova(domain, addr, size,
-				DMA_32BIT_MASK + 1, pdev->dma_mask);
+ 				dmar_preserve_iova_mask + 1, pdev->dma_mask);
 	else {
 #ifndef CONFIG_IOVA_NEXT_CONTIG
 		iova = alloc_iova(domain, addr, size,