PRCM cleanup - remove prcm-regs.h

new file mode 100644
index 0000000..6275cae
@@ -0,0 +1,37 @@
+#ifndef __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
+#define __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
+
+/*
+ * OMAP2 PRCM base and module definitions
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+
+/* Module offsets from both CM_BASE & PRM_BASE */
+
+/* Offsets that are the same on 24xx and 34xx */
+/* Technically OCP_MOD is 34xx only, and PLL_MOD is CCR_MOD on 3430 */
+#define OCP_MOD						0x000
+#define MPU_MOD						0x100
+#define CORE_MOD					0x200
+#define GFX_MOD						0x300
+#define WKUP_MOD					0x400
+#define PLL_MOD						0x500
+
+
+/* Chip-specific module offsets */
+#define OMAP24XX_DSP_MOD				0x800
+
+#define OMAP2430_MDM_MOD				0xc00
+
+
+#endif
+

index 6275cae..5220b05 100644
@@ -33,5 +33,110 @@
 #define OMAP2430_MDM_MOD				0xc00
 
 
+/* 24XX register bits shared between CM & PRM registers */
+
+/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
+#define OMAP2420_EN_MMC_SHIFT				26
+#define OMAP2420_EN_MMC					(1 << 26)
+#define OMAP24XX_EN_UART2_SHIFT				22
+#define OMAP24XX_EN_UART2				(1 << 22)
+#define OMAP24XX_EN_UART1_SHIFT				21
+#define OMAP24XX_EN_UART1				(1 << 21)
+#define OMAP24XX_EN_MCSPI2_SHIFT			18
+#define OMAP24XX_EN_MCSPI2				(1 << 18)
+#define OMAP24XX_EN_MCSPI1_SHIFT			17
+#define OMAP24XX_EN_MCSPI1				(1 << 17)
+#define OMAP24XX_EN_MCBSP2_SHIFT			16
+#define OMAP24XX_EN_MCBSP2				(1 << 16)
+#define OMAP24XX_EN_MCBSP1_SHIFT			15
+#define OMAP24XX_EN_MCBSP1				(1 << 15)
+#define OMAP24XX_EN_GPT12_SHIFT				14
+#define OMAP24XX_EN_GPT12				(1 << 14)
+#define OMAP24XX_EN_GPT11_SHIFT				13
+#define OMAP24XX_EN_GPT11				(1 << 13)
+#define OMAP24XX_EN_GPT10_SHIFT				12
+#define OMAP24XX_EN_GPT10				(1 << 12)
+#define OMAP24XX_EN_GPT9_SHIFT				11
+#define OMAP24XX_EN_GPT9				(1 << 11)
+#define OMAP24XX_EN_GPT8_SHIFT				10
+#define OMAP24XX_EN_GPT8				(1 << 10)
+#define OMAP24XX_EN_GPT7_SHIFT				9
+#define OMAP24XX_EN_GPT7				(1 << 9)
+#define OMAP24XX_EN_GPT6_SHIFT				8
+#define OMAP24XX_EN_GPT6				(1 << 8)
+#define OMAP24XX_EN_GPT5_SHIFT				7
+#define OMAP24XX_EN_GPT5				(1 << 7)
+#define OMAP24XX_EN_GPT4_SHIFT				6
+#define OMAP24XX_EN_GPT4				(1 << 6)
+#define OMAP24XX_EN_GPT3_SHIFT				5
+#define OMAP24XX_EN_GPT3				(1 << 5)
+#define OMAP24XX_EN_GPT2_SHIFT				4
+#define OMAP24XX_EN_GPT2				(1 << 4)
+#define OMAP2420_EN_VLYNQ_SHIFT				3
+#define OMAP2420_EN_VLYNQ				(1 << 3)
+
+/* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
+#define OMAP2430_EN_GPIO5_SHIFT				10
+#define OMAP2430_EN_GPIO5				(1 << 10)
+#define OMAP2430_EN_MCSPI3_SHIFT			9
+#define OMAP2430_EN_MCSPI3				(1 << 9)
+#define OMAP2430_EN_MMCHS2_SHIFT			8
+#define OMAP2430_EN_MMCHS2				(1 << 8)
+#define OMAP2430_EN_MMCHS1_SHIFT			7
+#define OMAP2430_EN_MMCHS1				(1 << 7)
+#define OMAP24XX_EN_UART3_SHIFT				2
+#define OMAP24XX_EN_UART3				(1 << 2)
+#define OMAP24XX_EN_USB_SHIFT				0
+#define OMAP24XX_EN_USB					(1 << 0)
+
+/* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
+#define OMAP2430_EN_MDM_INTC_SHIFT			11
+#define OMAP2430_EN_MDM_INTC				(1 << 11)
+#define OMAP2430_EN_USBHS_SHIFT				6
+#define OMAP2430_EN_USBHS				(1 << 6)
+
+/* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
+#define OMAP2420_ST_MMC					(1 << 26)
+#define OMAP24XX_ST_UART2				(1 << 22)
+#define OMAP24XX_ST_UART1				(1 << 21)
+#define OMAP24XX_ST_MCSPI2				(1 << 18)
+#define OMAP24XX_ST_MCSPI1				(1 << 17)
+#define OMAP24XX_ST_GPT12				(1 << 14)
+#define OMAP24XX_ST_GPT11				(1 << 13)
+#define OMAP24XX_ST_GPT10				(1 << 12)
+#define OMAP24XX_ST_GPT9				(1 << 11)
+#define OMAP24XX_ST_GPT8				(1 << 10)
+#define OMAP24XX_ST_GPT7				(1 << 9)
+#define OMAP24XX_ST_GPT6				(1 << 8)
+#define OMAP24XX_ST_GPT5				(1 << 7)
+#define OMAP24XX_ST_GPT4				(1 << 6)
+#define OMAP24XX_ST_GPT3				(1 << 5)
+#define OMAP24XX_ST_GPT2				(1 << 4)
+#define OMAP2420_ST_VLYNQ				(1 << 3)
+
+/* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */
+#define OMAP2430_ST_MDM_INTC				(1 << 11)
+#define OMAP2430_ST_GPIO5				(1 << 10)
+#define OMAP2430_ST_MCSPI3				(1 << 9)
+#define OMAP2430_ST_MMCHS2				(1 << 8)
+#define OMAP2430_ST_MMCHS1				(1 << 7)
+#define OMAP2430_ST_USBHS				(1 << 6)
+#define OMAP24XX_ST_UART3				(1 << 2)
+#define OMAP24XX_ST_USB					(1 << 0)
+
+/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
+#define OMAP24XX_EN_GPIOS_SHIFT				2
+#define OMAP24XX_EN_GPIOS				(1 << 2)
+#define OMAP24XX_EN_GPT1_SHIFT				0
+#define OMAP24XX_EN_GPT1				(1 << 0)
+
+/* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
+#define OMAP24XX_ST_GPIOS				(1 << 2)
+#define OMAP24XX_ST_GPT1				(1 << 0)
+
+/* CM_IDLEST_MDM and PM_WKST_MDM shared bits */
+#define OMAP2430_ST_MDM					(1 << 0)
+
+
 #endif
 

new file mode 100644
index 0000000..659e089
@@ -0,0 +1,94 @@
+#ifndef __ARCH_ASM_MACH_OMAP2_CM_H
+#define __ARCH_ASM_MACH_OMAP2_CM_H
+
+/*
+ * OMAP2 Clock Management (CM) register definitions
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <asm/io.h>
+#include "prcm_common.h"
+
+
+#define OMAP_CM_REGADDR(module, reg)	 (void __iomem *)IO_ADDRESS(CM_BASE + module + reg)
+
+/*
+ * Architecture-specific global CM registers
+ * Use cm_{read,write}_reg() with these registers.
+ */
+
+/* None currently */
+
+/* Clock management global register get/set */
+
+static void __attribute__((unused)) cm_write_reg(u32 val, void __iomem *addr)
+{
+	pr_debug("cm_write_reg: writing 0x%0x to 0x%0x\n", val, (u32)addr);
+
+	__raw_writel(val, addr);
+}
+
+static u32 __attribute__((unused)) cm_read_reg(void __iomem *addr)
+{
+	return __raw_readl(addr);
+}
+
+
+/*
+ * Module specific CM registers from CM_BASE + domain offset
+ * Use cm_{read,write}_mod_reg() with these registers.
+ */
+
+/* Common between 24xx and 34xx */
+
+#define CM_FCLKEN1					0x0000
+#define CM_CLKEN					CM_FCLKEN1
+#define CM_ICLKEN1					0x0010
+#define CM_ICLKEN					CM_ICLKEN1
+#define CM_ICLKEN2					0x0014
+#define CM_IDLEST1					0x0020
+#define CM_IDLEST                                       CM_IDLEST1
+#define CM_IDLEST2					0x0024
+#define CM_AUTOIDLE					0x0030
+#define CM_AUTOIDLE1					0x0030
+#define CM_AUTOIDLE2					0x0034
+#define CM_CLKSEL					0x0040
+#define CM_CLKSEL1					CM_CLKSEL
+#define CM_CLKSEL2					0x0044
+#define CM_CLKSTCTRL					0x0048
+
+
+/* Architecture-specific registers */
+
+#define OMAP24XX_CM_FCLKEN				CM_FCLKEN1
+#define OMAP24XX_CM_FCLKEN2				0x0004
+#define OMAP24XX_CM_ICLKEN4				0x001c
+#define OMAP24XX_CM_AUTOIDLE3				0x0038
+#define OMAP24XX_CM_AUTOIDLE4				0x003c
+
+#define OMAP2430_CM_ICLKEN3				0x0018
+#define OMAP2430_CM_IDLEST3				0x0028
+
+
+/* Clock management domain register get/set */
+
+static void __attribute__((unused)) cm_write_mod_reg(u32 val, s16 module, s16 idx)
+{
+	cm_write_reg(val, OMAP_CM_REGADDR(module, idx));
+}
+
+static u32 __attribute__((unused)) cm_read_mod_reg(s16 module, s16 idx)
+{
+	return cm_read_reg(OMAP_CM_REGADDR(module, idx));
+}
+
+#endif

index 659e089..48999ce 100644
@@ -91,4 +91,19 @@ static u32 __attribute__((unused)) cm_read_mod_reg(s16 module, s16 idx)
 	return cm_read_reg(OMAP_CM_REGADDR(module, idx));
 }
 
+/* CM register bits shared between 24XX and 3430 */
+
+/* CM_CLKSEL_GFX */
+#define OMAP_CLKSEL_GFX_SHIFT				0
+#define OMAP_CLKSEL_GFX_MASK				(0x7 << 0)
+
+/* CM_ICLKEN_GFX */
+#define OMAP_EN_GFX_SHIFT				0
+#define OMAP_EN_GFX					(1 << 0)
+
+/* CM_IDLEST_GFX */
+#define OMAP_ST_GFX					(1 << 0)
+
+
+
 #endif

new file mode 100644
index 0000000..70fb9de
@@ -0,0 +1,119 @@
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM_H
+#define __ARCH_ARM_MACH_OMAP2_PRM_H
+
+/*
+ * OMAP2 Power/Reset Management (PRM) register definitions
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <asm/io.h>
+#include "prcm_common.h"
+
+
+#define OMAP_PRM_REGADDR(module, reg)	(void __iomem *)IO_ADDRESS(PRM_BASE + module + reg)
+
+/*
+ * Architecture-specific global PRM registers
+ * Use prm_{read,write}_reg() with these registers.
+ *
+ * With a few exceptions, these are the register names beginning with
+ * PRCM_* on 24xx, and PRM_* on 34xx.  (The exceptions are the
+ * IRQSTATUS and IRQENABLE bits.)
+ *
+ */
+
+#define OMAP24XX_PRCM_REVISION		OMAP_PRM_REGADDR(OCP_MOD, 0x0004)
+#define OMAP24XX_PRCM_SYSCONFIG		OMAP_PRM_REGADDR(OCP_MOD, 0x0014)
+
+#define OMAP24XX_PRCM_IRQSTATUS_MPU	OMAP_PRM_REGADDR(OCP_MOD, 0x0018)
+#define OMAP24XX_PRCM_IRQENABLE_MPU	OMAP_PRM_REGADDR(OCP_MOD, 0x001c)
+
+#define OMAP24XX_PRCM_VOLTCTRL		OMAP_PRM_REGADDR(OCP_MOD, 0x0050)
+#define OMAP24XX_PRCM_VOLTST		OMAP_PRM_REGADDR(OCP_MOD, 0x0054)
+#define OMAP24XX_PRCM_CLKSRC_CTRL	OMAP_PRM_REGADDR(OCP_MOD, 0x0060)
+#define OMAP24XX_PRCM_CLKOUT_CTRL	OMAP_PRM_REGADDR(OCP_MOD, 0x0070)
+#define OMAP24XX_PRCM_CLKEMUL_CTRL	OMAP_PRM_REGADDR(OCP_MOD, 0x0078)
+#define OMAP24XX_PRCM_CLKCFG_CTRL	OMAP_PRM_REGADDR(OCP_MOD, 0x0080)
+#define OMAP24XX_PRCM_CLKCFG_STATUS	OMAP_PRM_REGADDR(OCP_MOD, 0x0084)
+#define OMAP24XX_PRCM_VOLTSETUP		OMAP_PRM_REGADDR(OCP_MOD, 0x0090)
+#define OMAP24XX_PRCM_CLKSSETUP		OMAP_PRM_REGADDR(OCP_MOD, 0x0094)
+#define OMAP24XX_PRCM_POLCTRL		OMAP_PRM_REGADDR(OCP_MOD, 0x0098)
+
+
+/* Power/reset management global register get/set */
+
+static void __attribute__((unused)) prm_write_reg(u32 val, void __iomem *addr)
+{
+	pr_debug("prm_write_reg: writing 0x%0x to 0x%0x\n", val, (u32)addr);
+
+	__raw_writel(val, addr);
+}
+
+static u32 __attribute__((unused)) prm_read_reg(void __iomem *addr)
+{
+	return __raw_readl(addr);
+}
+
+
+/*
+ * Module specific PRM registers from PRM_BASE + domain offset
+ *
+ * Use prm_{read,write}_mod_reg() with these registers.
+ *
+ * With a few exceptions, these are the register names beginning with
+ * {PM,RM}_* on both architectures.  (The exceptions are the IRQSTATUS
+ * and IRQENABLE bits.)
+ *
+ */
+
+/* Registers appearing on both 24xx and 34xx */
+
+#define RM_RSTCTRL					0x0050
+#define RM_RSTTIME					0x0054
+#define RM_RSTST					0x0058
+
+#define PM_WKEN1					0x00a0
+#define PM_WKEN						PM_WKEN1
+#define PM_WKST						0x00b0
+#define PM_WKST1					PM_WKST
+#define PM_WKDEP					0x00c8
+#define PM_EVGENCTRL					0x00d4
+#define PM_EVGENONTIM					0x00d8
+#define PM_EVGENOFFTIM					0x00dc
+#define PM_PWSTCTRL					0x00e0
+#define PM_PWSTST					0x00e4
+
+
+/* Architecture-specific registers */
+
+#define OMAP24XX_PM_WKEN2				0x00a4
+#define OMAP24XX_PM_WKST2				0x00b4
+
+#define OMAP24XX_PRCM_IRQSTATUS_DSP			0x00f0	/* IVA mod */
+#define OMAP24XX_PRCM_IRQENABLE_DSP			0x00f4	/* IVA mod */
+#define OMAP24XX_PRCM_IRQSTATUS_IVA			0x00f8
+#define OMAP24XX_PRCM_IRQENABLE_IVA			0x00fc
+
+
+/* Power/reset management domain register get/set */
+
+static void __attribute__((unused)) prm_write_mod_reg(u32 val, s16 module, s16 idx)
+{
+	prm_write_reg(val, OMAP_PRM_REGADDR(module, idx));
+}
+
+static u32 __attribute__((unused)) prm_read_mod_reg(s16 module, s16 idx)
+{
+	return prm_read_reg(OMAP_PRM_REGADDR(module, idx));
+}
+
+#endif

index 70fb9de..7e1738c 100644
@@ -116,4 +116,155 @@ static u32 __attribute__((unused)) prm_read_mod_reg(s16 module, s16 idx)
 	return prm_read_reg(OMAP_PRM_REGADDR(module, idx));
 }
 
+
+/*
+ * Bits common to specific registers
+ *
+ * The 3430 register and bit names are generally used,
+ * since they tend to make more sense
+ */
+
+/* PM_EVGENONTIM_MPU */
+/* Named PM_EVEGENONTIM_MPU on the 24XX */
+#define OMAP_ONTIMEVAL_SHIFT				0
+#define OMAP_ONTIMEVAL_MASK				(0xffffffff << 0)
+
+/* PM_EVGENOFFTIM_MPU */
+/* Named PM_EVEGENOFFTIM_MPU on the 24XX */
+#define OMAP_OFFTIMEVAL_SHIFT				0
+#define OMAP_OFFTIMEVAL_MASK				(0xffffffff << 0)
+
+/* PRM_CLKSETUP and PRCM_VOLTSETUP */
+/* Named PRCM_CLKSSETUP on the 24XX */
+#define OMAP_SETUP_TIME_SHIFT				0
+#define OMAP_SETUP_TIME_MASK				(0xffff << 0)
+
+/* PRM_CLKSRC_CTRL */
+/* Named PRCM_CLKSRC_CTRL on the 24XX */
+#define OMAP_SYSCLKDIV_SHIFT				6
+#define OMAP_SYSCLKDIV_MASK				(0x3 << 6)
+#define OMAP_AUTOEXTCLKMODE_SHIFT			3
+#define OMAP_AUTOEXTCLKMODE_MASK			(0x3 << 3)
+#define OMAP_SYSCLKSEL_SHIFT				0
+#define OMAP_SYSCLKSEL_MASK				(0x3 << 0)
+
+/* PM_EVGENCTRL_MPU */
+#define OMAP_OFFLOADMODE_SHIFT				3
+#define OMAP_OFFLOADMODE_MASK				(0x3 << 3)
+#define OMAP_ONLOADMODE_SHIFT				1
+#define OMAP_ONLOADMODE_MASK				(0x3 << 1)
+#define OMAP_ENABLE					(1 << 0)
+
+/* PRM_RSTTIME */
+/* Named RM_RSTTIME_WKUP on the 24xx */
+#define OMAP_RSTTIME2_SHIFT				8
+#define OMAP_RSTTIME2_MASK				(0x1f << 8)
+#define OMAP_RSTTIME1_SHIFT				0
+#define OMAP_RSTTIME1_MASK				(0xff << 0)
+
+
+/* PRM_RSTCTRL */
+/* Named RM_RSTCTRL_WKUP on the 24xx */
+/* 2420 calls RST_DPLL3 'RST_DPLL' */
+#define OMAP_RST_DPLL3					(1 << 2)
+#define OMAP_RST_GS					(1 << 1)
+
+
+/*
+ * Bits common to module-shared registers
+ *
+ * Not all registers of a particular type support all of these bits -
+ * check TRM if you are unsure
+ */
+
+/*
+ * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP
+ *
+ * 2430: PM_PWSTST_MDM
+ *
+ * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
+ *	 PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
+ *	 PM_PWSTST_NEON
+ */
+#define OMAP_INTRANSITION				(1 << 20)
+
+
+/*
+ * 24XX: PM_PWSTST_GFX, PM_PWSTST_DSP
+ *
+ * 2430: PM_PWSTST_MDM
+ *
+ * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
+ *	 PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
+ *	 PM_PWSTST_NEON
+ */
+#define OMAP_POWERSTATEST_SHIFT				0
+#define OMAP_POWERSTATEST_MASK				(0x3 << 0)
+
+/*
+ * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is
+ *	 called 'COREWKUP_RST'
+ *
+ * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS,
+ *	 RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON
+ */
+#define OMAP_COREDOMAINWKUP_RST				(1 << 3)
+
+/*
+ * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP
+ *
+ * 2430: RM_RSTST_MDM
+ *
+ * 3430: RM_RSTST_CORE, RM_RSTST_EMU
+ */
+#define OMAP_DOMAINWKUP_RST				(1 << 2)
+
+/*
+ * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP
+ *	 On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'.
+ *
+ * 2430: RM_RSTST_MDM
+ *
+ * 3430: RM_RSTST_CORE, RM_RSTST_EMU
+ */
+#define OMAP_GLOBALWARM_RST				(1 << 1)
+#define OMAP_GLOBALCOLD_RST				(1 << 0)
+
+/*
+ * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP
+ *	 2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP"
+ *
+ * 2430: PM_WKDEP_MDM
+ *
+ * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM,
+ *	 PM_WKDEP_PER
+ */
+#define OMAP_EN_WKUP					(1 << 4)
+
+/*
+ * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
+ *	 PM_PWSTCTRL_DSP
+ *
+ * 2430: PM_PWSTCTRL_MDM
+ *
+ * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
+ *	 PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
+ *	 PM_PWSTCTRL_NEON
+ */
+#define OMAP_LOGICRETSTATE				(1 << 2)
+
+/*
+ * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
+ *       PM_PWSTCTRL_DSP, PM_PWSTST_MPU
+ *
+ * 2430: PM_PWSTCTRL_MDM shared bits
+ *
+ * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE,
+ *	 PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
+ *	 PM_PWSTCTRL_NEON shared bits
+ */
+#define OMAP_POWERSTATE_SHIFT				0
+#define OMAP_POWERSTATE_MASK				(0x3 << 0)
+
+
 #endif

new file mode 100644
index 0000000..efd7c17
@@ -0,0 +1,398 @@
+#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
+
+/*
+ * OMAP24XX Clock Management register bits
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "cm.h"
+
+/* Bits shared between registers */
+
+/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
+#define OMAP24XX_EN_CAM_SHIFT				31
+#define OMAP24XX_EN_CAM					(1 << 31)
+#define OMAP24XX_EN_WDT4_SHIFT				29
+#define OMAP24XX_EN_WDT4				(1 << 29)
+#define OMAP2420_EN_WDT3_SHIFT				28
+#define OMAP2420_EN_WDT3				(1 << 28)
+#define OMAP24XX_EN_MSPRO_SHIFT				27
+#define OMAP24XX_EN_MSPRO				(1 << 27)
+#define OMAP24XX_EN_FAC_SHIFT				25
+#define OMAP24XX_EN_FAC					(1 << 25)
+#define OMAP2420_EN_EAC_SHIFT				24
+#define OMAP2420_EN_EAC					(1 << 24)
+#define OMAP24XX_EN_HDQ_SHIFT				23
+#define OMAP24XX_EN_HDQ					(1 << 23)
+#define OMAP2420_EN_I2C2_SHIFT				20
+#define OMAP2420_EN_I2C2				(1 << 20)
+#define OMAP2420_EN_I2C1_SHIFT				19
+#define OMAP2420_EN_I2C1				(1 << 19)
+
+/* CM_FCLKEN2_CORE and CM_ICLKEN2_CORE shared bits */
+#define OMAP2430_EN_MCBSP5_SHIFT			5
+#define OMAP2430_EN_MCBSP5				(1 << 5)
+#define OMAP2430_EN_MCBSP4_SHIFT			4
+#define OMAP2430_EN_MCBSP4				(1 << 4)
+#define OMAP2430_EN_MCBSP3_SHIFT			3
+#define OMAP2430_EN_MCBSP3				(1 << 3)
+#define OMAP24XX_EN_SSI_SHIFT				1
+#define OMAP24XX_EN_SSI					(1 << 1)
+
+/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
+#define OMAP24XX_EN_MPU_WDT_SHIFT			3
+#define OMAP24XX_EN_MPU_WDT				(1 << 3)
+
+/* Bits specific to each register */
+
+/* CM_IDLEST_MPU */
+/* 2430 only */
+#define OMAP2430_ST_MPU					(1 << 0)
+
+/* CM_CLKSEL_MPU */
+#define OMAP24XX_CLKSEL_MPU_SHIFT			0
+#define OMAP24XX_CLKSEL_MPU_MASK			(0x1f << 0)
+
+/* CM_CLKSTCTRL_MPU */
+#define OMAP24XX_AUTOSTATE_MPU				(1 << 0)
+
+/* CM_FCLKEN1_CORE specific bits*/
+#define OMAP24XX_EN_TV_SHIFT				2
+#define OMAP24XX_EN_TV					(1 << 2)
+#define OMAP24XX_EN_DSS2_SHIFT				1
+#define OMAP24XX_EN_DSS2				(1 << 1)
+#define OMAP24XX_EN_DSS1_SHIFT				0
+#define OMAP24XX_EN_DSS1				(1 << 0)
+
+/* CM_FCLKEN2_CORE specific bits */
+#define OMAP2430_EN_I2CHS2_SHIFT			20
+#define OMAP2430_EN_I2CHS2				(1 << 20)
+#define OMAP2430_EN_I2CHS1_SHIFT			19
+#define OMAP2430_EN_I2CHS1				(1 << 19)
+#define OMAP2430_EN_MMCHSDB2_SHIFT			17
+#define OMAP2430_EN_MMCHSDB2				(1 << 17)
+#define OMAP2430_EN_MMCHSDB1_SHIFT			16
+#define OMAP2430_EN_MMCHSDB1				(1 << 16)
+
+/* CM_ICLKEN1_CORE specific bits */
+#define OMAP24XX_EN_MAILBOXES_SHIFT			30
+#define OMAP24XX_EN_MAILBOXES				(1 << 30)
+#define OMAP24XX_EN_DSS_SHIFT				0
+#define OMAP24XX_EN_DSS					(1 << 0)
+
+/* CM_ICLKEN2_CORE specific bits */
+
+/* CM_ICLKEN3_CORE */
+/* 2430 only */
+#define OMAP2430_EN_SDRC_SHIFT				2
+#define OMAP2430_EN_SDRC				(1 << 2)
+
+/* CM_ICLKEN4_CORE */
+#define OMAP24XX_EN_PKA_SHIFT				4
+#define OMAP24XX_EN_PKA					(1 << 4)
+#define OMAP24XX_EN_AES_SHIFT				3
+#define OMAP24XX_EN_AES					(1 << 3)
+#define OMAP24XX_EN_RNG_SHIFT				2
+#define OMAP24XX_EN_RNG					(1 << 2)
+#define OMAP24XX_EN_SHA_SHIFT				1
+#define OMAP24XX_EN_SHA					(1 << 1)
+#define OMAP24XX_EN_DES_SHIFT				0
+#define OMAP24XX_EN_DES					(1 << 0)
+
+/* CM_IDLEST1_CORE specific bits */
+#define OMAP24XX_ST_MAILBOXES				(1 << 30)
+#define OMAP24XX_ST_WDT4				(1 << 29)
+#define OMAP2420_ST_WDT3				(1 << 28)
+#define OMAP24XX_ST_MSPRO				(1 << 27)
+#define OMAP24XX_ST_FAC					(1 << 25)
+#define OMAP2420_ST_EAC					(1 << 24)
+#define OMAP24XX_ST_HDQ					(1 << 23)
+#define OMAP24XX_ST_I2C2				(1 << 20)
+#define OMAP24XX_ST_I2C1				(1 << 19)
+#define OMAP24XX_ST_MCBSP2				(1 << 16)
+#define OMAP24XX_ST_MCBSP1				(1 << 15)
+#define OMAP24XX_ST_DSS					(1 << 0)
+
+/* CM_IDLEST2_CORE */
+#define OMAP2430_ST_MCBSP5				(1 << 5)
+#define OMAP2430_ST_MCBSP4				(1 << 4)
+#define OMAP2430_ST_MCBSP3				(1 << 3)
+#define OMAP24XX_ST_SSI					(1 << 1)
+
+/* CM_IDLEST3_CORE */
+/* 2430 only */
+#define OMAP2430_ST_SDRC				(1 << 2)
+
+/* CM_IDLEST4_CORE */
+#define OMAP24XX_ST_PKA					(1 << 4)
+#define OMAP24XX_ST_AES					(1 << 3)
+#define OMAP24XX_ST_RNG					(1 << 2)
+#define OMAP24XX_ST_SHA					(1 << 1)
+#define OMAP24XX_ST_DES					(1 << 0)
+
+/* CM_AUTOIDLE1_CORE */
+#define OMAP24XX_AUTO_CAM				(1 << 31)
+#define OMAP24XX_AUTO_MAILBOXES				(1 << 30)
+#define OMAP24XX_AUTO_WDT4				(1 << 29)
+#define OMAP2420_AUTO_WDT3				(1 << 28)
+#define OMAP24XX_AUTO_MSPRO				(1 << 27)
+#define OMAP2420_AUTO_MMC				(1 << 26)
+#define OMAP24XX_AUTO_FAC				(1 << 25)
+#define OMAP2420_AUTO_EAC				(1 << 24)
+#define OMAP24XX_AUTO_HDQ				(1 << 23)
+#define OMAP24XX_AUTO_UART2				(1 << 22)
+#define OMAP24XX_AUTO_UART1				(1 << 21)
+#define OMAP24XX_AUTO_I2C2				(1 << 20)
+#define OMAP24XX_AUTO_I2C1				(1 << 19)
+#define OMAP24XX_AUTO_MCSPI2				(1 << 18)
+#define OMAP24XX_AUTO_MCSPI1				(1 << 17)
+#define OMAP24XX_AUTO_MCBSP2				(1 << 16)
+#define OMAP24XX_AUTO_MCBSP1				(1 << 15)
+#define OMAP24XX_AUTO_GPT12				(1 << 14)
+#define OMAP24XX_AUTO_GPT11				(1 << 13)
+#define OMAP24XX_AUTO_GPT10				(1 << 12)
+#define OMAP24XX_AUTO_GPT9				(1 << 11)
+#define OMAP24XX_AUTO_GPT8				(1 << 10)
+#define OMAP24XX_AUTO_GPT7				(1 << 9)
+#define OMAP24XX_AUTO_GPT6				(1 << 8)
+#define OMAP24XX_AUTO_GPT5				(1 << 7)
+#define OMAP24XX_AUTO_GPT4				(1 << 6)
+#define OMAP24XX_AUTO_GPT3				(1 << 5)
+#define OMAP24XX_AUTO_GPT2				(1 << 4)
+#define OMAP2420_AUTO_VLYNQ				(1 << 3)
+#define OMAP24XX_AUTO_DSS				(1 << 0)
+
+/* CM_AUTOIDLE2_CORE */
+#define OMAP2430_AUTO_MDM_INTC				(1 << 11)
+#define OMAP2430_AUTO_GPIO5				(1 << 10)
+#define OMAP2430_AUTO_MCSPI3				(1 << 9)
+#define OMAP2430_AUTO_MMCHS2				(1 << 8)
+#define OMAP2430_AUTO_MMCHS1				(1 << 7)
+#define OMAP2430_AUTO_USBHS				(1 << 6)
+#define OMAP2430_AUTO_MCBSP5				(1 << 5)
+#define OMAP2430_AUTO_MCBSP4				(1 << 4)
+#define OMAP2430_AUTO_MCBSP3				(1 << 3)
+#define OMAP24XX_AUTO_UART3				(1 << 2)
+#define OMAP24XX_AUTO_SSI				(1 << 1)
+#define OMAP24XX_AUTO_USB				(1 << 0)
+
+/* CM_AUTOIDLE3_CORE */
+#define OMAP24XX_AUTO_SDRC				(1 << 2)
+#define OMAP24XX_AUTO_GPMC				(1 << 1)
+#define OMAP24XX_AUTO_SDMA				(1 << 0)
+
+/* CM_AUTOIDLE4_CORE */
+#define OMAP24XX_AUTO_PKA				(1 << 4)
+#define OMAP24XX_AUTO_AES				(1 << 3)
+#define OMAP24XX_AUTO_RNG				(1 << 2)
+#define OMAP24XX_AUTO_SHA				(1 << 1)
+#define OMAP24XX_AUTO_DES				(1 << 0)
+
+/* CM_CLKSEL1_CORE */
+#define OMAP24XX_CLKSEL_USB_SHIFT			25
+#define OMAP24XX_CLKSEL_USB_MASK			(0x7 << 25)
+#define OMAP24XX_CLKSEL_SSI_SHIFT			20
+#define OMAP24XX_CLKSEL_SSI_MASK			(0x1f << 20)
+#define OMAP2420_CLKSEL_VLYNQ_SHIFT			15
+#define OMAP2420_CLKSEL_VLYNQ_MASK			(0x1f << 15)
+#define OMAP24XX_CLKSEL_DSS2_SHIFT			13
+#define OMAP24XX_CLKSEL_DSS2_MASK			(0x1 << 13)
+#define OMAP24XX_CLKSEL_DSS1_SHIFT			8
+#define OMAP24XX_CLKSEL_DSS1_MASK			(0x1f << 8)
+#define OMAP24XX_CLKSEL_L4_SHIFT			5
+#define OMAP24XX_CLKSEL_L4_MASK				(0x3 << 5)
+#define OMAP24XX_CLKSEL_L3_SHIFT			0
+#define OMAP24XX_CLKSEL_L3_MASK				(0x1f << 0)
+
+/* CM_CLKSEL2_CORE */
+#define OMAP24XX_CLKSEL_GPT12_SHIFT			22
+#define OMAP24XX_CLKSEL_GPT12_MASK			(0x3 << 22)
+#define OMAP24XX_CLKSEL_GPT11_SHIFT			20
+#define OMAP24XX_CLKSEL_GPT11_MASK			(0x3 << 20)
+#define OMAP24XX_CLKSEL_GPT10_SHIFT			18
+#define OMAP24XX_CLKSEL_GPT10_MASK			(0x3 << 18)
+#define OMAP24XX_CLKSEL_GPT9_SHIFT			16
+#define OMAP24XX_CLKSEL_GPT9_MASK			(0x3 << 16)
+#define OMAP24XX_CLKSEL_GPT8_SHIFT			14
+#define OMAP24XX_CLKSEL_GPT8_MASK			(0x3 << 14)
+#define OMAP24XX_CLKSEL_GPT7_SHIFT			12
+#define OMAP24XX_CLKSEL_GPT7_MASK			(0x3 << 12)
+#define OMAP24XX_CLKSEL_GPT6_SHIFT			10
+#define OMAP24XX_CLKSEL_GPT6_MASK			(0x3 << 10)
+#define OMAP24XX_CLKSEL_GPT5_SHIFT			8
+#define OMAP24XX_CLKSEL_GPT5_MASK			(0x3 << 8)
+#define OMAP24XX_CLKSEL_GPT4_SHIFT			6
+#define OMAP24XX_CLKSEL_GPT4_MASK			(0x3 << 6)
+#define OMAP24XX_CLKSEL_GPT3_SHIFT			4
+#define OMAP24XX_CLKSEL_GPT3_MASK			(0x3 << 4)
+#define OMAP24XX_CLKSEL_GPT2_SHIFT			2
+#define OMAP24XX_CLKSEL_GPT2_MASK			(0x3 << 2)
+
+/* CM_CLKSTCTRL_CORE */
+#define OMAP24XX_AUTOSTATE_DSS				(1 << 2)
+#define OMAP24XX_AUTOSTATE_L4				(1 << 1)
+#define OMAP24XX_AUTOSTATE_L3				(1 << 0)
+
+/* CM_FCLKEN_GFX */
+#define OMAP24XX_EN_3D_SHIFT				2
+#define OMAP24XX_EN_3D					(1 << 2)
+#define OMAP24XX_EN_2D_SHIFT				1
+#define OMAP24XX_EN_2D					(1 << 1)
+
+/* CM_ICLKEN_GFX specific bits */
+
+/* CM_IDLEST_GFX specific bits */
+
+/* CM_CLKSEL_GFX specific bits */
+
+/* CM_CLKSTCTRL_GFX */
+#define OMAP24XX_AUTOSTATE_GFX				(1 << 0)
+
+/* CM_FCLKEN_WKUP specific bits */
+
+/* CM_ICLKEN_WKUP specific bits */
+#define OMAP2430_EN_ICR_SHIFT				6
+#define OMAP2430_EN_ICR					(1 << 6)
+#define OMAP24XX_EN_OMAPCTRL_SHIFT			5
+#define OMAP24XX_EN_OMAPCTRL				(1 << 5)
+#define OMAP24XX_EN_WDT1_SHIFT				4
+#define OMAP24XX_EN_WDT1				(1 << 4)
+#define OMAP24XX_EN_32KSYNC_SHIFT			1
+#define OMAP24XX_EN_32KSYNC				(1 << 1)
+
+/* CM_IDLEST_WKUP specific bits */
+#define OMAP2430_ST_ICR					(1 << 6)
+#define OMAP24XX_ST_OMAPCTRL				(1 << 5)
+#define OMAP24XX_ST_WDT1				(1 << 4)
+#define OMAP24XX_ST_MPU_WDT				(1 << 3)
+#define OMAP24XX_ST_32KSYNC				(1 << 1)
+
+/* CM_AUTOIDLE_WKUP */
+#define OMAP24XX_AUTO_OMAPCTRL				(1 << 5)
+#define OMAP24XX_AUTO_WDT1				(1 << 4)
+#define OMAP24XX_AUTO_MPU_WDT				(1 << 3)
+#define OMAP24XX_AUTO_GPIOS				(1 << 2)
+#define OMAP24XX_AUTO_32KSYNC				(1 << 1)
+#define OMAP24XX_AUTO_GPT1				(1 << 0)
+
+/* CM_CLKSEL_WKUP */
+#define OMAP24XX_CLKSEL_GPT1_SHIFT			0
+#define OMAP24XX_CLKSEL_GPT1_MASK			(0x3 << 0)
+
+/* CM_CLKEN_PLL */
+#define OMAP24XX_EN_54M_PLL_SHIFT			6
+#define OMAP24XX_EN_54M_PLL_MASK			(0x3 << 6)
+#define OMAP24XX_EN_96M_PLL_SHIFT			2
+#define OMAP24XX_EN_96M_PLL_MASK			(0x3 << 2)
+#define OMAP24XX_EN_DPLL_SHIFT				0
+#define OMAP24XX_EN_DPLL_MASK				(0x3 << 0)
+
+/* CM_IDLEST_CKGEN */
+#define OMAP24XX_ST_54M_APLL				(1 << 9)
+#define OMAP24XX_ST_96M_APLL				(1 << 8)
+#define OMAP24XX_ST_54M_CLK				(1 << 6)
+#define OMAP24XX_ST_12M_CLK				(1 << 5)
+#define OMAP24XX_ST_48M_CLK				(1 << 4)
+#define OMAP24XX_ST_96M_CLK				(1 << 2)
+#define OMAP24XX_ST_CORE_CLK_SHIFT			0
+#define OMAP24XX_ST_CORE_CLK_MASK			(0x3 << 0)
+
+/* CM_AUTOIDLE_PLL */
+#define OMAP24XX_AUTO_54M_SHIFT				6
+#define OMAP24XX_AUTO_54M_MASK				(0x3 << 6)
+#define OMAP24XX_AUTO_96M_SHIFT				2
+#define OMAP24XX_AUTO_96M_MASK				(0x3 << 2)
+#define OMAP24XX_AUTO_DPLL_SHIFT			0
+#define OMAP24XX_AUTO_DPLL_MASK				(0x3 << 0)
+
+/* CM_CLKSEL1_PLL */
+#define OMAP2430_MAXDPLLFASTLOCK_SHIFT			28
+#define OMAP2430_MAXDPLLFASTLOCK_MASK			(0x7 << 28)
+#define OMAP24XX_APLLS_CLKIN_SHIFT			23
+#define OMAP24XX_APLLS_CLKIN_MASK			(0x7 << 23)
+#define OMAP24XX_DPLL_MULT_SHIFT			12
+#define OMAP24XX_DPLL_MULT_MASK				(0x3ff << 12)
+#define OMAP24XX_DPLL_DIV_SHIFT				8
+#define OMAP24XX_DPLL_DIV_MASK				(0xf << 8)
+#define OMAP24XX_54M_SOURCE				(1 << 5)
+#define OMAP2430_96M_SOURCE				(1 << 4)
+#define OMAP24XX_48M_SOURCE				(1 << 3)
+#define OMAP2430_ALTCLK_SOURCE_SHIFT			0
+#define OMAP2430_ALTCLK_SOURCE_MASK			(0x7 << 0)
+
+/* CM_CLKSEL2_PLL */
+#define OMAP24XX_CORE_CLK_SRC_SHIFT			0
+#define OMAP24XX_CORE_CLK_SRC_MASK			(0x3 << 0)
+
+/* CM_FCLKEN_DSP */
+#define OMAP2420_EN_IVA_COP_SHIFT			10
+#define OMAP2420_EN_IVA_COP				(1 << 10)
+#define OMAP2420_EN_IVA_MPU_SHIFT			8
+#define OMAP2420_EN_IVA_MPU				(1 << 8)
+#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT		0
+#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP			(1 << 0)
+
+/* CM_ICLKEN_DSP */
+#define OMAP2420_EN_DSP_IPI_SHIFT			1
+#define OMAP2420_EN_DSP_IPI				(1 << 1)
+
+/* CM_IDLEST_DSP */
+#define OMAP2420_ST_IVA					(1 << 8)
+#define OMAP2420_ST_IPI					(1 << 1)
+#define OMAP24XX_ST_DSP					(1 << 0)
+
+/* CM_AUTOIDLE_DSP */
+#define OMAP2420_AUTO_DSP_IPI				(1 << 1)
+
+/* CM_CLKSEL_DSP */
+#define OMAP2420_SYNC_IVA				(1 << 13)
+#define OMAP2420_CLKSEL_IVA_SHIFT			8
+#define OMAP2420_CLKSEL_IVA_MASK			(0x1f << 8)
+#define OMAP24XX_SYNC_DSP				(1 << 7)
+#define OMAP24XX_CLKSEL_DSP_IF_SHIFT			5
+#define OMAP24XX_CLKSEL_DSP_IF_MASK			(0x3 << 5)
+#define OMAP24XX_CLKSEL_DSP_SHIFT			0
+#define OMAP24XX_CLKSEL_DSP_MASK			(0x1f << 0)
+
+/* CM_CLKSTCTRL_DSP */
+#define OMAP2420_AUTOSTATE_IVA				(1 << 8)
+#define OMAP24XX_AUTOSTATE_DSP				(1 << 0)
+
+/* CM_FCLKEN_MDM */
+/* 2430 only */
+#define OMAP2430_EN_OSC_SHIFT				1
+#define OMAP2430_EN_OSC					(1 << 1)
+
+/* CM_ICLKEN_MDM */
+/* 2430 only */
+#define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT		0
+#define OMAP2430_CM_ICLKEN_MDM_EN_MDM			(1 << 0)
+
+/* CM_IDLEST_MDM specific bits */
+/* 2430 only */
+
+/* CM_AUTOIDLE_MDM */
+/* 2430 only */
+#define OMAP2430_AUTO_OSC				(1 << 1)
+#define OMAP2430_AUTO_MDM				(1 << 0)
+
+/* CM_CLKSEL_MDM */
+/* 2430 only */
+#define OMAP2430_SYNC_MDM				(1 << 4)
+#define OMAP2430_CLKSEL_MDM_SHIFT			0
+#define OMAP2430_CLKSEL_MDM_MASK			(0xf << 0)
+
+/* CM_CLKSTCTRL_MDM */
+/* 2430 only */
+#define OMAP2430_AUTOSTATE_MDM				(1 << 0)
+
+#endif

new file mode 100644
index 0000000..c6d17a3
@@ -0,0 +1,279 @@
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_24XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_24XX_H
+
+/*
+ * OMAP24XX Power/Reset Management register bits
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "prm.h"
+
+/* Bits shared between registers */
+
+/* PRCM_IRQSTATUS_MPU, PM_IRQSTATUS_DSP, PRCM_IRQSTATUS_IVA shared bits */
+#define OMAP24XX_VOLTTRANS_ST				(1 << 2)
+#define OMAP24XX_WKUP2_ST				(1 << 1)
+#define OMAP24XX_WKUP1_ST				(1 << 0)
+
+/* PRCM_IRQENABLE_MPU, PM_IRQENABLE_DSP, PRCM_IRQENABLE_IVA shared bits */
+#define OMAP24XX_VOLTTRANS_EN				(1 << 2)
+#define OMAP24XX_WKUP2_EN				(1 << 1)
+#define OMAP24XX_WKUP1_EN				(1 << 0)
+
+/* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */
+#define OMAP24XX_EN_MPU					(1 << 1)
+#define OMAP24XX_EN_CORE				(1 << 0)
+
+/*
+ * PM_PWSTCTRL_MPU, PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM
+ * shared bits
+ */
+#define OMAP24XX_MEMONSTATE_SHIFT			10
+#define OMAP24XX_MEMONSTATE_MASK			(0x3 << 10)
+#define OMAP24XX_MEMRETSTATE				(1 << 3)
+
+/* PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM shared bits */
+#define OMAP24XX_FORCESTATE				(1 << 18)
+
+/*
+ * PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP,
+ * PM_PWSTST_MDM shared bits
+ */
+#define OMAP24XX_CLKACTIVITY				(1 << 19)
+
+/* PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_DSP shared bits */
+#define OMAP24XX_LASTSTATEENTERED_SHIFT			4
+#define OMAP24XX_LASTSTATEENTERED_MASK			(0x3 << 4)
+
+/* PM_PWSTST_MPU and PM_PWSTST_DSP shared bits */
+#define OMAP2430_MEMSTATEST_SHIFT			10
+#define OMAP2430_MEMSTATEST_MASK			(0x3 << 10)
+
+/* PM_PWSTST_GFX, PM_PWSTST_DSP, PM_PWSTST_MDM shared bits */
+#define OMAP24XX_POWERSTATEST_SHIFT			0
+#define OMAP24XX_POWERSTATEST_MASK			(0x3 << 0)
+
+
+/* Bits specific to each register */
+
+/* PRCM_REVISION */
+#define OMAP24XX_REV_SHIFT				0
+#define OMAP24XX_REV_MASK				(0xff << 0)
+
+/* PRCM_SYSCONFIG */
+#define OMAP24XX_AUTOIDLE				(1 << 0)
+
+/* PRCM_IRQSTATUS_MPU specific bits */
+#define OMAP2430_DPLL_RECAL_ST				(1 << 6)
+#define OMAP24XX_TRANSITION_ST				(1 << 5)
+#define OMAP24XX_EVGENOFF_ST				(1 << 4)
+#define OMAP24XX_EVGENON_ST				(1 << 3)
+
+/* PRCM_IRQENABLE_MPU specific bits */
+#define OMAP2430_DPLL_RECAL_EN				(1 << 6)
+#define OMAP24XX_TRANSITION_EN				(1 << 5)
+#define OMAP24XX_EVGENOFF_EN				(1 << 4)
+#define OMAP24XX_EVGENON_EN				(1 << 3)
+
+/* PRCM_VOLTCTRL */
+#define OMAP24XX_AUTO_EXTVOLT				(1 << 15)
+#define OMAP24XX_FORCE_EXTVOLT				(1 << 14)
+#define OMAP24XX_SETOFF_LEVEL_SHIFT			12
+#define OMAP24XX_SETOFF_LEVEL_MASK			(0x3 << 12)
+#define OMAP24XX_MEMRETCTRL				(1 << 8)
+#define OMAP24XX_SETRET_LEVEL_SHIFT			6
+#define OMAP24XX_SETRET_LEVEL_MASK			(0x3 << 6)
+#define OMAP24XX_VOLT_LEVEL_SHIFT			0
+#define OMAP24XX_VOLT_LEVEL_MASK			(0x3 << 0)
+
+/* PRCM_VOLTST */
+#define OMAP24XX_ST_VOLTLEVEL_SHIFT			0
+#define OMAP24XX_ST_VOLTLEVEL_MASK			(0x3 << 0)
+
+/* PRCM_CLKSRC_CTRL specific bits */
+
+/* PRCM_CLKOUT_CTRL */
+#define OMAP2420_CLKOUT2_EN_SHIFT			15
+#define OMAP2420_CLKOUT2_EN				(1 << 15)
+#define OMAP2420_CLKOUT2_DIV_SHIFT			11
+#define OMAP2420_CLKOUT2_DIV_MASK			(0x7 << 11)
+#define OMAP2420_CLKOUT2_SOURCE_SHIFT			8
+#define OMAP2420_CLKOUT2_SOURCE_MASK			(0x3 << 8)
+#define OMAP24XX_CLKOUT_EN_SHIFT			7
+#define OMAP24XX_CLKOUT_EN				(1 << 7)
+#define OMAP24XX_CLKOUT_DIV_SHIFT			3
+#define OMAP24XX_CLKOUT_DIV_MASK			(0x7 << 3)
+#define OMAP24XX_CLKOUT_SOURCE_SHIFT			0
+#define OMAP24XX_CLKOUT_SOURCE_MASK			(0x3 << 0)
+
+/* PRCM_CLKEMUL_CTRL */
+#define OMAP24XX_EMULATION_EN_SHIFT			0
+#define OMAP24XX_EMULATION_EN				(1 << 0)
+
+/* PRCM_CLKCFG_CTRL */
+#define OMAP24XX_VALID_CONFIG				(1 << 0)
+
+/* PRCM_CLKCFG_STATUS */
+#define OMAP24XX_CONFIG_STATUS				(1 << 0)
+
+/* PRCM_VOLTSETUP specific bits */
+
+/* PRCM_CLKSSETUP specific bits */
+
+/* PRCM_POLCTRL */
+#define OMAP2420_CLKOUT2_POL				(1 << 10)
+#define OMAP24XX_CLKOUT_POL				(1 << 9)
+#define OMAP24XX_CLKREQ_POL				(1 << 8)
+#define OMAP2430_USE_POWEROK				(1 << 2)
+#define OMAP2430_POWEROK_POL				(1 << 1)
+#define OMAP24XX_EXTVOL_POL				(1 << 0)
+
+/* RM_RSTST_MPU specific bits */
+/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */
+
+/* PM_WKDEP_MPU specific bits */
+#define OMAP2430_PM_WKDEP_MPU_EN_MDM			(1 << 5)
+#define OMAP24XX_PM_WKDEP_MPU_EN_DSP			(1 << 2)
+
+/* PM_EVGENCTRL_MPU specific bits */
+
+/* PM_EVEGENONTIM_MPU specific bits */
+
+/* PM_EVEGENOFFTIM_MPU specific bits */
+
+/* PM_PWSTCTRL_MPU specific bits */
+#define OMAP2430_FORCESTATE				(1 << 18)
+
+/* PM_PWSTST_MPU specific bits */
+/* INTRANSITION, CLKACTIVITY, POWERSTATE, MEMSTATEST are 2430 only */
+
+/* PM_WKEN1_CORE specific bits */
+
+/* PM_WKEN2_CORE specific bits */
+
+/* PM_WKST1_CORE specific bits*/
+
+/* PM_WKST2_CORE specific bits */
+
+/* PM_WKDEP_CORE specific bits*/
+#define OMAP2430_PM_WKDEP_CORE_EN_MDM			(1 << 5)
+#define OMAP24XX_PM_WKDEP_CORE_EN_GFX			(1 << 3)
+#define OMAP24XX_PM_WKDEP_CORE_EN_DSP			(1 << 2)
+
+/* PM_PWSTCTRL_CORE specific bits */
+#define OMAP24XX_MEMORYCHANGE				(1 << 20)
+#define OMAP24XX_MEM3ONSTATE_SHIFT			14
+#define OMAP24XX_MEM3ONSTATE_MASK			(0x3 << 14)
+#define OMAP24XX_MEM2ONSTATE_SHIFT			12
+#define OMAP24XX_MEM2ONSTATE_MASK			(0x3 << 12)
+#define OMAP24XX_MEM1ONSTATE_SHIFT			10
+#define OMAP24XX_MEM1ONSTATE_MASK			(0x3 << 10)
+#define OMAP24XX_MEM3RETSTATE				(1 << 5)
+#define OMAP24XX_MEM2RETSTATE				(1 << 4)
+#define OMAP24XX_MEM1RETSTATE				(1 << 3)
+
+/* PM_PWSTST_CORE specific bits */
+#define OMAP24XX_MEM3STATEST_SHIFT			14
+#define OMAP24XX_MEM3STATEST_MASK			(0x3 << 14)
+#define OMAP24XX_MEM2STATEST_SHIFT			12
+#define OMAP24XX_MEM2STATEST_MASK			(0x3 << 12)
+#define OMAP24XX_MEM1STATEST_SHIFT			10
+#define OMAP24XX_MEM1STATEST_MASK			(0x3 << 10)
+
+/* RM_RSTCTRL_GFX */
+#define OMAP24XX_GFX_RST				(1 << 0)
+
+/* RM_RSTST_GFX specific bits */
+#define OMAP24XX_GFX_SW_RST				(1 << 4)
+
+/* PM_PWSTCTRL_GFX specific bits */
+
+/* PM_WKDEP_GFX specific bits */
+/* 2430 often calls EN_WAKEUP "EN_WKUP" */
+
+/* RM_RSTCTRL_WKUP specific bits */
+
+/* RM_RSTTIME_WKUP specific bits */
+
+/* RM_RSTST_WKUP specific bits */
+/* 2430 calls EXTWMPU_RST "EXTWARM_RST" and GLOBALWMPU_RST "GLOBALWARM_RST" */
+#define OMAP24XX_EXTWMPU_RST				(1 << 6)
+#define OMAP24XX_SECU_WD_RST				(1 << 5)
+#define OMAP24XX_MPU_WD_RST				(1 << 4)
+#define OMAP24XX_SECU_VIOL_RST				(1 << 3)
+
+/* PM_WKEN_WKUP specific bits */
+
+/* PM_WKST_WKUP specific bits */
+
+/* RM_RSTCTRL_DSP */
+#define OMAP2420_RST_IVA				(1 << 8)
+#define OMAP24XX_RST2_DSP				(1 << 1)
+#define OMAP24XX_RST1_DSP				(1 << 0)
+
+/* RM_RSTST_DSP specific bits */
+/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" */
+#define OMAP2420_IVA_SW_RST				(1 << 8)
+#define OMAP24XX_DSP_SW_RST2				(1 << 5)
+#define OMAP24XX_DSP_SW_RST1				(1 << 4)
+
+/* PM_WKDEP_DSP specific bits */
+
+/* PM_PWSTCTRL_DSP specific bits */
+/* 2430 only: MEMONSTATE, MEMRETSTATE */
+#define OMAP2420_MEMIONSTATE_SHIFT			12
+#define OMAP2420_MEMIONSTATE_MASK			(0x3 << 12)
+#define OMAP2420_MEMIRETSTATE				(1 << 4)
+
+/* PM_PWSTST_DSP specific bits */
+/* MEMSTATEST is 2430 only */
+#define OMAP2420_MEMISTATEST_SHIFT			12
+#define OMAP2420_MEMISTATEST_MASK			(0x3 << 12)
+
+/* PRCM_IRQSTATUS_DSP specific bits */
+
+/* PRCM_IRQENABLE_DSP specific bits */
+
+/* RM_RSTCTRL_MDM */
+/* 2430 only */
+#define OMAP2430_PWRON1_MDM				(1 << 1)
+#define OMAP2430_RST1_MDM				(1 << 0)
+
+/* RM_RSTST_MDM specific bits */
+/* 2430 only */
+#define OMAP2430_MDM_SECU_VIOL				(1 << 6)
+#define OMAP2430_MDM_SW_PWRON1				(1 << 5)
+#define OMAP2430_MDM_SW_RST1				(1 << 4)
+
+/* PM_WKEN_MDM */
+/* 2430 only */
+#define OMAP2430_PM_WKEN_MDM_EN_MDM			(1 << 0)
+
+/* PM_WKST_MDM specific bits */
+/* 2430 only */
+
+/* PM_WKDEP_MDM specific bits */
+/* 2430 only */
+
+/* PM_PWSTCTRL_MDM specific bits */
+/* 2430 only */
+#define OMAP2430_KILLDOMAINWKUP				(1 << 19)
+
+/* PM_PWSTST_MDM specific bits */
+/* 2430 only */
+
+/* PRCM_IRQSTATUS_IVA */
+/* 2420 only */
+
+/* PRCM_IRQENABLE_IVA */
+/* 2420 only */
+
+#endif

Index: linux-omap/include/asm-arm/arch-omap/omap24xx.h
===================================================================
@@ -21,11 +21,15 @@
 #define OMAP2420_CTRL_BASE	L4_24XX_BASE
 #define OMAP2420_32KSYNCT_BASE	(L4_24XX_BASE + 0x4000)
 #define OMAP2420_PRCM_BASE	(L4_24XX_BASE + 0x8000)
+#define OMAP2420_CM_BASE	(L4_24XX_BASE + 0x8000)
+#define OMAP2420_PRM_BASE	OMAP2420_CM_BASE
 #define OMAP2420_SDRC_BASE	(L3_24XX_BASE + 0x9000)
 #define OMAP2420_SMS_BASE	0x68008000
 
 #define OMAP2430_32KSYNCT_BASE	(L4_WK_243X_BASE + 0x20000)
 #define OMAP2430_PRCM_BASE	(L4_WK_243X_BASE + 0x6000)
+#define OMAP2430_CM_BASE	(L4_WK_243X_BASE + 0x6000)
+#define OMAP2430_PRM_BASE	OMAP2430_CM_BASE
 
 #define OMAP243X_SMS_BASE	0x6C000000
 #define OMAP243X_SDRC_BASE	0x6D000000

@@ -52,6 +56,8 @@
 
 #define OMAP_32KSYNCT_BASE	OMAP2420_32KSYNCT_BASE
 #define PRCM_BASE		OMAP2420_PRCM_BASE
+#define CM_BASE			OMAP2420_CM_BASE
+#define PRM_BASE		OMAP2420_PRM_BASE
 #define SDRC_BASE		OMAP2420_SDRC_BASE
 #define SMS_BASE		OMAP2420_SMS_BASE
 #define L4_OMAP_BASE		L4_24XX_BASE

@@ -62,6 +68,8 @@
 
 #define OMAP_32KSYNCT_BASE	OMAP2430_32KSYNCT_BASE
 #define PRCM_BASE		OMAP2430_PRCM_BASE
+#define CM_BASE			OMAP2430_CM_BASE
+#define PRM_BASE		OMAP2430_PRM_BASE
 #define SDRC_BASE		OMAP243X_SDRC_BASE
 #define SMS_BASE		OMAP243X_SMS_BASE
 #define L4_OMAP_BASE		L4_24XX_BASE

Index: linux-omap/arch/arm/mach-omap2/pm.c
===================================================================
@@ -23,7 +23,6 @@
 #include <linux/pm.h>
 #include <linux/sched.h>
 #include <linux/proc_fs.h>
-#include <linux/pm.h>
 #include <linux/interrupt.h>
 #include <linux/sysfs.h>
 #include <linux/module.h>

@@ -48,116 +47,16 @@
 
 #include "sdrc.h"
 
-#define PRCM_REVISION		0x000
-#define PRCM_SYSCONFIG		0x010
-#define PRCM_IRQSTATUS_MPU	0x018
-#define PRCM_IRQENABLE_MPU	0x01c
-#define PRCM_VOLTCTRL		0x050
-#define		AUTO_EXTVOLT	(1 << 15)
-#define		FORCE_EXTVOLT	(1 << 14)
-#define		SETOFF_LEVEL(x)	(((x) & 0x3) << 12)
-#define		MEMRETCTRL	(1 << 8)
-#define		SETRET_LEVEL(x)	(((x) & 0x3) << 6)
-#define		VOLT_LEVEL(x)	(((x) & 0x3) << 0)
-#define PRCM_CLKSRC_CTRL	0x060
-#define PRCM_CLKOUT_CTRL	0x070
-#define PRCM_CLKEMUL_CTRL	0x078
-#define PRCM_CLKCFG_CTRL	0x080
-#define PRCM_VOLTSETUP		0x090
-#define PRCM_CLKSSETUP		0x094
-
-
-#define CM_CLKSEL_MPU		0x140
-#define CM_CLKSTCTRL_MPU	0x148
-#define		AUTOSTAT_MPU	(1 << 0)
-#define PM_WKDEP_MPU		0x1c8
-#define 	EN_WKUP		(1 << 4)
-#define 	EN_GFX		(1 << 3)
-#define 	EN_DSP		(1 << 2)
-#define 	EN_MPU		(1 << 1)
-#define 	EN_CORE		(1 << 0)
-#define PM_PWSTCTRL_MPU		0x1e0
-#define PM_PWSTST_MPU		0x1e4
-
-
-#define CM_FCLKEN1_CORE		0x200
-#define CM_FCLKEN2_CORE		0x204
-#define CM_ICLKEN1_CORE		0x210
-#define CM_ICLKEN2_CORE		0x214
-#define CM_ICLKEN4_CORE		0x21c
-#define CM_IDLEST1_CORE		0x220
-#define CM_IDLEST2_CORE		0x224
-#define CM_AUTOIDLE1_CORE	0x230
-#define CM_AUTOIDLE2_CORE	0x234
-#define CM_AUTOIDLE3_CORE	0x238
-#define CM_AUTOIDLE4_CORE	0x23c
-#define CM_CLKSEL1_CORE		0x240
-#define CM_CLKSEL2_CORE		0x244
-#define CM_CLKSTCTRL_CORE	0x248
-#define		AUTOSTAT_DSS	(1 << 2)
-#define		AUTOSTAT_L4	(1 << 1)
-#define		AUTOSTAT_L3	(1 << 0)
-#define PM_WKEN1_CORE		0x2a0
-#define PM_WKEN2_CORE		0x2a4
-#define PM_WKST1_CORE		0x2b0
-#define PM_WKST2_CORE		0x2b4
-#define PM_WKDEP_CORE		0x2c8
-#define PM_PWSTCTRL_CORE	0x2e0
-#define PM_PWSTST_CORE		0x2e4
-
-
-#define CM_CLKSTCTRL_GFX	0x348
-#define		AUTOSTAT_GFX	(1 << 0)
-#define PM_WKDEP_GFX    	0x3c8
-#define PM_PWSTCTRL_GFX		0x3e0
-
-
-#define CM_FCLKEN_WKUP		0x400
-#define CM_ICLKEN_WKUP		0x410
-#define CM_AUTOIDLE_WKUP	0x430
-#define PM_WKEN_WKUP		0x4a0
-#define 	EN_GPIOS	(1 << 2)
-#define 	EN_GPT1		(1 << 0)
-#define PM_WKST_WKUP		0x4b0
-
-
-#define CM_CLKEN_PLL		0x500
-#define CM_IDLEST_CKGEN		0x520
-#define CM_AUTOIDLE_PLL		0x530
-#define CM_CLKSEL1_PLL		0x540
-#define CM_CLKSEL2_PLL		0x544
-
-
-#define CM_FCLKEN_DSP		0x800
-#define CM_ICLKEN_DSP		0x810
-#define CM_IDLEST_DSP		0x820
-#define CM_AUTOIDLE_DSP		0x830
-#define CM_CLKSEL_DSP		0x840
-#define CM_CLKSTCTRL_DSP	0x848
-#define		AUTOSTAT_IVA	(1 << 8)
-#define		AUTOSTAT_DSP	(1 << 0)
-#define RM_RSTCTRL_DSP		0x850
-#define RM_RSTST_DSP		0x858
-#define PM_WKDEP_DSP		0x8c8
-#define PM_PWSTCTRL_DSP		0x8e0
-#define PM_PWSTST_DSP		0x8e4
+#include "prm.h"
+#include "prm_regbits_24xx.h"
+#include "cm.h"
+#include "cm_regbits_24xx.h"
+#include "sdrc.h"
 
 static void (*omap2_sram_idle)(void);
-static void (*omap2_sram_suspend)(void __iomem *dllctrl);
+static void (*omap2_sram_suspend)(void __iomem * dllctrl);
 static void (*saved_idle)(void);
 
-static u32 prcm_base = IO_ADDRESS(PRCM_BASE);
-
-static inline void prcm_write_reg(int idx, u32 val)
-{
-	__raw_writel(val, prcm_base + idx);
-}
-
-static inline u32 prcm_read_reg(int idx)
-{
-	return __raw_readl(prcm_base + idx);
-}
-
 static u32 omap2_read_32k_sync_counter(void)
 {
         return omap_readl(OMAP_32KSYNCT_BASE + 0x0010);

@@ -231,18 +130,18 @@ static void serial_console_sleep(int ena
 
 		switch (serial_console_uart)  {
 		case 1:
-			l = prcm_read_reg(PM_WKST1_CORE);
-			if (l & (1 << 21))
+			l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
+			if (l & OMAP24XX_ST_UART1)
 				serial_wakeup = 1;
 			break;
 		case 2:
-			l = prcm_read_reg(PM_WKST1_CORE);
-			if (l & (1 << 22))
+			l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
+			if (l & OMAP24XX_ST_UART2)
 				serial_wakeup = 1;
 			break;
 		case 3:
-			l = prcm_read_reg(PM_WKST2_CORE);
-			if (l & (1 << 2))
+			l = prm_read_mod_reg(CORE_MOD, PM_WKST2);
+			if (l & OMAP24XX_ST_UART3)
 				serial_wakeup = 1;
 			break;
 		}

@@ -283,26 +182,35 @@ static void pm_init_serial_console(void)
 	}
 	switch (serial_console_uart) {
 	case 1:
-		l = prcm_read_reg(PM_WKEN1_CORE);
-		l |= 1 << 21;
-		prcm_write_reg(PM_WKEN1_CORE, l);
+		l = prcm_read_mod_reg(CORE_MOD, PM_WKEN1);
+		l |= OMAP24XX_ST_UART1;
+		prm_write_mod_reg(l, CORE_MOD, PM_WKEN1);
 		break;
 	case 2:
-		l = prcm_read_reg(PM_WKEN1_CORE);
-		l |= 1 << 22;
-		prcm_write_reg(PM_WKEN1_CORE, l);
+		l = prcm_read_mod_reg(CORE_MOD, PM_WKEN1);
+		l |= OMAP24XX_ST_UART2;
+		prm_write_mod_reg(l, CORE_MOD, PM_WKEN1);
 		break;
 	case 3:
-		l = prcm_read_reg(PM_WKEN2_CORE);
-		l |= 1 << 2;
-		prcm_write_reg(PM_WKEN2_CORE, l);
+		l = prcm_read_mod_reg(CORE_MOD, PM_WKEN2);
+		l |= OMAP24XX_ST_UART3;
+		prm_write_mod_reg(l, CORE_MOD, PM_WKEN2);
 		break;
 	}
 }
 
-#define DUMP_REG(reg) \
+#define DUMP_PRM_MOD_REG(mod, reg)    \
+	regs[reg_count].name = #mod "." #reg; \
+	regs[reg_count++].val = prm_read_mod_reg(mod, reg)
+#define DUMP_CM_MOD_REG(mod, reg)     \
+	regs[reg_count].name = #mod "." #reg; \
+	regs[reg_count++].val = cm_read_mod_reg(mod, reg)
+#define DUMP_PRM_REG(reg) \
 	regs[reg_count].name = #reg; \
-	regs[reg_count++].val = prcm_read_reg(reg)
+	regs[reg_count++].val = prm_read_reg(reg)
+#define DUMP_CM_REG(reg) \
+	regs[reg_count].name = #reg; \
+	regs[reg_count++].val = cm_read_reg(reg)
 #define DUMP_INTC_REG(reg, off) \
 	regs[reg_count].name = #reg; \
 	regs[reg_count++].val = __raw_readl(IO_ADDRESS(0x480fe000 + (off)))

@@ -319,11 +227,11 @@ static void omap2_pm_dump(int mode, int 
 	if (!resume) {
 #if 0
 		/* MPU */
-		DUMP_REG(PRCM_IRQENABLE_MPU);
-		DUMP_REG(CM_CLKSTCTRL_MPU);
-		DUMP_REG(PM_PWSTCTRL_MPU);
-		DUMP_REG(PM_PWSTST_MPU);
-		DUMP_REG(PM_WKDEP_MPU);
+		DUMP_PRM_REG(OMAP24XX_PRCM_IRQENABLE_MPU);
+		DUMP_CM_MOD_REG(MPU_MOD, CM_CLKSTCTRL);
+		DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTCTRL);
+		DUMP_PRM_MOD_REG(MPU_MOD, PM_PWSTST);
+		DUMP_PRM_MOD_REG(MPU_MOD, PM_WKDEP);
 #endif
 #if 0
 		/* INTC */

@@ -332,36 +240,36 @@ static void omap2_pm_dump(int mode, int 
 		DUMP_INTC_REG(INTC_MIR2, 0x00c4);
 #endif
 #if 0
-		DUMP_REG(CM_FCLKEN1_CORE);
-		DUMP_REG(CM_FCLKEN2_CORE);
-		DUMP_REG(CM_FCLKEN_WKUP);
-		DUMP_REG(CM_ICLKEN1_CORE);
-		DUMP_REG(CM_ICLKEN2_CORE);
-		DUMP_REG(CM_ICLKEN_WKUP);
-		DUMP_REG(CM_CLKEN_PLL);
-		DUMP_REG(PRCM_CLKEMUL_CTRL);
-		DUMP_REG(CM_AUTOIDLE_PLL);
-		DUMP_REG(PM_PWSTST_CORE);
-		DUMP_REG(PRCM_CLKSRC_CTRL);
+		DUMP_CM_MOD_REG(CORE_MOD, CM_FCLKEN1);
+		DUMP_CM_MOD_REG(CORE_MOD, CM_FCLKEN2);
+		DUMP_CM_MOD_REG(WKUP_MOD, CM_FCLKEN);
+		DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN1);
+		DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN2);
+		DUMP_CM_MOD_REG(WKUP_MOD, CM_ICLKEN);
+		DUMP_CM_MOD_REG(PLL_MOD, CM_CLKEN_PLL);
+		DUMP_PRM_REG(OMAP24XX_PRCM_CLKEMUL_CTRL);
+		DUMP_CM_MOD_REG(PLL_MOD, CM_AUTOIDLE);
+		DUMP_PRM_MOD_REG(CORE_REG, PM_PWSTST);
+		DUMP_PRM_REG(OMAP24XX_PRCM_CLKSRC_CTRL);
 #endif
 #if 0
 		/* DSP */
-		DUMP_REG(CM_FCLKEN_DSP);
-		DUMP_REG(CM_ICLKEN_DSP);
-		DUMP_REG(CM_IDLEST_DSP);
-		DUMP_REG(CM_AUTOIDLE_DSP);
-		DUMP_REG(CM_CLKSEL_DSP);
-		DUMP_REG(CM_CLKSTCTRL_DSP);
-		DUMP_REG(RM_RSTCTRL_DSP);
-		DUMP_REG(RM_RSTST_DSP);
-		DUMP_REG(PM_PWSTCTRL_DSP);
-		DUMP_REG(PM_PWSTST_DSP);
+		DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_FCLKEN);
+		DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_ICLKEN);
+		DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_IDLEST);
+		DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_AUTOIDLE);
+		DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSEL);
+		DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSTCTRL);
+		DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTCTRL);
+		DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, RM_RSTST);
+		DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTCTRL);
+		DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, PM_PWSTST);
 #endif
 	} else {
-		DUMP_REG(PM_WKST1_CORE);
-		DUMP_REG(PM_WKST2_CORE);
-		DUMP_REG(PM_WKST_WKUP);
-		DUMP_REG(PRCM_IRQSTATUS_MPU);
+		DUMP_PRM_MOD_REG(CORE_MOD, PM_WKST1);
+		DUMP_PRM_MOD_REG(CORE_MOD, PM_WKST2);
+		DUMP_PRM_MOD_REG(WKUP_MOD, PM_WKST);
+		DUMP_PRM_REG(OMAP24XX_PRCM_IRQSTATUS_MPU);
 #if 1
 		DUMP_INTC_REG(INTC_PENDING_IRQ0, 0x0098);
 		DUMP_INTC_REG(INTC_PENDING_IRQ1, 0x00b8);

@@ -445,8 +353,8 @@ static int omap2_fclks_active(void)
 {
 	u32 f1, f2;
 
-	f1 = prcm_read_reg(CM_FCLKEN1_CORE);
-	f2 = prcm_read_reg(CM_FCLKEN2_CORE);
+	f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
+	f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
 	serial_console_fclk_mask(&f1, &f2);
 	if (f1 | f2)
 		return 1;

@@ -493,12 +401,14 @@ static void omap2_enter_full_retention(v
 	clk_disable(osc_ck);
 
 	/* Clear old wake-up events */
-	prcm_write_reg(PM_WKST1_CORE, 0xffffffff);
-	prcm_write_reg(PM_WKST2_CORE, 0xffffffff);
-	prcm_write_reg(PM_WKST_WKUP, 0xffffffff);
+	/* REVISIT: These write to reserved bits? */
+	prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
+	prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
+	prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 
 	/* Try to enter retention */
-	prcm_write_reg(PM_PWSTCTRL_MPU, (0x01 << 0) | (1 << 2));
+	prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | OMAP_LOGICRETSTATE,
+			  MPU_MOD, PM_PWSTCTRL);
 
 	/* Workaround to kill USB */
 	CONTROL_DEVCONF |= 0x00008000;

@@ -540,8 +450,8 @@ static int omap2_i2c_active(void)
 {
 	u32 l;
 
-	l = prcm_read_reg(CM_FCLKEN1_CORE);
-	return l & ((1 << 19) | (1 << 20));
+	l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
+	return l & (OMAP2420_EN_I2C2 | OMAP2420_EN_I2C1);
 }
 
 static int sti_console_enabled;

@@ -553,13 +463,15 @@ static int omap2_allow_mpu_retention(voi
 	if (atomic_read(&sleep_block))
 		return 0;
 
-	/* Check for UART2, UART1, McSPI2, McSPI1 and DSS1. */
-	l = prcm_read_reg(CM_FCLKEN1_CORE);
-	if (l & 0x04660001)
+	/* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
+	l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
+	if (l & (OMAP2420_EN_MMC | OMAP24XX_EN_UART2 |
+		 OMAP24XX_EN_UART1 | OMAP24XX_EN_MCSPI2 |
+		 OMAP24XX_EN_MCSPI1 | OMAP24XX_EN_DSS1))
 		return 0;
 	/* Check for UART3. */
-	l = prcm_read_reg(CM_FCLKEN2_CORE);
-	if (l & (1 << 2))
+	l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
+	if (l & OMAP24XX_EN_UART3)
 		return 0;
 	if (sti_console_enabled)
 		return 0;

@@ -580,15 +492,19 @@ static void omap2_enter_mpu_retention(vo
 	/* The peripherals seem not to be able to wake up the MPU when
 	 * it is in retention mode. */
 	if (omap2_allow_mpu_retention()) {
-		prcm_write_reg(PM_WKST1_CORE, 0xffffffff);
-		prcm_write_reg(PM_WKST2_CORE, 0xffffffff);
-		prcm_write_reg(PM_WKST_WKUP, 0xffffffff);
+	        /* REVISIT: These write to reserved bits? */
+		prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
+		prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
+		prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 
 		/* Try to enter MPU retention */
-		prcm_write_reg(PM_PWSTCTRL_MPU, (0x01 << 0) | (1 << 2));
+		prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
+				  OMAP_LOGICRETSTATE,
+				  MPU_MOD, PM_PWSTCTRL);
 	} else {
 		/* Block MPU retention */
-		prcm_write_reg(PM_PWSTCTRL_MPU, 1 << 2);
+
+		prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD, PM_PWSTCTRL);
 		only_idle = 1;
 	}
 

@@ -688,8 +604,8 @@ static int omap2_pm_suspend(void)
 {
 	u32 wken_wkup, mir1;
 
-	wken_wkup = prcm_read_reg(PM_WKEN_WKUP);
-	prcm_write_reg(PM_WKEN_WKUP, wken_wkup & ~EN_GPT1);
+	wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
+	prm_write_mod_reg(wken_wkup & ~OMAP24XX_EN_GPT1, WKUP_MOD, PM_WKEN);
 
 	/* Mask GPT1 */
 	mir1 = omap_readl(0x480fe0a4);

@@ -698,7 +614,7 @@ static int omap2_pm_suspend(void)
 	omap2_enter_full_retention();
 
 	omap_writel(mir1, 0x480fe0a4);
-	prcm_write_reg(PM_WKEN_WKUP, wken_wkup);
+	prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
 
 	return 0;
 }

@@ -737,58 +653,121 @@ static void __init prcm_setup_regs(void)
 	u32 l;
 
 	/* Enable autoidle */
-	prcm_write_reg(PRCM_SYSCONFIG, 1 << 0);
+	prm_write_reg(OMAP24XX_AUTOIDLE, OMAP24XX_PRCM_SYSCONFIG);
 
 	/* Set all domain wakeup dependencies */
-	prcm_write_reg(PM_WKDEP_MPU, EN_WKUP);
-	prcm_write_reg(PM_WKDEP_DSP, 0);
-	prcm_write_reg(PM_WKDEP_GFX, 0);
+	prm_write_mod_reg(OMAP_EN_WKUP, MPU_MOD, PM_WKDEP);
+	prm_write_mod_reg(0, OMAP24XX_DSP_MOD, PM_WKDEP);
+	prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
 
-	l = prcm_read_reg(PM_PWSTCTRL_CORE);
+	l = prm_read_mod_reg(CORE_MOD, PM_PWSTCTRL);
 	/* Enable retention for all memory blocks */
-	l |= (1 << 3) | (1 << 4) | (1 << 5);
-	/* Set power state to RETENTION */
-	l &= ~0x03;
-	l |= 0x01 << 0;
-	prcm_write_reg(PM_PWSTCTRL_CORE, l);
+	l |= OMAP24XX_MEM3RETSTATE | OMAP24XX_MEM2RETSTATE |
+		OMAP24XX_MEM1RETSTATE;
 
-	prcm_write_reg(PM_PWSTCTRL_MPU, (0x01 << 0) | (1 << 2));
+	/* Set power state to RETENTION */
+	l &= ~OMAP_POWERSTATE_MASK;
+	l |= 0x01 << OMAP_POWERSTATE_SHIFT;
+	prm_write_mod_reg(l, CORE_MOD, PM_PWSTCTRL);
+
+	prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
+			  OMAP_LOGICRETSTATE,
+			  MPU_MOD, PM_PWSTCTRL);
 
 	/* Power down DSP and GFX */
-	prcm_write_reg(PM_PWSTCTRL_DSP, (1 << 18) | 0x03);
-	prcm_write_reg(PM_PWSTCTRL_GFX, (1 << 18) | 0x03);
+	prm_write_mod_reg(OMAP24XX_FORCESTATE | (0x3 << OMAP_POWERSTATE_SHIFT),
+			  OMAP24XX_DSP_MOD, PM_PWSTCTRL);
+	prm_write_mod_reg(OMAP24XX_FORCESTATE | (0x3 << OMAP_POWERSTATE_SHIFT),
+			  GFX_MOD, PM_PWSTCTRL);
 
 	/* Enable clock auto control for all domains */
-	prcm_write_reg(CM_CLKSTCTRL_MPU, AUTOSTAT_MPU);
-	prcm_write_reg(CM_CLKSTCTRL_CORE, AUTOSTAT_DSS | AUTOSTAT_L4 | AUTOSTAT_L3);
-	prcm_write_reg(CM_CLKSTCTRL_GFX, AUTOSTAT_GFX);
-	prcm_write_reg(CM_CLKSTCTRL_DSP, AUTOSTAT_IVA | AUTOSTAT_DSP);
+	cm_write_mod_reg(OMAP24XX_AUTOSTATE_MPU, MPU_MOD, CM_CLKSTCTRL);
+	cm_write_mod_reg(OMAP24XX_AUTOSTATE_DSS | OMAP24XX_AUTOSTATE_L4 |
+			 OMAP24XX_AUTOSTATE_L3,
+			 CORE_MOD, CM_CLKSTCTRL);
+	cm_write_mod_reg(OMAP24XX_AUTOSTATE_GFX, GFX_MOD, CM_CLKSTCTRL);
+	cm_write_mod_reg(OMAP2420_AUTOSTATE_IVA | OMAP24XX_AUTOSTATE_DSP,
+			 OMAP24XX_DSP_MOD, CM_CLKSTCTRL);
 
 	/* Enable clock autoidle for all domains */
-	prcm_write_reg(CM_AUTOIDLE1_CORE, 0xfffffff9);
-	prcm_write_reg(CM_AUTOIDLE2_CORE, 0x07);
-	prcm_write_reg(CM_AUTOIDLE3_CORE, 0x07);
-	prcm_write_reg(CM_AUTOIDLE4_CORE, 0x1f);
+	cm_write_mod_reg(OMAP24XX_AUTO_CAM |
+			 OMAP24XX_AUTO_MAILBOXES |
+			 OMAP24XX_AUTO_WDT4 |
+			 OMAP2420_AUTO_WDT3 |
+			 OMAP24XX_AUTO_MSPRO |
+			 OMAP2420_AUTO_MMC |
+			 OMAP24XX_AUTO_FAC |
+			 OMAP2420_AUTO_EAC |
+			 OMAP24XX_AUTO_HDQ |
+			 OMAP24XX_AUTO_UART2 |
+			 OMAP24XX_AUTO_UART1 |
+			 OMAP24XX_AUTO_I2C2 |
+			 OMAP24XX_AUTO_I2C1 |
+			 OMAP24XX_AUTO_MCSPI2 |
+			 OMAP24XX_AUTO_MCSPI1 |
+			 OMAP24XX_AUTO_MCBSP2 |
+			 OMAP24XX_AUTO_MCBSP1 |
+			 OMAP24XX_AUTO_GPT12 |
+			 OMAP24XX_AUTO_GPT11 |
+			 OMAP24XX_AUTO_GPT10 |
+			 OMAP24XX_AUTO_GPT9 |
+			 OMAP24XX_AUTO_GPT8 |
+			 OMAP24XX_AUTO_GPT7 |
+			 OMAP24XX_AUTO_GPT6 |
+			 OMAP24XX_AUTO_GPT5 |
+			 OMAP24XX_AUTO_GPT4 |
+			 OMAP24XX_AUTO_GPT3 |
+			 OMAP24XX_AUTO_GPT2 |
+			 OMAP2420_AUTO_VLYNQ |
+			 OMAP24XX_AUTO_DSS,
+			 CORE_MOD, CM_AUTOIDLE1);
+	cm_write_mod_reg(OMAP24XX_AUTO_UART3 |
+			 OMAP24XX_AUTO_SSI |
+			 OMAP24XX_AUTO_USB,
+			 CORE_MOD, CM_AUTOIDLE2);
+	cm_write_mod_reg(OMAP24XX_AUTO_SDRC |
+			 OMAP24XX_AUTO_GPMC |
+			 OMAP24XX_AUTO_SDMA,
+			 CORE_MOD, OMAP24XX_CM_AUTOIDLE3);
+	cm_write_mod_reg(OMAP24XX_AUTO_PKA |
+			 OMAP24XX_AUTO_AES |
+			 OMAP24XX_AUTO_RNG |
+			 OMAP24XX_AUTO_SHA |
+			 OMAP24XX_AUTO_DES,
+			 CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
 
-	prcm_write_reg(CM_AUTOIDLE_DSP, 0x02);
+	cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI, OMAP24XX_DSP_MOD, CM_AUTOIDLE);
 
 	/* Put DPLL and both APLLs into autoidle mode */
-	prcm_write_reg(CM_AUTOIDLE_PLL, (0x03 << 0) | (0x03 << 2) | (0x03 << 6));
-
-	prcm_write_reg(CM_AUTOIDLE_WKUP, 0x3f);
+	cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
+			 (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
+			 (0x03 << OMAP24XX_AUTO_54M_SHIFT),
+			 PLL_MOD, CM_AUTOIDLE);
+
+	cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL |
+			 OMAP24XX_AUTO_WDT1 |
+			 OMAP24XX_AUTO_MPU_WDT |
+			 OMAP24XX_AUTO_GPIOS |
+			 OMAP24XX_AUTO_32KSYNC |
+			 OMAP24XX_AUTO_GPT1,
+			 WKUP_MOD, CM_AUTOIDLE);
 
 	/* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
 	 * stabilisation */
-	prcm_write_reg(PRCM_CLKSSETUP, 15);
+	prm_write_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_CLKSSETUP);
 
 	/* Configure automatic voltage transition */
-	prcm_write_reg(PRCM_VOLTSETUP, 2);
-	l = AUTO_EXTVOLT | SETOFF_LEVEL(1) | MEMRETCTRL | \
-		SETRET_LEVEL(1) | VOLT_LEVEL(0);
-	prcm_write_reg(PRCM_VOLTCTRL, l);
+	prm_write_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_VOLTSETUP);
+	prm_write_reg(OMAP24XX_AUTO_EXTVOLT |
+		      (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
+		      OMAP24XX_MEMRETCTRL |
+		      (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
+		      (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
+		      OMAP24XX_PRCM_VOLTCTRL);
 
 	/* Enable wake-up events */
-	prcm_write_reg(PM_WKEN_WKUP, EN_GPIOS | EN_GPT1);
+	prm_write_mod_reg(OMAP24XX_EN_GPIOS | OMAP24XX_EN_GPT1,
+			  WKUP_MOD, PM_WKEN);
 }
 
 int __init omap2_pm_init(void)

@@ -796,7 +775,7 @@ int __init omap2_pm_init(void)
 	u32 l;
 
 	printk(KERN_INFO "Power Management for OMAP2 initializing\n");
-	l = prcm_read_reg(PRCM_REVISION);
+	l = prm_read_reg(OMAP24XX_PRCM_REVISION);
 	printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
 
 	osc_ck = clk_get(NULL, "osc_ck");

index 1d02406..8cacfa4 100644
@@ -29,13 +29,20 @@
 #include <asm/arch/sram.h>
 #include <asm/div64.h>
 
-#include "prcm-regs.h"
 #include "memory.h"
 #include "clock.h"
+#include "prm.h"
+#include "prm_regbits_24xx.h"
+#include "cm.h"
+#include "cm_regbits_24xx.h"
 #include "sdrc.h"
 
 #undef DEBUG
 
+/* SET_PERFORMANCE_LEVEL PARAMETERS */
+#define PRCM_HALF_SPEED		1
+#define PRCM_FULL_SPEED		2
+
 //#define DOWN_VARIABLE_DPLL 1			/* Experimental */
 
 static struct prcm_config *curr_prcm_set;

@@ -50,8 +57,9 @@ static struct clk *sclk;
 /* Recalculate SYST_CLK */
 static void omap2_sys_clk_recalc(struct clk * clk)
 {
-	u32 div = PRCM_CLKSRC_CTRL;
-	div &= (1 << 7) | (1 << 6);	/* Test if ext clk divided by 1 or 2 */
+	u32 div = prm_read_reg(OMAP24XX_PRCM_CLKSRC_CTRL);
+	/* Test if ext clk divided by 1 or 2 */
+	div &= (0x3 << OMAP_SYSCLKDIV_SHIFT);
 	div >>= clk->rate_offset;
 	clk->rate = (clk->parent->rate / div);
 	propagate_rate(clk);

@@ -61,12 +69,18 @@ static u32 omap2_get_dpll_rate(struct clk * tclk)
 {
 	long long dpll_clk;
 	int dpll_mult, dpll_div, amult;
+	u32 dpll;
+
+	dpll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
 
-	dpll_mult = (CM_CLKSEL1_PLL >> 12) & 0x03ff;	/* 10 bits */
-	dpll_div = (CM_CLKSEL1_PLL >> 8) & 0x0f;	/* 4 bits */
+	dpll_mult = dpll & OMAP24XX_DPLL_MULT_MASK;
+	dpll_mult >>= OMAP24XX_DPLL_MULT_SHIFT;		/* 10 bits */
+	dpll_div = dpll & OMAP24XX_DPLL_DIV_MASK;
+	dpll_div >>= OMAP24XX_DPLL_DIV_SHIFT;		/* 4 bits */
 	dpll_clk = (long long)tclk->parent->rate * dpll_mult;
 	do_div(dpll_clk, dpll_div + 1);
-	amult = CM_CLKSEL2_PLL & 0x3;
+	amult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+	amult &= OMAP24XX_CORE_CLK_SRC_MASK;
 	dpll_clk *= amult;
 
 	return dpll_clk;

@@ -87,10 +101,16 @@ static void omap2_propagate_rate(struct clk * clk)
 
 static void omap2_set_osc_ck(int enable)
 {
+	u32 pcc;
+
+	pcc = prm_read_reg(OMAP24XX_PRCM_CLKSRC_CTRL);
+
 	if (enable)
-		PRCM_CLKSRC_CTRL &= ~(0x3 << 3);
+		prm_write_reg(pcc & ~OMAP_AUTOEXTCLKMODE_MASK,
+			      OMAP24XX_PRCM_CLKSRC_CTRL);
 	else
-		PRCM_CLKSRC_CTRL |= 0x3 << 3;
+		prm_write_reg(pcc | OMAP_AUTOEXTCLKMODE_MASK,
+			      OMAP24XX_PRCM_CLKSRC_CTRL);
 }
 
 /* Enable an APLL if off */

@@ -101,21 +121,22 @@ static void omap2_clk_fixed_enable(struct clk *clk)
 	if (clk->enable_bit == PARENT_CONTROLS_CLOCK)	/* Parent will do it */
 		return;
 
-	cval = CM_CLKEN_PLL;
+	cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
 
 	if ((cval & (0x3 << clk->enable_bit)) == (0x3 << clk->enable_bit))
 		return;
 
 	cval &= ~(0x3 << clk->enable_bit);
 	cval |= (0x3 << clk->enable_bit);
-	CM_CLKEN_PLL = cval;
+	cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
 
 	if (clk == &apll96_ck)
-		cval = (1 << 8);
+		cval = OMAP24XX_ST_96M_APLL;
 	else if (clk == &apll54_ck)
-		cval = (1 << 6);
+		cval = OMAP24XX_ST_54M_CLK;
 
-	while (!(CM_IDLEST_CKGEN & cval)) {		/* Wait for lock */
+	/* Wait for lock */
+	while (!(cm_read_mod_reg(PLL_MOD, CM_IDLEST) & cval)) {
 		++i;
 		udelay(1);
 		if (i == 100000) {

@@ -132,12 +153,12 @@ static void omap2_clk_wait_ready(struct clk *clk)
 	int i;
 
 	reg = (unsigned long) clk->enable_reg;
-	if (reg == (unsigned long) &CM_FCLKEN1_CORE ||
-	    reg == (unsigned long) &CM_FCLKEN2_CORE)
-		other_reg = (reg & ~0xf0) | 0x10;
-	else if (reg == (unsigned long) &CM_ICLKEN1_CORE ||
-		 reg == (unsigned long) &CM_ICLKEN2_CORE)
-		other_reg = (reg & ~0xf0) | 0x00;
+	if (reg == (unsigned long)OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1) ||
+	    reg == (unsigned long)OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2))
+		other_reg = (reg & ~0xf0) | 0x10; /* CM_ICLKEN* */
+	else if (reg == (unsigned long)OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1) ||
+		 reg == (unsigned long)OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2))
+		other_reg = (reg & ~0xf0) | 0x00; /* CM_FCLKEN* */
 	else
 		return;
 

@@ -150,11 +171,11 @@ static void omap2_clk_wait_ready(struct clk *clk)
 	/* Check if both functional and interface clocks
 	 * are running. */
 	bit = 1 << clk->enable_bit;
-	if (!(__raw_readl(other_reg) & bit))
+	if (!(cm_read_reg((void __iomem *)other_reg) & bit))
 		return;
-	st_reg = (other_reg & ~0xf0) | 0x20;
+	st_reg = (other_reg & ~0xf0) | 0x20; /* CM_IDLEST* */
 	i = 0;
-	while (!(__raw_readl(st_reg) & bit)) {
+	while (!(cm_read_reg((void __iomem *)st_reg) & bit)) {
 		i++;
 		if (i == 100000) {
 			printk(KERN_ERR "Timeout enabling clock %s\n", clk->name);

@@ -186,14 +207,14 @@ static int _omap2_clk_enable(struct clk * clk)
 		return 0;
 	}
 
-	if (clk->enable_reg == (void __iomem *)&CM_CLKEN_PLL) {
+	if (clk->enable_reg == (void __iomem *)OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN)) {
 		omap2_clk_fixed_enable(clk);
 		return 0;
 	}
 
-	regval32 = __raw_readl(clk->enable_reg);
+	regval32 = cm_read_reg(clk->enable_reg);
 	regval32 |= (1 << clk->enable_bit);
-	__raw_writel(regval32, clk->enable_reg);
+	cm_write_reg(regval32, clk->enable_reg);
 	wmb();
 
 	omap2_clk_wait_ready(clk);

@@ -209,9 +230,9 @@ static void omap2_clk_fixed_disable(struct clk *clk)
 	if (clk->enable_bit == PARENT_CONTROLS_CLOCK)
 		return;		/* let parent off do it */
 
-	cval = CM_CLKEN_PLL;
+	cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
 	cval &= ~(0x3 << clk->enable_bit);
-	CM_CLKEN_PLL = cval;
+	cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
 }
 
 /* Disables clock without considering parent dependencies or use count */

@@ -227,14 +248,14 @@ static void _omap2_clk_disable(struct clk *clk)
 	if (clk->enable_reg == 0)
 		return;
 
-	if (clk->enable_reg == (void __iomem *)&CM_CLKEN_PLL) {
+	if (clk->enable_reg == (void __iomem *)OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN)) {
 		omap2_clk_fixed_disable(clk);
 		return;
 	}
 
-	regval32 = __raw_readl(clk->enable_reg);
+	regval32 = cm_read_reg(clk->enable_reg);
 	regval32 &= ~(1 << clk->enable_bit);
-	__raw_writel(regval32, clk->enable_reg);
+	cm_write_reg(regval32, clk->enable_reg);
 	wmb();
 }
 

@@ -277,9 +298,12 @@ static void omap2_clk_disable(struct clk *clk)
  */
 static u32 omap2_dpll_round_rate(unsigned long target_rate)
 {
-	u32 high, low;
+	u32 high, low, core_clk_src;
 
-	if ((CM_CLKSEL2_PLL & 0x3) == 1) {	/* DPLL clockout */
+	core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+	core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
+
+	if (core_clk_src == 1) {	/* DPLL clockout */
 		high = curr_prcm_set->dpll_speed * 2;
 		low = curr_prcm_set->dpll_speed;
 	} else {				/* DPLL clockout x 2 */

@@ -308,6 +332,7 @@ static u32 omap2_dpll_round_rate(unsigned long target_rate)
 static void omap2_clksel_recalc(struct clk * clk)
 {
 	u32 fixed = 0, div = 0;
+	u32 clksel1_core;
 
 	if (clk == &dpll_ck) {
 		clk->rate = omap2_get_dpll_rate(clk);

@@ -320,7 +345,10 @@ static void omap2_clksel_recalc(struct clk * clk)
 		fixed = 1;
 	}
 
-	if ((clk == &dss1_fck) && ((CM_CLKSEL1_CORE & (0x1f << 8)) == 0)) {
+	clksel1_core = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1);
+
+	if ((clk == &dss1_fck) &&
+	    (clksel1_core & OMAP24XX_CLKSEL_DSS1_MASK) == 0) {
 		clk->rate = sys_ck.rate;
 		return;
 	}

@@ -471,7 +499,7 @@ static u32 omap2_reprogram_sdrc(u32 level, u32 force)
 
 	if (level == PRCM_HALF_SPEED) {
 		local_irq_save(flags);
-		PRCM_VOLTSETUP = 0xffff;
+		prm_write_reg(0xffff, OMAP24XX_PRCM_VOLTSETUP);
 		omap2_sram_reprogram_sdrc(PRCM_HALF_SPEED,
 					  slow_dll_ctrl, m_type);
 		curr_perf_level = PRCM_HALF_SPEED;

@@ -479,7 +507,7 @@ static u32 omap2_reprogram_sdrc(u32 level, u32 force)
 	}
 	if (level == PRCM_FULL_SPEED) {
 		local_irq_save(flags);
-		PRCM_VOLTSETUP = 0xffff;
+		prm_write_reg(0xffff, OMAP24XX_PRCM_VOLTSETUP);
 		omap2_sram_reprogram_sdrc(PRCM_FULL_SPEED,
 					  fast_dll_ctrl, m_type);
 		curr_perf_level = PRCM_FULL_SPEED;

@@ -498,7 +526,8 @@ static int omap2_reprogram_dpll(struct clk * clk, unsigned long rate)
 
 	local_irq_save(flags);
 	cur_rate = omap2_get_dpll_rate(&dpll_ck);
-	mult = CM_CLKSEL2_PLL & 0x3;
+	mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+	mult &= OMAP24XX_CORE_CLK_SRC_MASK;
 
 	if ((rate == (cur_rate / 2)) && (mult == 2)) {
 		omap2_reprogram_sdrc(PRCM_HALF_SPEED, 1);

@@ -509,16 +538,17 @@ static int omap2_reprogram_dpll(struct clk * clk, unsigned long rate)
 		if (valid_rate != rate)
 			goto dpll_exit;
 
-		if ((CM_CLKSEL2_PLL & 0x3) == 1)
+		if (mult == 1)
 			low = curr_prcm_set->dpll_speed;
 		else
 			low = curr_prcm_set->dpll_speed / 2;
 
-		tmpset.cm_clksel1_pll = CM_CLKSEL1_PLL;
+		/* REVISIT: This sets several reserved bits? */
+		tmpset.cm_clksel1_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
 		tmpset.cm_clksel1_pll &= ~(0x3FFF << 8);
 		div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
-		tmpset.cm_clksel2_pll = CM_CLKSEL2_PLL;
-		tmpset.cm_clksel2_pll &= ~0x3;
+		tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+		tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
 		if (rate > low) {
 			tmpset.cm_clksel2_pll |= 0x2;
 			mult = ((rate / 2) / 1000000);

@@ -528,7 +558,8 @@ static int omap2_reprogram_dpll(struct clk * clk, unsigned long rate)
 			mult = (rate / 1000000);
 			done_rate = PRCM_HALF_SPEED;
 		}
-		tmpset.cm_clksel1_pll |= ((div << 8) | (mult << 12));
+		tmpset.cm_clksel1_pll |= (div << OMAP24XX_DPLL_DIV_SHIFT);
+		tmpset.cm_clksel1_pll |= (mult << OMAP24XX_DPLL_MULT_SHIFT);
 
 		/* Worst case */
 		tmpset.base_sdrc_rfr = V24XX_SDRC_RFR_CTRL_BYPASS;

@@ -617,74 +648,87 @@ static u32 omap2_get_clksel(u32 *div_sel, u32 *field_mask,
 {
 	int ret = ~0;
 	u32 reg_val, div_off;
-	u32 div_addr = 0;
+	void __iomem *div_addr = 0;
 	u32 mask = ~0;
 
 	div_off = clk->rate_offset;
 
 	switch ((*div_sel & SRC_RATE_SEL_MASK)) {
 	case CM_MPU_SEL1:
-		div_addr = (u32)&CM_CLKSEL_MPU;
-		mask = 0x1f;
+		div_addr = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL);
+		mask = OMAP24XX_CLKSEL_MPU_MASK;
 		break;
 	case CM_DSP_SEL1:
-		div_addr = (u32)&CM_CLKSEL_DSP;
+		div_addr = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL);
 		if (cpu_is_omap2420()) {
-			if ((div_off == 0) || (div_off == 8))
-				mask = 0x1f;
-			else if (div_off == 5)
-				mask = 0x3;
+			if (div_off == OMAP24XX_CLKSEL_DSP_SHIFT)
+				mask = OMAP24XX_CLKSEL_DSP_MASK;
+			else if (div_off == OMAP2420_CLKSEL_IVA_SHIFT)
+				mask = OMAP2420_CLKSEL_IVA_MASK;
+			else if (div_off == OMAP24XX_CLKSEL_DSP_IF_SHIFT)
+				mask = OMAP24XX_CLKSEL_DSP_IF_MASK;
 		} else if (cpu_is_omap2430()) {
-			if (div_off == 0)
-				mask = 0x1f;
-			else if (div_off == 5)
-				mask = 0x3;
+			if (div_off == OMAP24XX_CLKSEL_DSP_SHIFT)
+				mask = OMAP24XX_CLKSEL_DSP_MASK;
+			else if (div_off == OMAP24XX_CLKSEL_DSP_IF_SHIFT)
+				mask = OMAP24XX_CLKSEL_DSP_IF_MASK;
 		}
-		break;
 	case CM_GFX_SEL1:
-		div_addr = (u32)&CM_CLKSEL_GFX;
-		if (div_off == 0)
-			mask = 0x7;
+		div_addr = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL);
+		if (div_off == OMAP_CLKSEL_GFX_SHIFT)
+			mask = OMAP_CLKSEL_GFX_MASK;
 		break;
 	case CM_MODEM_SEL1:
-		div_addr = (u32)&CM_CLKSEL_MDM;
-		if (div_off == 0)
-			mask = 0xf;
+		div_addr = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL);
+		if (div_off == OMAP2430_CLKSEL_MDM_SHIFT)
+			mask = OMAP2430_CLKSEL_MDM_MASK;
 		break;
 	case CM_SYSCLKOUT_SEL1:
-		div_addr = (u32)&PRCM_CLKOUT_CTRL;
-		if ((div_off == 3) || (div_off == 11))
-			mask= 0x3;
+		div_addr = OMAP24XX_PRCM_CLKOUT_CTRL;
+		if (div_off == OMAP24XX_CLKOUT_DIV_SHIFT)
+			mask = OMAP24XX_CLKOUT_DIV_MASK;
+		else if (div_off == OMAP2420_CLKOUT2_DIV_SHIFT)
+			mask = OMAP2420_CLKOUT2_DIV_MASK;
 		break;
 	case CM_CORE_SEL1:
-		div_addr = (u32)&CM_CLKSEL1_CORE;
+		div_addr = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1);
 		switch (div_off) {
-		case 0:					/* l3 */
-		case 8:					/* dss1 */
-		case 15:				/* vylnc-2420 */
-		case 20:				/* ssi */
-			mask = 0x1f; break;
-		case 5:					/* l4 */
-			mask = 0x3; break;
-		case 13:				/* dss2 */
-			mask = 0x1; break;
-		case 25:				/* usb */
-			mask = 0x7; break;
+		case OMAP24XX_CLKSEL_L3_SHIFT:
+			mask = OMAP24XX_CLKSEL_L3_MASK;
+			break;
+		case OMAP24XX_CLKSEL_L4_SHIFT:
+			mask = OMAP24XX_CLKSEL_L4_MASK;
+			break;
+		case OMAP24XX_CLKSEL_DSS1_SHIFT:
+			mask = OMAP24XX_CLKSEL_DSS1_MASK;
+			break;
+		case OMAP24XX_CLKSEL_DSS2_SHIFT:
+			mask = OMAP24XX_CLKSEL_DSS2_MASK;
+			break;
+		case OMAP2420_CLKSEL_VLYNQ_SHIFT:
+			mask = OMAP2420_CLKSEL_VLYNQ_MASK;
+			break;
+		case OMAP24XX_CLKSEL_SSI_SHIFT:
+			mask = OMAP24XX_CLKSEL_SSI_MASK;
+			break;
+		case OMAP24XX_CLKSEL_USB_SHIFT:
+			mask = OMAP24XX_CLKSEL_USB_MASK;
+			break;
 		}
 	}
 
-	*field_mask = mask;
+	*field_mask = (mask >> div_off);
 
 	if (unlikely(mask == ~0))
 		div_addr = 0;
 
-	*div_sel = div_addr;
+	*div_sel = (u32)div_addr;
 
 	if (unlikely(div_addr == 0))
 		return ret;
 
 	/* Isolate field */
-	reg_val = __raw_readl((void __iomem *)div_addr) & (mask << div_off);
+	reg_val = cm_read_reg(div_addr) & mask;
 
 	/* Normalize back to divider value */
 	reg_val >>= div_off;

@@ -763,15 +807,16 @@ static int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
 
 		reg = (void __iomem *)div_sel;
 
-		reg_val = __raw_readl(reg);
+		reg_val = cm_read_reg(reg);
 		reg_val &= ~(field_mask << div_off);
 		reg_val |= (field_val << div_off);
-		__raw_writel(reg_val, reg);
+		cm_write_reg(reg_val, reg);
 		wmb();
 		clk->rate = clk->parent->rate / field_val;
 
 		if (clk->flags & DELAYED_APP) {
-			__raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL);
+			prm_write_reg(OMAP24XX_VALID_CONFIG,
+				      OMAP24XX_PRCM_CLKCFG_CTRL);
 			wmb();
 		}
 		ret = 0;

@@ -788,26 +833,31 @@ static int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
 static u32 omap2_get_src_field(u32 *type_to_addr, u32 reg_offset,
 			       struct clk *src_clk, u32 *field_mask)
 {
-	u32 val = ~0, src_reg_addr = 0, mask = 0;
+	u32 val = ~0, mask = 0;
+	void __iomem *src_reg_addr = 0;
 
 	/* Find target control register.*/
 	switch ((*type_to_addr & SRC_RATE_SEL_MASK)) {
 	case CM_CORE_SEL1:
-		src_reg_addr = (u32)&CM_CLKSEL1_CORE;
-		if (reg_offset == 13) {			/* DSS2_fclk */
-			mask = 0x1;
+		src_reg_addr = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1);
+		if (reg_offset == OMAP24XX_CLKSEL_DSS2_SHIFT) {
+			mask = OMAP24XX_CLKSEL_DSS2_MASK;
+			mask >>= OMAP24XX_CLKSEL_DSS2_SHIFT;
 			if (src_clk == &sys_ck)
 				val = 0;
 			if (src_clk == &func_48m_ck)
 				val = 1;
-		} else if (reg_offset == 8) {		/* DSS1_fclk */
-			mask = 0x1f;
+		} else if (reg_offset == OMAP24XX_CLKSEL_DSS1_SHIFT) {
+			mask = OMAP24XX_CLKSEL_DSS1_MASK;
+			mask >>= OMAP24XX_CLKSEL_DSS1_SHIFT;
 			if (src_clk == &sys_ck)
 				val = 0;
 			else if (src_clk == &core_ck)	/* divided clock */
 				val = 0x10;		/* rate needs fixing */
-		} else if ((reg_offset == 15) && cpu_is_omap2420()){ /*vlnyq*/
-			mask = 0x1F;
+		} else if ((reg_offset == OMAP2420_CLKSEL_VLYNQ_SHIFT) &&
+			   cpu_is_omap2420()){
+			mask = OMAP2420_CLKSEL_VLYNQ_MASK;
+			mask >>= OMAP2420_CLKSEL_VLYNQ_SHIFT;
 			if(src_clk == &func_96m_ck)
 				val = 0;
 			else if (src_clk == &core_ck)

@@ -815,7 +865,7 @@ static u32 omap2_get_src_field(u32 *type_to_addr, u32 reg_offset,
 		}
 		break;
 	case CM_CORE_SEL2:
-		src_reg_addr = (u32)&CM_CLKSEL2_CORE;
+		src_reg_addr = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2);
 		mask = 0x3;
 		if (src_clk == &func_32k_ck)
 			val = 0x0;

@@ -825,7 +875,7 @@ static u32 omap2_get_src_field(u32 *type_to_addr, u32 reg_offset,
 			val = 0x2;
 		break;
 	case CM_WKUP_SEL1:
-		src_reg_addr = (u32)&CM_CLKSEL_WKUP;
+		src_reg_addr = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL);
 		mask = 0x3;
 		if (src_clk == &func_32k_ck)
 			val = 0x0;

@@ -835,7 +885,7 @@ static u32 omap2_get_src_field(u32 *type_to_addr, u32 reg_offset,
 			val = 0x2;
 		break;
 	case CM_PLL_SEL1:
-		src_reg_addr = (u32)&CM_CLKSEL1_PLL;
+		src_reg_addr = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1);
 		mask = 0x1;
 		if (reg_offset == 0x3) {
 			if (src_clk == &apll96_ck)

@@ -851,7 +901,7 @@ static u32 omap2_get_src_field(u32 *type_to_addr, u32 reg_offset,
 		}
 		break;
 	case CM_PLL_SEL2:
-		src_reg_addr = (u32)&CM_CLKSEL2_PLL;
+		src_reg_addr = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2);
 		mask = 0x3;
 		if (src_clk == &func_32k_ck)
 			val = 0x0;

@@ -859,7 +909,7 @@ static u32 omap2_get_src_field(u32 *type_to_addr, u32 reg_offset,
 			val = 0x2;
 		break;
 	case CM_SYSCLKOUT_SEL1:
-		src_reg_addr = (u32)&PRCM_CLKOUT_CTRL;
+		src_reg_addr = OMAP24XX_PRCM_CLKOUT_CTRL;
 		mask = 0x3;
 		if (src_clk == &dpll_ck)
 			val = 0;

@@ -875,7 +925,7 @@ static u32 omap2_get_src_field(u32 *type_to_addr, u32 reg_offset,
 	if (val == ~0)			/* Catch errors in offset */
 		*type_to_addr = 0;
 	else
-		*type_to_addr = src_reg_addr;
+		*type_to_addr = (u32)src_reg_addr;
 	*field_mask = mask;
 
 	return val;

@@ -912,7 +962,8 @@ static int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
 		wmb();
 
 		if (clk->flags & DELAYED_APP) {
-			__raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL);
+			prm_write_reg(OMAP24XX_VALID_CONFIG,
+				      OMAP24XX_PRCM_CLKCFG_CTRL);
 			wmb();
 		}
 		if (clk->usecount > 0)

@@ -990,23 +1041,25 @@ static int omap2_select_table_rate(struct clk * clk, unsigned long rate)
 		if (prcm->dpll_speed == prcm->xtal_speed)
 			bypass = 1;
 
-		if ((prcm->cm_clksel2_pll & 0x3) == 2)
+		if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) == 2)
 			done_rate = PRCM_FULL_SPEED;
 		else
 			done_rate = PRCM_HALF_SPEED;
 
 		/* MPU divider */
-		CM_CLKSEL_MPU = prcm->cm_clksel_mpu;
+		cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
 
 		/* dsp + iva1 div(2420), iva2.1(2430) */
-		CM_CLKSEL_DSP = prcm->cm_clksel_dsp;
+		cm_write_mod_reg(prcm->cm_clksel_dsp,
+				 OMAP24XX_DSP_MOD, CM_CLKSEL);
 
-		CM_CLKSEL_GFX = prcm->cm_clksel_gfx;
+		cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
 
 		/* Major subsystem dividers */
-		CM_CLKSEL1_CORE = prcm->cm_clksel1_core;
+		cm_write_mod_reg(prcm->cm_clksel1_core, CORE_MOD, CM_CLKSEL1);
 		if (cpu_is_omap2430())
-			CM_CLKSEL_MDM = prcm->cm_clksel_mdm;
+			cm_write_mod_reg(prcm->cm_clksel_mdm,
+					 OMAP2430_MDM_MOD, CM_CLKSEL);
 
 		/* x2 to enter init_mem */
 		omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1);

@@ -1033,7 +1086,7 @@ static void __init omap2_clk_disable_unused(struct clk *clk)
 {
 	u32 regval32;
 
-	regval32 = __raw_readl(clk->enable_reg);
+	regval32 = cm_read_reg(clk->enable_reg);
 	if ((regval32 & (1 << clk->enable_bit)) == 0)
 		return;
 

@@ -1057,9 +1110,9 @@ static void __init omap2_get_crystal_rate(struct clk *osc, struct clk *sys)
 {
 	u32 div, aplls, sclk = 13000000;
 
-	aplls = CM_CLKSEL1_PLL;
-	aplls &= ((1 << 23) | (1 << 24) | (1 << 25));
-	aplls >>= 23;			/* Isolate field, 0,2,3 */
+	aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
+	aplls &= OMAP24XX_APLLS_CLKIN_MASK;
+	aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;	/* Isolate field, 0,2,3 */
 
 	if (aplls == 0)
 		sclk = 19200000;

@@ -1068,8 +1121,8 @@ static void __init omap2_get_crystal_rate(struct clk *osc, struct clk *sys)
 	else if (aplls == 3)
 		sclk = 12000000;
 
-	div = PRCM_CLKSRC_CTRL;
-	div &= ((1 << 7) | (1 << 6));
+	div = prm_read_reg(OMAP24XX_PRCM_CLKSRC_CTRL);
+	div &= OMAP_SYSCLKDIV_MASK;
 	div >>= sys->rate_offset;
 
 	osc->rate = sclk * div;

index 90f5305..9af8848 100644
@@ -17,19 +17,22 @@
 #include <linux/init.h>
 #include <linux/clk.h>
 
-#include "prcm-regs.h"
+#include "prm.h"
+#include "prm_regbits_24xx.h"
 
 extern void omap2_clk_prepare_for_reboot(void);
 
 u32 omap_prcm_get_reset_sources(void)
 {
-	return RM_RSTST_WKUP & 0x7f;
+	return prm_read_mod_reg(WKUP_MOD, RM_RSTST) & 0x7f;
 }
 EXPORT_SYMBOL(omap_prcm_get_reset_sources);
 
 /* Resets clock rates and reboots the system. Only called from system.h */
 void omap_prcm_arch_reset(char mode)
 {
+	u32 wkup;
 	omap2_clk_prepare_for_reboot();
-	RM_RSTCTRL_WKUP |= 2;
+	wkup = prm_read_mod_reg(WKUP_MOD, RM_RSTCTRL) | OMAP_RST_DPLL3;
+	prm_write_mod_reg(wkup, WKUP_MOD, RM_RSTCTRL);
 }

index ba26e16..e6616b9 100644
@@ -17,6 +17,9 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
 #define __ARCH_ARM_MACH_OMAP2_CLOCK_H
 
+#include "prm.h"
+#include "cm.h"
+
 static void omap2_sys_clk_recalc(struct clk * clk);
 static void omap2_clksel_recalc(struct clk * clk);
 static void omap2_followparent_recalc(struct clk * clk);

@@ -639,7 +642,7 @@ static struct clk apll96_ck = {
 	.rate		= 96000000,
 	.flags		= CLOCK_IN_OMAP242X |CLOCK_IN_OMAP243X |
 				RATE_FIXED | RATE_PROPAGATES,
-	.enable_reg	= (void __iomem *)&CM_CLKEN_PLL,
+	.enable_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 	.enable_bit	= 0x2,
 	.recalc		= &omap2_propagate_rate,
 };

@@ -650,7 +653,7 @@ static struct clk apll54_ck = {
 	.rate		= 54000000,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				RATE_FIXED | RATE_PROPAGATES,
-	.enable_reg	= (void __iomem *)&CM_CLKEN_PLL,
+	.enable_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 	.enable_bit	= 0x6,
 	.recalc		= &omap2_propagate_rate,
 };

@@ -665,7 +668,7 @@ static struct clk func_54m_ck = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
 	.src_offset	= 5,
-	.enable_reg	= (void __iomem *)&CM_CLKEN_PLL,
+	.enable_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 	.enable_bit	= PARENT_CONTROLS_CLOCK,
 	.recalc		= &omap2_propagate_rate,
 };

@@ -692,7 +695,7 @@ static struct clk func_96m_ck = {
 	.rate		= 96000000,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				RATE_FIXED | RATE_PROPAGATES,
-	.enable_reg	= (void __iomem *)&CM_CLKEN_PLL,
+	.enable_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 	.enable_bit	= PARENT_CONTROLS_CLOCK,
 	.recalc		= &omap2_propagate_rate,
 };

@@ -704,7 +707,7 @@ static struct clk func_48m_ck = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
 	.src_offset	= 3,
-	.enable_reg	= (void __iomem *)&CM_CLKEN_PLL,
+	.enable_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 	.enable_bit	= PARENT_CONTROLS_CLOCK,
 	.recalc		= &omap2_propagate_rate,
 };

@@ -716,7 +719,7 @@ static struct clk func_12m_ck = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				RATE_FIXED | RATE_PROPAGATES,
 	.recalc		= &omap2_propagate_rate,
-	.enable_reg	= (void __iomem *)&CM_CLKEN_PLL,
+	.enable_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 	.enable_bit	= PARENT_CONTROLS_CLOCK,
 };
 

@@ -735,7 +738,7 @@ static struct clk sys_clkout = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
 	.src_offset	= 0,
-	.enable_reg	= (void __iomem *)&PRCM_CLKOUT_CTRL,
+	.enable_reg	= OMAP24XX_PRCM_CLKOUT_CTRL,
 	.enable_bit	= 7,
 	.rate_offset	= 3,
 	.recalc		= &omap2_clksel_recalc,

@@ -749,7 +752,7 @@ static struct clk sys_clkout2 = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
 	.src_offset	= 8,
-	.enable_reg	= (void __iomem *)&PRCM_CLKOUT_CTRL,
+	.enable_reg	= OMAP24XX_PRCM_CLKOUT_CTRL,
 	.enable_bit	= 15,
 	.rate_offset	= 11,
 	.recalc		= &omap2_clksel_recalc,

@@ -759,7 +762,7 @@ static struct clk emul_ck = {
 	.name		= "emul_ck",
 	.parent		= &func_54m_ck,
 	.flags		= CLOCK_IN_OMAP242X,
-	.enable_reg	= (void __iomem *)&PRCM_CLKEMUL_CTRL,
+	.enable_reg	= OMAP24XX_PRCM_CLKEMUL_CTRL,
 	.enable_bit	= 0,
 	.recalc		= &omap2_propagate_rate,
 

@@ -798,7 +801,7 @@ static struct clk iva2_1_fck = {
 				DELAYED_APP | RATE_PROPAGATES |
 				CONFIG_PARTICIPANT,
 	.rate_offset	= 0,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN_DSP,
+	.enable_reg	= OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
 	.enable_bit	= 0,
 	.recalc		= &omap2_clksel_recalc,
 };

@@ -824,7 +827,7 @@ static struct clk dsp_fck = {
 	.flags		= CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
 			DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES,
 	.rate_offset	= 0,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN_DSP,
+	.enable_reg	= OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
 	.enable_bit	= 0,
 	.recalc		= &omap2_clksel_recalc,
 };

@@ -835,7 +838,7 @@ static struct clk dsp_ick = {
 	.flags		= CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
 				DELAYED_APP | CONFIG_PARTICIPANT,
 	.rate_offset	= 5,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN_DSP,
+	.enable_reg	= OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
 	.enable_bit	= 1,		/* for ipi */
 	.recalc		= &omap2_clksel_recalc,
 };

@@ -846,7 +849,7 @@ static struct clk iva1_ifck = {
 	.flags		= CLOCK_IN_OMAP242X | CM_DSP_SEL1 | RATE_CKCTL |
 			CONFIG_PARTICIPANT | RATE_PROPAGATES | DELAYED_APP,
 	.rate_offset	= 8,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN_DSP,
+	.enable_reg	= OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
 	.enable_bit	= 10,
 	.recalc		= &omap2_clksel_recalc,
 };

@@ -856,7 +859,7 @@ static struct clk iva1_mpu_int_ifck = {
 	.name		= "iva1_mpu_int_ifck",
 	.parent		= &iva1_ifck,
 	.flags		= CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN_DSP,
+	.enable_reg	= OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
 	.enable_bit	= 8,
 	.recalc		= &omap2_clksel_recalc,
 };

@@ -897,7 +900,7 @@ static struct clk usb_l4_ick = {	/* FS-USB interface clock */
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP |
 				CONFIG_PARTICIPANT,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN2_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 	.enable_bit	= 0,
 	.rate_offset	= 25,
 	.recalc		= &omap2_clksel_recalc,

@@ -916,7 +919,7 @@ static struct clk ssi_ssr_sst_fck = {
 	.parent		= &core_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN2_CORE,	/* bit 1 */
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),	/* bit 1 */
 	.enable_bit	= 1,
 	.rate_offset	= 20,
 	.recalc		= &omap2_clksel_recalc,

@@ -938,7 +941,7 @@ static struct clk gfx_3d_fck = {
 	.parent		= &core_l3_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				RATE_CKCTL | CM_GFX_SEL1,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN_GFX,
+	.enable_reg	= OMAP_CM_REGADDR(GFX_MOD, OMAP24XX_CM_FCLKEN),
 	.enable_bit	= 2,
 	.rate_offset	= 0,
 	.recalc		= &omap2_clksel_recalc,

@@ -949,7 +952,7 @@ static struct clk gfx_2d_fck = {
 	.parent		= &core_l3_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				RATE_CKCTL | CM_GFX_SEL1,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN_GFX,
+	.enable_reg	= OMAP_CM_REGADDR(GFX_MOD, OMAP24XX_CM_FCLKEN),
 	.enable_bit	= 1,
 	.rate_offset	= 0,
 	.recalc		= &omap2_clksel_recalc,

@@ -960,7 +963,7 @@ static struct clk gfx_ick = {
 	.parent		= &core_l3_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				RATE_CKCTL,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN_GFX,	/* bit 0 */
+	.enable_reg	= OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),	/* bit 0 */
 	.enable_bit	= 0,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -977,7 +980,7 @@ static struct clk mdm_ick = {		/* used both as a ick and fck */
 	.flags		= CLOCK_IN_OMAP243X | RATE_CKCTL | CM_MODEM_SEL1 |
 				DELAYED_APP | CONFIG_PARTICIPANT,
 	.rate_offset	= 0,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN_MDM,
+	.enable_reg	= OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
 	.enable_bit	= 0,
 	.recalc		= &omap2_clksel_recalc,
 };

@@ -987,7 +990,7 @@ static struct clk mdm_osc_ck = {
 	.rate		= 26000000,
 	.parent		= &osc_ck,
 	.flags		= CLOCK_IN_OMAP243X | RATE_FIXED,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN_MDM,
+	.enable_reg	= OMAP_CM_REGADDR(OMAP2430_MDM_MOD, OMAP24XX_CM_FCLKEN),
 	.enable_bit	= 1,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1013,7 +1016,7 @@ static struct clk ssi_l4_ick = {
 	.name		= "ssi_l4_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN2_CORE,	/* bit 1 */
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),	/* bit 1 */
 	.enable_bit	= 1,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1030,7 +1033,7 @@ static struct clk dss_ick = {		/* Enables both L3,L4 ICLK's */
 	.name		= "dss_ick",
 	.parent		= &l4_ck,	/* really both l3 and l4 */
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= 0,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1040,7 +1043,7 @@ static struct clk dss1_fck = {
 	.parent		= &core_ck,		/* Core or sys */
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= 0,
 	.rate_offset	= 8,
 	.src_offset	= 8,

@@ -1053,7 +1056,7 @@ static struct clk dss2_fck = {		/* Alt clk used in power management */
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				RATE_CKCTL | CM_CORE_SEL1 | RATE_FIXED |
 				DELAYED_APP,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= 1,
 	.src_offset	= 13,
 	.recalc		= &omap2_followparent_recalc,

@@ -1065,7 +1068,7 @@ static struct clk dss_54m_fck = {	/* Alt clk used in power management */
 	.rate		= 54000000,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				RATE_FIXED | RATE_PROPAGATES,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= 2,
 	.recalc		= &omap2_propagate_rate,
 };

@@ -1080,7 +1083,7 @@ static struct clk gpt1_ick = {
 	.name		= "gpt1_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN_WKUP,	/* Bit0 */
+	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),	/* Bit0 */
 	.enable_bit	= 0,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1090,7 +1093,7 @@ static struct clk gpt1_fck = {
 	.parent		= &func_32k_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				CM_WKUP_SEL1,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN_WKUP,	/* Bit0 */
+	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),	/* Bit0 */
 	.enable_bit	= 0,
 	.src_offset	= 0,
 	.recalc		= &omap2_followparent_recalc,

@@ -1100,7 +1103,7 @@ static struct clk gpt2_ick = {
 	.name		= "gpt2_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,	/* Bit4 */
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),	/* Bit4 */
 	.enable_bit	= 4,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1110,7 +1113,7 @@ static struct clk gpt2_fck = {
 	.parent		= &func_32k_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				CM_CORE_SEL2,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= 4,
 	.src_offset	= 2,
 	.recalc		= &omap2_followparent_recalc,

@@ -1120,7 +1123,7 @@ static struct clk gpt3_ick = {
 	.name		= "gpt3_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,	/* Bit5 */
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),	/* Bit5 */
 	.enable_bit	= 5,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1130,7 +1133,7 @@ static struct clk gpt3_fck = {
 	.parent		= &func_32k_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				CM_CORE_SEL2,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= 5,
 	.src_offset	= 4,
 	.recalc		= &omap2_followparent_recalc,

@@ -1140,7 +1143,7 @@ static struct clk gpt4_ick = {
 	.name		= "gpt4_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,	/* Bit6 */
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),	/* Bit6 */
 	.enable_bit	= 6,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1150,7 +1153,7 @@ static struct clk gpt4_fck = {
 	.parent		= &func_32k_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				CM_CORE_SEL2,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= 6,
 	.src_offset	= 6,
 	.recalc		= &omap2_followparent_recalc,

@@ -1160,7 +1163,7 @@ static struct clk gpt5_ick = {
 	.name		= "gpt5_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,	 /* Bit7 */
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),	 /* Bit7 */
 	.enable_bit	= 7,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1170,7 +1173,7 @@ static struct clk gpt5_fck = {
 	.parent		= &func_32k_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				CM_CORE_SEL2,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= 7,
 	.src_offset	= 8,
 	.recalc		= &omap2_followparent_recalc,

@@ -1181,7 +1184,7 @@ static struct clk gpt6_ick = {
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
 	.enable_bit	= 8,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,	 /* bit8 */
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),	 /* bit8 */
 	.recalc		= &omap2_followparent_recalc,
 };
 

@@ -1190,7 +1193,7 @@ static struct clk gpt6_fck = {
 	.parent		= &func_32k_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				CM_CORE_SEL2,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= 8,
 	.src_offset	= 10,
 	.recalc		= &omap2_followparent_recalc,

@@ -1200,7 +1203,7 @@ static struct clk gpt7_ick = {
 	.name		= "gpt7_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,	 /* bit9 */
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),	 /* bit9 */
 	.enable_bit	= 9,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1210,7 +1213,7 @@ static struct clk gpt7_fck = {
 	.parent		= &func_32k_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				CM_CORE_SEL2,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= 9,
 	.src_offset	= 12,
 	.recalc		= &omap2_followparent_recalc,

@@ -1220,7 +1223,7 @@ static struct clk gpt8_ick = {
 	.name		= "gpt8_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,	 /* bit10 */
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),	 /* bit10 */
 	.enable_bit	= 10,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1230,7 +1233,7 @@ static struct clk gpt8_fck = {
 	.parent		= &func_32k_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				CM_CORE_SEL2,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= 10,
 	.src_offset	= 14,
 	.recalc		= &omap2_followparent_recalc,

@@ -1240,7 +1243,7 @@ static struct clk gpt9_ick = {
 	.name		= "gpt9_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= 11,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1250,7 +1253,7 @@ static struct clk gpt9_fck = {
 	.parent		= &func_32k_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 					CM_CORE_SEL2,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= 11,
 	.src_offset	= 16,
 	.recalc		= &omap2_followparent_recalc,

@@ -1260,7 +1263,7 @@ static struct clk gpt10_ick = {
 	.name		= "gpt10_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= 12,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1270,7 +1273,7 @@ static struct clk gpt10_fck = {
 	.parent		= &func_32k_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 					CM_CORE_SEL2,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= 12,
 	.src_offset	= 18,
 	.recalc		= &omap2_followparent_recalc,

@@ -1280,7 +1283,7 @@ static struct clk gpt11_ick = {
 	.name		= "gpt11_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= 13,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1290,7 +1293,7 @@ static struct clk gpt11_fck = {
 	.parent		= &func_32k_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 					CM_CORE_SEL2,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= 13,
 	.src_offset	= 20,
 	.recalc		= &omap2_followparent_recalc,

@@ -1300,7 +1303,7 @@ static struct clk gpt12_ick = {
 	.name		= "gpt12_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,	 /* bit14 */
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),	 /* bit14 */
 	.enable_bit	= 14,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1310,7 +1313,7 @@ static struct clk gpt12_fck = {
 	.parent		= &func_32k_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 					CM_CORE_SEL2,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= 14,
 	.src_offset	= 22,
 	.recalc		= &omap2_followparent_recalc,

@@ -1320,7 +1323,7 @@ static struct clk mcbsp1_ick = {
 	.name		= "mcbsp1_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,	 /* bit16 */
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),	 /* bit16 */
 	.enable_bit	= 15,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1329,7 +1332,7 @@ static struct clk mcbsp1_fck = {
 	.name		= "mcbsp1_fck",
 	.parent		= &func_96m_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= 15,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1338,7 +1341,7 @@ static struct clk mcbsp2_ick = {
 	.name		= "mcbsp2_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= 16,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1347,7 +1350,7 @@ static struct clk mcbsp2_fck = {
 	.name		= "mcbsp2_fck",
 	.parent		= &func_96m_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= 16,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1356,7 +1359,7 @@ static struct clk mcbsp3_ick = {
 	.name		= "mcbsp3_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN2_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 	.enable_bit	= 3,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1365,7 +1368,7 @@ static struct clk mcbsp3_fck = {
 	.name		= "mcbsp3_fck",
 	.parent		= &func_96m_ck,
 	.flags		= CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN2_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
 	.enable_bit	= 3,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1374,7 +1377,7 @@ static struct clk mcbsp4_ick = {
 	.name		= "mcbsp4_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN2_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 	.enable_bit	= 4,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1383,7 +1386,7 @@ static struct clk mcbsp4_fck = {
 	.name		= "mcbsp4_fck",
 	.parent		= &func_96m_ck,
 	.flags		= CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN2_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
 	.enable_bit	= 4,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1392,7 +1395,7 @@ static struct clk mcbsp5_ick = {
 	.name		= "mcbsp5_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN2_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 	.enable_bit	= 5,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1401,7 +1404,7 @@ static struct clk mcbsp5_fck = {
 	.name		= "mcbsp5_fck",
 	.parent		= &func_96m_ck,
 	.flags		= CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN2_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
 	.enable_bit	= 5,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1411,7 +1414,7 @@ static struct clk mcspi1_ick = {
 	.id		= 1,
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= 17,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1421,7 +1424,7 @@ static struct clk mcspi1_fck = {
 	.id		= 1,
 	.parent		= &func_48m_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= 17,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1431,7 +1434,7 @@ static struct clk mcspi2_ick = {
 	.id		= 2,
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= 18,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1441,7 +1444,7 @@ static struct clk mcspi2_fck = {
 	.id		= 2,
 	.parent		= &func_48m_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= 18,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1451,7 +1454,7 @@ static struct clk mcspi3_ick = {
 	.id		= 3,
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN2_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 	.enable_bit	= 9,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1461,7 +1464,7 @@ static struct clk mcspi3_fck = {
 	.id		= 3,
 	.parent		= &func_48m_ck,
 	.flags		= CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN2_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
 	.enable_bit	= 9,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1470,7 +1473,7 @@ static struct clk uart1_ick = {
 	.name		= "uart1_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= 21,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1479,7 +1482,7 @@ static struct clk uart1_fck = {
 	.name		= "uart1_fck",
 	.parent		= &func_48m_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= 21,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1488,7 +1491,7 @@ static struct clk uart2_ick = {
 	.name		= "uart2_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= 22,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1497,7 +1500,7 @@ static struct clk uart2_fck = {
 	.name		= "uart2_fck",
 	.parent		= &func_48m_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= 22,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1506,7 +1509,7 @@ static struct clk uart3_ick = {
 	.name		= "uart3_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN2_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 	.enable_bit	= 2,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1515,7 +1518,7 @@ static struct clk uart3_fck = {
 	.name		= "uart3_fck",
 	.parent		= &func_48m_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN2_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
 	.enable_bit	= 2,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1524,7 +1527,7 @@ static struct clk gpios_ick = {
 	.name		= "gpios_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN_WKUP,
+	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
 	.enable_bit	= 2,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1533,7 +1536,7 @@ static struct clk gpios_fck = {
 	.name		= "gpios_fck",
 	.parent		= &func_32k_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN_WKUP,
+	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),
 	.enable_bit	= 2,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1542,7 +1545,7 @@ static struct clk mpu_wdt_ick = {
 	.name		= "mpu_wdt_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN_WKUP,
+	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
 	.enable_bit	= 3,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1551,7 +1554,7 @@ static struct clk mpu_wdt_fck = {
 	.name		= "mpu_wdt_fck",
 	.parent		= &func_32k_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN_WKUP,
+	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),
 	.enable_bit	= 3,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1560,7 +1563,7 @@ static struct clk sync_32k_ick = {
 	.name		= "sync_32k_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN_WKUP,
+	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
 	.enable_bit	= 1,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1568,7 +1571,7 @@ static struct clk wdt1_ick = {
 	.name		= "wdt1_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN_WKUP,
+	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
 	.enable_bit	= 4,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1576,7 +1579,7 @@ static struct clk omapctrl_ick = {
 	.name		= "omapctrl_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN_WKUP,
+	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
 	.enable_bit	= 5,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1584,7 +1587,7 @@ static struct clk icr_ick = {
 	.name		= "icr_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN_WKUP,
+	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
 	.enable_bit	= 6,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1593,7 +1596,7 @@ static struct clk cam_ick = {
 	.name		= "cam_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= 31,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1602,7 +1605,7 @@ static struct clk cam_fck = {
 	.name		= "cam_fck",
 	.parent		= &func_96m_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= 31,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1611,7 +1614,7 @@ static struct clk mailboxes_ick = {
 	.name		= "mailboxes_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= 30,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1620,7 +1623,7 @@ static struct clk wdt4_ick = {
 	.name		= "wdt4_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= 29,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1629,7 +1632,7 @@ static struct clk wdt4_fck = {
 	.name		= "wdt4_fck",
 	.parent		= &func_32k_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= 29,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1638,7 +1641,7 @@ static struct clk wdt3_ick = {
 	.name		= "wdt3_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP242X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= 28,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1647,7 +1650,7 @@ static struct clk wdt3_fck = {
 	.name		= "wdt3_fck",
 	.parent		= &func_32k_ck,
 	.flags		= CLOCK_IN_OMAP242X,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= 28,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1656,7 +1659,7 @@ static struct clk mspro_ick = {
 	.name		= "mspro_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= 27,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1665,7 +1668,7 @@ static struct clk mspro_fck = {
 	.name		= "mspro_fck",
 	.parent		= &func_96m_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= 27,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1674,7 +1677,7 @@ static struct clk mmc_ick = {
 	.name		= "mmc_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP242X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= 26,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1683,7 +1686,7 @@ static struct clk mmc_fck = {
 	.name		= "mmc_fck",
 	.parent		= &func_96m_ck,
 	.flags		= CLOCK_IN_OMAP242X,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= 26,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1692,7 +1695,7 @@ static struct clk fac_ick = {
 	.name		= "fac_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= 25,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1701,7 +1704,7 @@ static struct clk fac_fck = {
 	.name		= "fac_fck",
 	.parent		= &func_12m_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= 25,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1710,7 +1713,7 @@ static struct clk eac_ick = {
 	.name		= "eac_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP242X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= 24,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1719,7 +1722,7 @@ static struct clk eac_fck = {
 	.name		= "eac_fck",
 	.parent		= &func_96m_ck,
 	.flags		= CLOCK_IN_OMAP242X,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= 24,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1728,7 +1731,7 @@ static struct clk hdq_ick = {
 	.name		= "hdq_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= 23,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1737,7 +1740,7 @@ static struct clk hdq_fck = {
 	.name		= "hdq_fck",
 	.parent		= &func_12m_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= 23,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1747,7 +1750,7 @@ static struct clk i2c2_ick = {
 	.id		= 2,
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= 20,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1757,7 +1760,7 @@ static struct clk i2c2_fck = {
 	.id		= 2,
 	.parent		= &func_12m_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= 20,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1767,7 +1770,7 @@ static struct clk i2chs2_fck = {
 	.id		= 2,
 	.parent		= &func_96m_ck,
 	.flags		= CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN2_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
 	.enable_bit	= 20,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1777,7 +1780,7 @@ static struct clk i2c1_ick = {
 	.id		= 1,
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= 19,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1787,7 +1790,7 @@ static struct clk i2c1_fck = {
 	.id		= 1,
 	.parent		= &func_12m_ck,
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= 19,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1797,7 +1800,7 @@ static struct clk i2chs1_fck = {
 	.id		= 1,
 	.parent		= &func_96m_ck,
 	.flags		= CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN2_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
 	.enable_bit	= 19,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1806,7 +1809,7 @@ static struct clk vlynq_ick = {
 	.name		= "vlynq_ick",
 	.parent		= &core_l3_ck,
 	.flags		= CLOCK_IN_OMAP242X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 	.enable_bit	= 3,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1815,7 +1818,7 @@ static struct clk vlynq_fck = {
 	.name		= "vlynq_fck",
 	.parent		= &func_96m_ck,
 	.flags		= CLOCK_IN_OMAP242X  | RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN1_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= 3,
 	.src_offset	= 15,
 	.recalc		= &omap2_followparent_recalc,

@@ -1825,7 +1828,7 @@ static struct clk sdrc_ick = {
 	.name		= "sdrc_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN3_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP2430_CM_ICLKEN3),
 	.enable_bit	= 2,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1834,7 +1837,7 @@ static struct clk des_ick = {
 	.name		= "des_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN4_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
 	.enable_bit	= 0,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1843,7 +1846,7 @@ static struct clk sha_ick = {
 	.name		= "sha_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN4_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
 	.enable_bit	= 1,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1852,7 +1855,7 @@ static struct clk rng_ick = {
 	.name		= "rng_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN4_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
 	.enable_bit	= 2,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1861,7 +1864,7 @@ static struct clk aes_ick = {
 	.name		= "aes_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN4_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
 	.enable_bit	= 3,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1870,7 +1873,7 @@ static struct clk pka_ick = {
 	.name		= "pka_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN4_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
 	.enable_bit	= 4,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1879,7 +1882,7 @@ static struct clk usb_fck = {
 	.name		= "usb_fck",
 	.parent		= &func_48m_ck,
 	.flags		= CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN2_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
 	.enable_bit	= 0,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1888,7 +1891,7 @@ static struct clk usbhs_ick = {
 	.name		= "usbhs_ick",
 	.parent		= &core_l3_ck,
 	.flags		= CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN2_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 	.enable_bit	= 6,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1897,7 +1900,7 @@ static struct clk mmchs1_ick = {
 	.name		= "mmchs1_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN2_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 	.enable_bit	= 7,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1906,7 +1909,7 @@ static struct clk mmchs1_fck = {
 	.name		= "mmchs1_fck",
 	.parent		= &func_96m_ck,
 	.flags		= CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN2_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
 	.enable_bit	= 7,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1915,7 +1918,7 @@ static struct clk mmchs2_ick = {
 	.name		= "mmchs2_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN2_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 	.enable_bit	= 8,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1924,7 +1927,7 @@ static struct clk mmchs2_fck = {
 	.name		= "mmchs2_fck",
 	.parent		= &func_96m_ck,
 	.flags		= CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN2_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
 	.enable_bit	= 8,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1933,7 +1936,7 @@ static struct clk gpio5_ick = {
 	.name		= "gpio5_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN2_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 	.enable_bit	= 10,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1942,7 +1945,7 @@ static struct clk gpio5_fck = {
 	.name		= "gpio5_fck",
 	.parent		= &func_32k_ck,
 	.flags		= CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN2_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
 	.enable_bit	= 10,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1951,7 +1954,7 @@ static struct clk mdm_intc_ick = {
 	.name		= "mdm_intc_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_ICLKEN2_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 	.enable_bit	= 11,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1960,7 +1963,7 @@ static struct clk mmchsdb1_fck = {
 	.name		= "mmchsdb1_fck",
 	.parent		= &func_32k_ck,
 	.flags		= CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN2_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
 	.enable_bit	= 16,
 	.recalc		= &omap2_followparent_recalc,
 };

@@ -1969,7 +1972,7 @@ static struct clk mmchsdb2_fck = {
 	.name		= "mmchsdb2_fck",
 	.parent		= &func_32k_ck,
 	.flags		= CLOCK_IN_OMAP243X,
-	.enable_reg	= (void __iomem *)&CM_FCLKEN2_CORE,
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
 	.enable_bit	= 17,
 	.recalc		= &omap2_followparent_recalc,
 };

index e6616b9..78da556 100644
@@ -19,6 +19,8 @@
 
 #include "prm.h"
 #include "cm.h"
+#include "prm_regbits_24xx.h"
+#include "cm_regbits_24xx.h"
 
 static void omap2_sys_clk_recalc(struct clk * clk);
 static void omap2_clksel_recalc(struct clk * clk);

@@ -643,7 +645,7 @@ static struct clk apll96_ck = {
 	.flags		= CLOCK_IN_OMAP242X |CLOCK_IN_OMAP243X |
 				RATE_FIXED | RATE_PROPAGATES,
 	.enable_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
-	.enable_bit	= 0x2,
+	.enable_bit	= OMAP24XX_EN_96M_PLL_SHIFT,
 	.recalc		= &omap2_propagate_rate,
 };
 

@@ -654,7 +656,7 @@ static struct clk apll54_ck = {
 	.flags		= CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
 				RATE_FIXED | RATE_PROPAGATES,
 	.enable_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
-	.enable_bit	= 0x6,
+	.enable_bit	= OMAP24XX_EN_54M_PLL_SHIFT,
 	.recalc		= &omap2_propagate_rate,
 };
 

@@ -739,7 +741,7 @@ static struct clk sys_clkout = {
 				CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
 	.src_offset	= 0,
 	.enable_reg	= OMAP24XX_PRCM_CLKOUT_CTRL,
-	.enable_bit	= 7,
+	.enable_bit	= OMAP24XX_CLKOUT_EN_SHIFT,
 	.rate_offset	= 3,
 	.recalc		= &omap2_clksel_recalc,
 };