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fix iommu sg list merge problem

PATCH In review FUJITA Tomonori 3 participants 5 messages Sep 26, 2007 SCSI

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#0 lore raw

cover fix iommu sg list merge problem

iommu code merges sg lists without considering lld's restrictions so some llds need a workaround to split sg lists again. This patchset fixes iommu to handle lld's max segment size limit properly.

The problem is that iommu code can't access to the restrictions because they are in request_queue. iommu code can access to only device structure. I chose the simplest approach, adding max_segment_size to device structure.

We could remove the lld restrictions in request_queue strucutre and have a new strucutre (something like struct io_restrictions). Then somehow we could link the new structure with request_queue and device strucutres. But iommu needs only max_segment_size and seg_boundary_mask, so the simplest approach is not so bad, I think.

scsi_add_host sets shost_gendev.parent->max_segment_size for iommu code (copied form shost->dma_max_segment_size).

This patchset includes only the x86_64 iommu patch but my git tree includes x86_64, ppc, ia64, parisc, and alpha patches. As far as I know, thye are all the iommu code that merges sg lists. The iommu patchse are only compile tested.

git://git.kernel.org/pub/scm/linux/kernel/git/tomo/linux-2.6-bidi.git iommu

3 llds, aacraid, scsi_debug, and sata_inic162x sets shost->dma_max_segment_size in slave_configure hook. But dma_max_segment_size is a lld restriction. I adds dma_max_segment_size to scsi_host_template and scsi_host. llds specify dma_max_segment_size in scsi_host_template, scsi-ml sets dma_max_segment_size in devices and call blk_queue_max_segment_size. This patchset includes only the sata_inic162x patch but all the patches for llds, aacraid and scsi_debug are in the git tree.

#1 lore raw
Quoted 3 lines · FUJITA Tomonori

iommu code merges sg lists without considering lld's restrictions so some llds need a workaround to split sg lists again. This patchset fixes iommu to handle lld's max segment size limit properly.

The patches look reasonable to me.

Quoted 1 line

This patchset includes only the x86_64 iommu patch

There are multiple x86-64 IOMMUs, but only GART is in-tree and supports merging.

Quoted 6 lines

but my git tree includes x86_64, ppc, ia64, parisc, and alpha patches. As far as I know, thye are all the iommu code that merges sg lists. The iommu patchse are only compile tested.

git://git.kernel.org/pub/scm/linux/kernel/git/tomo/linux-2.6-bidi.git iommu

Do you think it will be possible to abstract the merging code into common code, rather than duplicating it for every IOMMU?

Cheers,
Muli

#2 lore raw
Quoted 18 lines · On Wed, 26 Sep 2007 12:02:21 +0200 Muli Ben-Yehuda <[email protected]> wrote:
Quoted 3 lines · FUJITA Tomonori

iommu code merges sg lists without considering lld's restrictions so some llds need a workaround to split sg lists again. This patchset fixes iommu to handle lld's max segment size limit properly.

The patches look reasonable to me.

Quoted 1 line

This patchset includes only the x86_64 iommu patch

There are multiple x86-64 IOMMUs, but only GART is in-tree and supports merging.

Quoted 5 lines

but my git tree includes x86_64, ppc, ia64, parisc, and alpha patches. As far as I know, thye are all the iommu code that merges sg lists. The iommu patchse are only compile tested.

Quoted 4 lines
Quoted 1 line

git://git.kernel.org/pub/scm/linux/kernel/git/tomo/linux-2.6-bidi.git iommu

Do you think it will be possible to abstract the merging code into common code, rather than duplicating it for every IOMMU?

Yeah, I thought about it and it's possible (but not so easy). parisc has IOMMU merging helper code and two parisc IOMMUs use it. ia64 sba_iommu is almost identical to parisc code. x86_64 gart, power, and alpha do in their own way. But I think that we can merging helper code useful for all.

I'll see what we can have after fixing the mering problem.

#3 lore raw
Quoted 5 lines · FUJITA Tomonori

Yeah, I thought about it and it's possible (but not so easy). parisc has IOMMU merging helper code and two parisc IOMMUs use it. ia64 sba_iommu is almost identical to parisc code. x86_64 gart, power, and alpha do in their own way. But I think that we can merging helper code useful for all.

Er ... it should be identical ... the SBA iommu is the same ... I thought we moved the common code out to a shared file.

James

#4 lore raw
Quoted 9 lines · On Wed, 26 Sep 2007 09:38:32 -0500 James Bottomley…
Quoted 5 lines · FUJITA Tomonori

Yeah, I thought about it and it's possible (but not so easy). parisc has IOMMU merging helper code and two parisc IOMMUs use it. ia64 sba_iommu is almost identical to parisc code. x86_64 gart, power, and alpha do in their own way. But I think that we can merging helper code useful for all.

Er ... it should be identical ... the SBA iommu is the same ... I thought we moved the common code out to a shared file.

2.6.23-rc8-mm1 has two iommu_coalesce_chunks in drivers/iommu-helpers.h and arch/ioa64/hp/common/sb_iommu.c

iommu_coalesce_chunks are almost same. parisc's iommu_coalesce_chunks is simpler a bit.