avr32 uses gpio_chip
PATCH 2/3 avr32 uses gpio_chip
Teach AVR32 to use the "GPIO Library" when exposing its GPIOs, so that signals on external chips (like GPIO expanders) can easily be used.
This mostly reorganizes some existing logic, with two minor changes in behavior:
- The PSR registers are used instead of the previous "gpio_mask" values, matching AT91 behavior and removing some duplication between that role and that of "pinmux_mask".
- NR_IRQs grew to acommodate a bank of external GPIOs. Eventually this number should probably become a config option.
There's a debugfs dump of status for the built-in GPIOs, showing which pins have deglitching, pullups, or open drain drive enabled, as well as the ID string used when requesting each IRQ.
--- arch/avr32/Kconfig | 1 arch/avr32/mach-at32ap/pio.c | 169 +++++++++++++++-------------- arch/avr32/mach-at32ap/pio.h | 2 include/asm-avr32/arch-at32ap/at32ap7000.h | 2 include/asm-avr32/arch-at32ap/gpio.h | 34 ++++- include/asm-avr32/arch-at32ap/irq.h | 4 6 files changed, 118 insertions(+), 94 deletions(-)
arch/avr32/Kconfig +1 -0
@@ -86,6 +86,7 @@ config PLATFORM_AT32AP select SUBARCH_AVR32B select MMU select PERFORMANCE_COUNTERS + select GPIO_LIB choice prompt "AVR32 CPU type"
arch/avr32/mach-at32ap/pio.c +89 -80
241 lines not on this page · raw message
arch/avr32/mach-at32ap/pio.h +1 -1
@@ -19,7 +19,7 @@#define PIO_OSR 0x0018#define PIO_IFER 0x0020#define PIO_IFDR 0x0024 -#define PIO_ISFR 0x0028 +#define PIO_IFSR 0x0028#define PIO_SODR 0x0030#define PIO_CODR 0x0034#define PIO_ODSR 0x0038
include/asm-avr32/arch-at32ap/at32ap7000.h +0 -2
@@ -13,8 +13,6 @@#define GPIO_PERIPH_A 0#define GPIO_PERIPH_B 1 -#define NR_GPIO_CONTROLLERS 4 -/* * Pin numbers identifying specific GPIO pins on the chip. They can * also be converted to IRQ numbers by passing them through
include/asm-avr32/arch-at32ap/gpio.h +25 -9
@@ -5,20 +5,36 @@#include <asm/irq.h> -/* Arch-neutral GPIO API */ -int __must_check gpio_request (unsigned int gpio,const char *label); -void gpio_free (unsigned int gpio); +/* Some GPIO chips can manage IRQs; some can't. The exact numbers can +* be changed if needed, but for the moment they're not configurable. +*/ +#define ARCH_NR_GPIOS (NR_GPIO_IRQS + 2 * ARCH_GPIOS_PER_CHIP) -int gpio_direction_input (unsigned int gpio); -int gpio_direction_output (unsigned int gpio,int value); -int gpio_get_value (unsigned int gpio); -void gpio_set_value (unsigned int gpio,int value); -#include <asm-generic/gpio.h> /* cansleep wrappers */ +/* Arch-neutral GPIO API, supporting both "native" and external GPIOs. */ +#include <asm-generic/gpio.h> + +static inline int gpio_get_value (unsigned int gpio) +{ +return __gpio_get_value (gpio); +} + +static inline void gpio_set_value (unsigned int gpio,int value) +{ +__gpio_set_value (gpio, value); +} + +static inline int gpio_cansleep (unsigned int gpio) +{ +return __gpio_cansleep (gpio); +} +static inline int gpio_to_irq (unsigned int gpio) { -return gpio +GPIO_IRQ_BASE ; +if (gpio <NR_GPIO_IRQS ) +return gpio +GPIO_IRQ_BASE ; +return -EINVAL ; }static inline int irq_to_gpio (unsigned int irq)
include/asm-avr32/arch-at32ap/irq.h +2 -2
@@ -3,11 +3,11 @@#define EIM_IRQ_BASE NR_INTERNAL_IRQS#define NR_EIM_IRQS 32 -#define AT32_EXTINT (n) (EIM_IRQ_BASE + (n))#define GPIO_IRQ_BASE (EIM_IRQ_BASE + NR_EIM_IRQS) -#define NR_GPIO_IRQS (5 * 32) +#define NR_GPIO_CTLR (5 /*internal*/ + 1 /*external*/) +#define NR_GPIO_IRQS (NR_GPIO_CTLR * 32)#define NR_IRQS (GPIO_IRQ_BASE + NR_GPIO_IRQS)