Runtime constants: define (some) OMAP address bases at runtime rather than compile time for multiboot

Index: linux-omap/arch/arm/mach-omap2/board-n800.c
===================================================================
@@ -479,6 +479,7 @@
 	omap_board_config = n800_config;
 	omap_board_config_size = ARRAY_SIZE(n800_config);
 
+	omap2_set_globals_242x();
 	omap2_map_common_io();
 }
 

Index: linux-omap/include/asm-arm/arch-omap/omap24xx.h
===================================================================
@@ -85,7 +85,6 @@
 #define OMAP2_PRM_BASE		OMAP2420_PRM_BASE
 #define OMAP2_SDRC_BASE		OMAP2420_SDRC_BASE
 #define OMAP2_SMS_BASE		OMAP2420_SMS_BASE
-#define OMAP2_L4_BASE		L4_24XX_BASE
 #define OMAP2_VA_IC_BASE	IO_ADDRESS(OMAP24XX_IC_BASE)
 #define OMAP2_CTRL_BASE		OMAP2420_CTRL_BASE
 

@@ -97,7 +96,6 @@
 #define OMAP2_PRM_BASE		OMAP2430_PRM_BASE
 #define OMAP2_SDRC_BASE		OMAP243X_SDRC_BASE
 #define OMAP2_SMS_BASE		OMAP243X_SMS_BASE
-#define OMAP2_L4_BASE		L4_24XX_BASE
 #define OMAP2_VA_IC_BASE	IO_ADDRESS(OMAP24XX_IC_BASE)
 #define OMAP2_CTRL_BASE		OMAP243X_CTRL_BASE
 

Index: linux-omap/include/asm-arm/arch-omap/omap34xx.h
===================================================================
@@ -66,7 +66,6 @@
 #define OMAP2_PRM_BASE			OMAP3430_PRM_BASE
 #define OMAP2_SDRC_BASE			OMAP343X_SDRC_BASE
 #define OMAP2_SMS_BASE			OMAP343X_SMS_BASE
-#define OMAP2_L4_BASE			L4_34XX_BASE
 #define OMAP2_VA_IC_BASE		IO_ADDRESS(OMAP34XX_IC_BASE)
 #define OMAP2_CTRL_BASE			OMAP3430_CTRL_BASE
 #define OMAP34XX_CONTROL_DEVCONF0	(L4_34XX_BASE + 0x2274)

Index: linux-omap/arch/arm/mach-omap2/board-2430sdp.c
===================================================================
@@ -392,6 +392,7 @@
 
 static void __init omap_2430sdp_map_io(void)
 {
+	omap2_set_globals_243x();
 	omap2_map_common_io();
 }
 

Index: linux-omap/arch/arm/mach-omap2/board-3430sdp.c
===================================================================
@@ -328,6 +328,7 @@
 
 static void __init omap_3430sdp_map_io(void)
 {
+	omap2_set_globals_343x();
 	omap2_map_common_io();
 }
 arch_initcall(omap3430_i2c_init);

Index: linux-omap/arch/arm/mach-omap2/board-apollon.c
===================================================================
@@ -390,6 +390,7 @@
 
 static void __init omap_apollon_map_io(void)
 {
+	omap2_set_globals_242x();
 	omap2_map_common_io();
 }
 

Index: linux-omap/arch/arm/mach-omap2/board-generic.c
===================================================================
@@ -67,6 +67,7 @@
 
 static void __init omap_generic_map_io(void)
 {
+	omap2_set_globals_242x(); /* should be 242x, 243x, or 343x */
 	omap2_map_common_io();
 }
 

Index: linux-omap/arch/arm/mach-omap2/board-h4.c
===================================================================
@@ -741,6 +741,7 @@
 
 static void __init omap_h4_map_io(void)
 {
+	omap2_set_globals_242x();
 	omap2_map_common_io();
 }
 

Index: linux-omap/arch/arm/mach-omap2/board-2430osk.c
===================================================================
@@ -125,6 +125,7 @@
 
 static void __init omap_2430osk_map_io(void)
 {
+	omap2_set_globals_243x();
 	omap2_map_common_io();
 }
 

Index: linux-omap/arch/arm/plat-omap/common.c
===================================================================
@@ -230,3 +230,24 @@
 arch_initcall(omap_init_clocksource_32k);
 
 #endif	/* TIMER_32K_SYNCHRONIZED */
+
+/* Global address base setup code */
+
+#if defined(CONFIG_ARCH_OMAP2420)
+void __init omap2_set_globals_242x(void)
+{
+}
+#endif
+
+#if defined(CONFIG_ARCH_OMAP2430)
+void __init omap2_set_globals_243x(void)
+{
+}
+#endif
+
+#if defined(CONFIG_ARCH_OMAP3430)
+void __init omap2_set_globals_343x(void)
+{
+}
+#endif
+

Index: linux-omap/include/asm-arm/arch-omap/common.h
===================================================================
@@ -40,4 +40,8 @@
 				 struct i2c_board_info const *info,
 				 unsigned len);
 
+void omap2_set_globals_242x(void);
+void omap2_set_globals_243x(void);
+void omap2_set_globals_343x(void);
+
 #endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */

Index: linux-omap/arch/arm/mach-omap2/sdrc.h
===================================================================
@@ -13,23 +13,14 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+#undef DEBUG
 
 #include <linux/kernel.h>
-#include <asm/arch/io.h>
+#include <asm/arch/sdrc.h>
 
+extern unsigned long omap2_sdrc_base;
 
-#define OMAP_SDRC_REGADDR(reg)	(void __iomem *)IO_ADDRESS(OMAP2_SDRC_BASE + reg)
-
-/* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
-
-#define SDRC_SYSCONFIG		0x010
-#define SDRC_DLLA_CTRL		0x060
-#define SDRC_DLLA_STATUS	0x064
-#define SDRC_DLLB_CTRL		0x068
-#define SDRC_DLLB_STATUS	0x06C
-#define SDRC_POWER		0x070
-#define SDRC_MR_0		0x084
-#define SDRC_RFR_CTRL_0		0x0a4
+#define OMAP_SDRC_REGADDR(reg)	(void __iomem *)IO_ADDRESS(omap2_sdrc_base + reg)
 
 /* SDRC global register get/set */
 

@@ -46,35 +37,5 @@
 	return __raw_readl(OMAP_SDRC_REGADDR(reg));
 }
 
-/*
- * These values represent the number of memory clock cycles between
- * autorefresh initiation.  They assume 1 refresh per 64 ms (JEDEC), 8192
- * rows per device, and include a subtraction of a 50 cycle window in the
- * event that the autorefresh command is delayed due to other SDRC activity.
- * The '| 1' sets the ARE field to send one autorefresh when the autorefresh
- * counter reaches 0.
- *
- * These represent optimal values for common parts, it won't work for all.
- * As long as you scale down, most parameters are still work, they just
- * become sub-optimal. The RFR value goes in the opposite direction. If you
- * don't adjust it down as your clock period increases the refresh interval
- * will not be met. Setting all parameters for complete worst case may work,
- * but may cut memory performance by 2x. Due to errata the DLLs need to be
- * unlocked and their value needs run time calibration.	A dynamic call is
- * need for that as no single right value exists acorss production samples.
- *
- * Only the FULL speed values are given. Current code is such that rate
- * changes must be made at DPLLoutx2. The actual value adjustment for low
- * frequency operation will be handled by omap_set_performance()
- *
- * By having the boot loader boot up in the fastest L4 speed available likely
- * will result in something which you can switch between.
- */
-#define SDRC_RFR_CTRL_165MHz	(0x00044c00 | 1)
-#define SDRC_RFR_CTRL_133MHz	(0x0003de00 | 1)
-#define SDRC_RFR_CTRL_100MHz	(0x0002da01 | 1)
-#define SDRC_RFR_CTRL_110MHz	(0x0002da01 | 1) /* Need to calc */
-#define SDRC_RFR_CTRL_BYPASS	(0x00005000 | 1) /* Need to calc */
-
 
 #endif

Index: linux-omap/arch/arm/mach-omap2/memory.c
===================================================================
@@ -34,6 +34,8 @@
 
 #define SMS_SYSCONFIG			(OMAP2_SMS_BASE + 0x010)
 
+unsigned long omap2_sdrc_base;
+
 static struct memory_timings mem_timings;
 static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;
 

Index: linux-omap/include/asm-arm/arch-omap/omap24xx.h
===================================================================
@@ -83,7 +83,6 @@
 #define OMAP2_PRCM_BASE		OMAP2420_PRCM_BASE
 #define OMAP2_CM_BASE		OMAP2420_CM_BASE
 #define OMAP2_PRM_BASE		OMAP2420_PRM_BASE
-#define OMAP2_SDRC_BASE		OMAP2420_SDRC_BASE
 #define OMAP2_SMS_BASE		OMAP2420_SMS_BASE
 #define OMAP2_VA_IC_BASE	IO_ADDRESS(OMAP24XX_IC_BASE)
 #define OMAP2_CTRL_BASE		OMAP2420_CTRL_BASE

@@ -94,7 +93,6 @@
 #define OMAP2_PRCM_BASE		OMAP2430_PRCM_BASE
 #define OMAP2_CM_BASE		OMAP2430_CM_BASE
 #define OMAP2_PRM_BASE		OMAP2430_PRM_BASE
-#define OMAP2_SDRC_BASE		OMAP243X_SDRC_BASE
 #define OMAP2_SMS_BASE		OMAP243X_SMS_BASE
 #define OMAP2_VA_IC_BASE	IO_ADDRESS(OMAP24XX_IC_BASE)
 #define OMAP2_CTRL_BASE		OMAP243X_CTRL_BASE

Index: linux-omap/include/asm-arm/arch-omap/omap34xx.h
===================================================================
@@ -64,7 +64,6 @@
 #define OMAP2_32KSYNCT_BASE		OMAP3430_32KSYNCT_BASE
 #define OMAP2_CM_BASE			OMAP3430_CM_BASE
 #define OMAP2_PRM_BASE			OMAP3430_PRM_BASE
-#define OMAP2_SDRC_BASE			OMAP343X_SDRC_BASE
 #define OMAP2_SMS_BASE			OMAP343X_SMS_BASE
 #define OMAP2_VA_IC_BASE		IO_ADDRESS(OMAP34XX_IC_BASE)
 #define OMAP2_CTRL_BASE			OMAP3430_CTRL_BASE

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Index: linux-omap/arch/arm/plat-omap/common.c
===================================================================
@@ -32,6 +32,10 @@
 
 #include <asm/arch/clock.h>
 
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+# include "../mach-omap2/sdrc.h"
+#endif
+
 #define NO_LENGTH_CHECK 0xffffffff
 
 unsigned char omap_bootloader_tag[512];

@@ -236,18 +240,21 @@
 #if defined(CONFIG_ARCH_OMAP2420)
 void __init omap2_set_globals_242x(void)
 {
+	omap2_sdrc_base = OMAP2420_SDRC_BASE;
 }
 #endif
 
 #if defined(CONFIG_ARCH_OMAP2430)
 void __init omap2_set_globals_243x(void)
 {
+	omap2_sdrc_base = OMAP243X_SDRC_BASE;
 }
 #endif
 
 #if defined(CONFIG_ARCH_OMAP3430)
 void __init omap2_set_globals_343x(void)
 {
+	omap2_sdrc_base = OMAP343X_SDRC_BASE;
 }
 #endif
 

Index: linux-omap/arch/arm/mach-omap2/memory.c
===================================================================
@@ -32,9 +32,8 @@
 #include "memory.h"
 #include "sdrc.h"
 
-#define SMS_SYSCONFIG			(OMAP2_SMS_BASE + 0x010)
-
 unsigned long omap2_sdrc_base;
+unsigned long omap2_sms_base;
 
 static struct memory_timings mem_timings;
 static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;

@@ -160,14 +159,13 @@
 {
 	u32 l;
 
-	l = omap_readl(SMS_SYSCONFIG);
+	l = sms_read_reg(SMS_SYSCONFIG);
 	l &= ~(0x3 << 3);
 	l |= (0x2 << 3);
-	omap_writel(l, SMS_SYSCONFIG);
+	sms_write_reg(l, SMS_SYSCONFIG);
 
 	l = sdrc_read_reg(SDRC_SYSCONFIG);
 	l &= ~(0x3 << 3);
 	l |= (0x2 << 3);
 	sdrc_write_reg(l, SDRC_SYSCONFIG);
-
 }

Index: linux-omap/arch/arm/mach-omap2/sdrc.h
===================================================================
@@ -19,8 +19,11 @@
 #include <asm/arch/sdrc.h>
 
 extern unsigned long omap2_sdrc_base;
+extern unsigned long omap2_sms_base;
 
 #define OMAP_SDRC_REGADDR(reg)	(void __iomem *)IO_ADDRESS(omap2_sdrc_base + reg)
+#define OMAP_SMS_REGADDR(reg)	(void __iomem *)IO_ADDRESS(omap2_sms_base + reg)
+
 
 /* SDRC global register get/set */
 

@@ -37,5 +40,21 @@
 	return __raw_readl(OMAP_SDRC_REGADDR(reg));
 }
 
+/* SMS global register get/set */
+
+static void __attribute__((unused)) sms_write_reg(u32 val, u16 reg)
+{
+	pr_debug("sms_write_reg: writing 0x%0x to 0x%0x\n", val,
+		 (u32)OMAP_SMS_REGADDR(reg));
+
+	__raw_writel(val, OMAP_SMS_REGADDR(reg));
+}
+
+static u32 __attribute__((unused)) sms_read_reg(u16 reg)
+{
+	return __raw_readl(OMAP_SMS_REGADDR(reg));
+}
+
+
 
 #endif

Index: linux-omap/include/asm-arm/arch-omap/sdrc.h
===================================================================
@@ -2,7 +2,7 @@
 #define ____ASM_ARCH_SDRC_H
 
 /*
- * OMAP2 SDRC register definitions
+ * OMAP2/3 SDRC/SMS register definitions
  *
  * Copyright (C) 2007 Texas Instruments, Inc.
  * Copyright (C) 2007 Nokia Corporation

@@ -62,4 +62,18 @@
 #define SDRC_RFR_CTRL_BYPASS	(0x00005000 | 1) /* Need to calc */
 
 
+/*
+ * SMS register access
+ */
+
+
+#define OMAP242X_SMS_REGADDR(reg)	(void __iomem *)IO_ADDRESS(OMAP2420_SMS_BASE + reg)
+#define OMAP243X_SMS_REGADDR(reg)	(void __iomem *)IO_ADDRESS(OMAP243X_SMS_BASE + reg)
+#define OMAP343X_SMS_REGADDR(reg)	(void __iomem *)IO_ADDRESS(OMAP343X_SMS_BASE + reg)
+
+/* SMS register offsets - read/write with sms_{read,write}_reg() */
+
+#define SMS_SYSCONFIG		0x010
+/* REVISIT: fill in other SMS registers here */
+
 #endif

Index: linux-omap/include/asm-arm/arch-omap/omap24xx.h
===================================================================
@@ -83,7 +83,6 @@
 #define OMAP2_PRCM_BASE		OMAP2420_PRCM_BASE
 #define OMAP2_CM_BASE		OMAP2420_CM_BASE
 #define OMAP2_PRM_BASE		OMAP2420_PRM_BASE
-#define OMAP2_SMS_BASE		OMAP2420_SMS_BASE
 #define OMAP2_VA_IC_BASE	IO_ADDRESS(OMAP24XX_IC_BASE)
 #define OMAP2_CTRL_BASE		OMAP2420_CTRL_BASE
 

@@ -93,7 +92,6 @@
 #define OMAP2_PRCM_BASE		OMAP2430_PRCM_BASE
 #define OMAP2_CM_BASE		OMAP2430_CM_BASE
 #define OMAP2_PRM_BASE		OMAP2430_PRM_BASE
-#define OMAP2_SMS_BASE		OMAP243X_SMS_BASE
 #define OMAP2_VA_IC_BASE	IO_ADDRESS(OMAP24XX_IC_BASE)
 #define OMAP2_CTRL_BASE		OMAP243X_CTRL_BASE
 

Index: linux-omap/include/asm-arm/arch-omap/omap34xx.h
===================================================================
@@ -45,8 +45,8 @@
 #define OMAP343X_SMS_BASE	0x6C000000
 #define OMAP343X_SDRC_BASE	0x6D000000
 #define OMAP34XX_GPMC_BASE	0x6E000000
-#define OMAP3430_SCM_BASE	0x48002000
-#define OMAP3430_CTRL_BASE	OMAP3430_SCM_BASE
+#define OMAP343X_SCM_BASE	0x48002000
+#define OMAP3430_CTRL_BASE	OMAP343X_SCM_BASE
 
 #define OMAP34XX_IC_BASE	0x48200000
 #define OMAP34XX_IVA_INTC_BASE	0x40000000

@@ -64,7 +64,6 @@
 #define OMAP2_32KSYNCT_BASE		OMAP3430_32KSYNCT_BASE
 #define OMAP2_CM_BASE			OMAP3430_CM_BASE
 #define OMAP2_PRM_BASE			OMAP3430_PRM_BASE
-#define OMAP2_SMS_BASE			OMAP343X_SMS_BASE
 #define OMAP2_VA_IC_BASE		IO_ADDRESS(OMAP34XX_IC_BASE)
 #define OMAP2_CTRL_BASE			OMAP3430_CTRL_BASE
 #define OMAP34XX_CONTROL_DEVCONF0	(L4_34XX_BASE + 0x2274)

Index: linux-omap/arch/arm/plat-omap/common.c
===================================================================
@@ -241,6 +241,7 @@
 void __init omap2_set_globals_242x(void)
 {
 	omap2_sdrc_base = OMAP2420_SDRC_BASE;
+	omap2_sms_base = OMAP2420_SMS_BASE;
 }
 #endif
 

@@ -248,6 +249,7 @@
 void __init omap2_set_globals_243x(void)
 {
 	omap2_sdrc_base = OMAP243X_SDRC_BASE;
+	omap2_sms_base = OMAP243X_SMS_BASE;
 }
 #endif
 

@@ -255,6 +257,7 @@
 void __init omap2_set_globals_343x(void)
 {
 	omap2_sdrc_base = OMAP343X_SDRC_BASE;
+	omap2_sms_base = OMAP343X_SMS_BASE;
 }
 #endif
 

Index: linux-omap/arch/arm/mach-omap2/control.h
===================================================================
@@ -0,0 +1,41 @@
+#ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H
+#define __ARCH_ARM_MACH_OMAP2_CONTROL_H
+
+/*
+ * OMAP2/3 System Control Module register definitions
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#undef DEBUG
+
+#include <linux/kernel.h>
+#include <asm/arch/control.h>
+
+extern unsigned long omap2_ctrl_base;
+
+#define OMAP_CTRL_REGADDR(reg)	(void __iomem *)IO_ADDRESS(omap2_ctrl_base + reg)
+
+
+/* Control global register get/set */
+
+static void __attribute__((unused)) ctrl_write_reg(u32 val, u16 reg)
+{
+	pr_debug("ctrl_write_reg: writing 0x%0x to 0x%0x\n", val,
+		 (u32)OMAP_CTRL_REGADDR(reg));
+
+	__raw_writel(val, OMAP_CTRL_REGADDR(reg));
+}
+
+static u32 __attribute__((unused)) ctrl_read_reg(u16 reg)
+{
+	return __raw_readl(OMAP_CTRL_REGADDR(reg));
+}
+
+#endif  /* __ARCH_ARM_MACH_OMAP2_CONTROL_H */

Index: linux-omap/arch/arm/plat-omap/sram.c
===================================================================
@@ -29,6 +29,7 @@
 # include "../mach-omap2/prm.h"
 # include "../mach-omap2/cm.h"
 # include "../mach-omap2/sdrc.h"
+# include "../mach-omap2/control.h"
 #endif
 
 #define OMAP1_SRAM_PA		0x20000000

@@ -47,7 +48,6 @@
 #define VA_REQINFOPERM0		IO_ADDRESS(0x68005048)
 #define VA_READPERM0		IO_ADDRESS(0x68005050)
 #define VA_WRITEPERM0		IO_ADDRESS(0x68005058)
-#define VA_CONTROL_STAT		IO_ADDRESS(0x480002F8)
 #define GP_DEVICE		0x300
 #define TYPE_MASK		0x700
 

@@ -92,8 +92,10 @@
 {
 	int type = 0;
 
+#if defined(CONFIG_ARCH_OMAP242X)
 	if (cpu_is_omap242x())
-		type = __raw_readl(VA_CONTROL_STAT) & TYPE_MASK;
+		type = ctrl_read_reg(CONTROL_STATUS) & TYPE_MASK;
+#endif
 
 	if (type == GP_DEVICE) {
 		/* RAMFW: R/W access to all initiators for all qualifier sets */

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Index: linux-omap/arch/arm/plat-omap/devices.c
===================================================================
@@ -25,6 +25,10 @@
 #include <asm/arch/gpio.h>
 #include <asm/arch/menelaus.h>
 
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+# include "../mach-omap2/control.h"
+#endif
+
 #if	defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE)
 
 #include "../plat-omap/dsp/dsp_common.h"

@@ -269,17 +273,19 @@
 				omap_cfg_reg(MMC_DAT3);
 			}
 		}
+#if defined(CONFIG_ARCH_OMAP2420)
 		if (mmc->internal_clock) {
 			/*
 			 * Use internal loop-back in MMC/SDIO
 			 * Module Input Clock selection
 			 */
 			if (cpu_is_omap24xx()) {
-				u32 v = omap_readl(OMAP2_CONTROL_DEVCONF);
-				v |= (1 << 24);
-				omap_writel(v, OMAP2_CONTROL_DEVCONF);
+				u32 v = ctrl_read_reg(CONTROL_DEVCONF0);
+				v |= (1 << 24); /* not used in 243x */
+				ctrl_write_reg(v, CONTROL_DEVCONF0);
 			}
 		}
+#endif
 		mmc1_conf = *mmc;
 		(void) platform_device_register(&mmc_omap_device1);
 	}

Index: linux-omap/arch/arm/mach-omap2/clock34xx.h
===================================================================
@@ -15,19 +15,11 @@
 #include "cm_regbits_34xx.h"
 #include "prm.h"
 #include "prm_regbits_34xx.h"
+#include "control.h"
 
 static void omap3_dpll_recalc(struct clk *clk);
 static void omap3_clkoutx2_recalc(struct clk *clk);
 
-/* REVISIT: this stuff should be moved to a scm.h file */
-/* CONTROL_DEVCONF0 bits */
-#define OMAP3430_MCBSP2_CLKS_MASK		    (1 << 6)
-#define OMAP3430_MCBSP1_CLKS_MASK		    (1 << 2)
-/* OMAP34XX_CONTROL_DEVCONF1 bits */
-#define OMAP3430_MCBSP5_CLKS_MASK		    (1 << 4)
-#define OMAP3430_MCBSP4_CLKS_MASK		    (1 << 2)
-#define OMAP3430_MCBSP3_CLKS_MASK		    (1 << 0)
-
 /*
  * DPLL1 supplies clock to the MPU.
  * DPLL2 supplies clock to the IVA2.

@@ -930,8 +922,8 @@
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_MCBSP5_SHIFT,
-	.clksel_reg	= (void __iomem *)IO_ADDRESS(OMAP34XX_CONTROL_DEVCONF1),
-	.clksel_mask	= OMAP3430_MCBSP5_CLKS_MASK,
+	.clksel_reg	= OMAP343X_CTRL_REGADDR(CONTROL_DEVCONF1),
+	.clksel_mask	= OMAP2_MCBSP5_CLKS_MASK,
 	.clksel		= mcbsp_15_clksel,
 	.flags		= CLOCK_IN_OMAP343X,
 	.recalc		= &omap2_clksel_recalc,

@@ -942,8 +934,8 @@
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_MCBSP1_SHIFT,
-	.clksel_reg	= (void __iomem *)IO_ADDRESS(OMAP34XX_CONTROL_DEVCONF0),
-	.clksel_mask	= OMAP3430_MCBSP1_CLKS_MASK,
+	.clksel_reg	= OMAP343X_CTRL_REGADDR(CONTROL_DEVCONF0),
+	.clksel_mask	= OMAP2_MCBSP1_CLKS_MASK,
 	.clksel		= mcbsp_15_clksel,
 	.flags		= CLOCK_IN_OMAP343X,
 	.recalc		= &omap2_clksel_recalc,

@@ -1990,8 +1982,8 @@
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_MCBSP2_SHIFT,
-	.clksel_reg	= (void __iomem *)IO_ADDRESS(OMAP34XX_CONTROL_DEVCONF0),
-	.clksel_mask	= OMAP3430_MCBSP2_CLKS_MASK,
+	.clksel_reg	= OMAP343X_CTRL_REGADDR(CONTROL_DEVCONF0),
+	.clksel_mask	= OMAP2_MCBSP2_CLKS_MASK,
 	.clksel		= mcbsp_234_clksel,
 	.flags		= CLOCK_IN_OMAP343X,
 	.recalc		= &omap2_clksel_recalc,

@@ -2002,8 +1994,8 @@
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_MCBSP3_SHIFT,
-	.clksel_reg	= (void __iomem *)IO_ADDRESS(OMAP34XX_CONTROL_DEVCONF1),
-	.clksel_mask	= OMAP3430_MCBSP3_CLKS_MASK,
+	.clksel_reg	= OMAP343X_CTRL_REGADDR(CONTROL_DEVCONF1),
+	.clksel_mask	= OMAP2_MCBSP3_CLKS_MASK,
 	.clksel		= mcbsp_234_clksel,
 	.flags		= CLOCK_IN_OMAP343X,
 	.recalc		= &omap2_clksel_recalc,

@@ -2014,8 +2006,8 @@
 	.init		= &omap2_init_clksel_parent,
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_MCBSP4_SHIFT,
-	.clksel_reg	= (void __iomem *)IO_ADDRESS(OMAP34XX_CONTROL_DEVCONF1),
-	.clksel_mask	= OMAP3430_MCBSP4_CLKS_MASK,
+	.clksel_reg	= OMAP343X_CTRL_REGADDR(CONTROL_DEVCONF1),
+	.clksel_mask	= OMAP2_MCBSP4_CLKS_MASK,
 	.clksel		= mcbsp_234_clksel,
 	.flags		= CLOCK_IN_OMAP343X,
 	.recalc		= &omap2_clksel_recalc,

Index: linux-omap/arch/arm/mach-omap2/board-h4.c
===================================================================
@@ -47,6 +47,7 @@
 
 #include <asm/io.h>
 
+#include "control.h"
 #include <../drivers/media/video/ov9640.h>
 
 #define H4_FLASH_CS	0

@@ -271,7 +272,7 @@
 /* 2420 Sysboot setup (2430 is different) */
 static u32 get_sysboot_value(void)
 {
-	return (omap_readl(OMAP2_CONTROL_STATUS) & 0xFFF);
+	return (ctrl_read_reg(CONTROL_STATUS) & 0xFFF);
 }
 
 /* FIXME: This function should be moved to some other file, gpmc.c? */

Index: linux-omap/arch/arm/mach-omap2/pm.c
===================================================================
@@ -51,6 +51,7 @@
 #include "cm.h"
 #include "cm_regbits_24xx.h"
 #include "sdrc.h"
+#include "control.h"
 
 /* These addrs are in assembly language code to be patched at runtime */
 extern void *omap2_ocs_sdrc_power;

@@ -351,8 +352,6 @@
 
 static struct clk *osc_ck, *emul_ck;
 
-#define CONTROL_DEVCONF		__REG32(OMAP2_CTRL_BASE + 0x274)
-
 static int omap2_fclks_active(void)
 {
 	u32 f1, f2;

@@ -395,7 +394,7 @@
 
 static void omap2_enter_full_retention(void)
 {
-	u32 sleep_time = 0;
+	u32 sleep_time = 0, r;
 
 	/* There is 1 reference hold for all children of the oscillator
 	 * clock, the following will remove it. If no one else uses the

@@ -415,7 +414,8 @@
 			  MPU_MOD, PM_PWSTCTRL);
 
 	/* Workaround to kill USB */
-	CONTROL_DEVCONF |= 0x00008000;
+	r = ctrl_read_reg(CONTROL_DEVCONF0) | 0x00008000;
+	ctrl_write_reg(r, CONTROL_DEVCONF0);
 
 	omap2_gpio_prepare_for_retention();
 

Index: linux-omap/include/asm-arm/arch-omap/omap24xx.h
===================================================================
@@ -84,7 +84,6 @@
 #define OMAP2_CM_BASE		OMAP2420_CM_BASE
 #define OMAP2_PRM_BASE		OMAP2420_PRM_BASE
 #define OMAP2_VA_IC_BASE	IO_ADDRESS(OMAP24XX_IC_BASE)
-#define OMAP2_CTRL_BASE		OMAP2420_CTRL_BASE
 
 #elif defined(CONFIG_ARCH_OMAP2430)
 

@@ -93,19 +92,8 @@
 #define OMAP2_CM_BASE		OMAP2430_CM_BASE
 #define OMAP2_PRM_BASE		OMAP2430_PRM_BASE
 #define OMAP2_VA_IC_BASE	IO_ADDRESS(OMAP24XX_IC_BASE)
-#define OMAP2_CTRL_BASE		OMAP243X_CTRL_BASE
 
-#elif !defined(CONFIG_ARCH_OMAP34XX)
-/* FIXME: These will go away soon */
-#define OMAP2_CTRL_BASE		L4_24XX_BASE
 #endif
 
-/* Control module */
-#define OMAP2_CONTROL_DEVCONF0	(OMAP2_CTRL_BASE + 0x274)
-#define OMAP2_CONTROL_DEVCONF1	(OMAP2_CTRL_BASE + 0x2e8)
-#define OMAP2_CONTROL_DEVCONF   OMAP2_CONTROL_DEVCONF0
-
-#define OMAP2_CONTROL_STATUS	(OMAP2_CTRL_BASE + 0x2f8)
-
 #endif /* __ASM_ARCH_OMAP24XX_H */
 

Index: linux-omap/include/asm-arm/arch-omap/omap34xx.h
===================================================================
@@ -46,7 +46,7 @@
 #define OMAP343X_SDRC_BASE	0x6D000000
 #define OMAP34XX_GPMC_BASE	0x6E000000
 #define OMAP343X_SCM_BASE	0x48002000
-#define OMAP3430_CTRL_BASE	OMAP343X_SCM_BASE
+#define OMAP343X_CTRL_BASE	OMAP343X_SCM_BASE
 
 #define OMAP34XX_IC_BASE	0x48200000
 #define OMAP34XX_IVA_INTC_BASE	0x40000000

@@ -55,20 +55,10 @@
 
 #if defined(CONFIG_ARCH_OMAP3430)
 
-/*
- * REVISIT: OMAP3430 has two CONTROL_DEVCONF registers, CONTROL_DEVCONF0
- * and CONTROL_DEVCONF1.  We should probably split those defines, along
- * with any other System Control Module registers and read/write fns,
- * out to a separate scm.h file, and do this for 24xx also.
- */
 #define OMAP2_32KSYNCT_BASE		OMAP3430_32KSYNCT_BASE
 #define OMAP2_CM_BASE			OMAP3430_CM_BASE
 #define OMAP2_PRM_BASE			OMAP3430_PRM_BASE
 #define OMAP2_VA_IC_BASE		IO_ADDRESS(OMAP34XX_IC_BASE)
-#define OMAP2_CTRL_BASE			OMAP3430_CTRL_BASE
-#define OMAP34XX_CONTROL_DEVCONF0	(L4_34XX_BASE + 0x2274)
-#define OMAP34XX_CONTROL_DEVCONF1	(L4_34XX_BASE + 0x22D8)
-#define OMAP2_CONTROL_STATUS		(OMAP2_CTRL_BASE + 0x2f0)
 
 #endif
 

Index: linux-omap/include/asm-arm/arch-omap/usb.h
===================================================================
@@ -132,14 +132,11 @@
 #	define	CONF_USB_PWRDN_DP_R	(1 << 1)
 
 /* OMAP2 */
-#define	CONTROL_DEVCONF_REG		__REG32(L4_24XX_BASE + 0x0274)
 #	define	USB_UNIDIR			0x0
 #	define	USB_UNIDIR_TLL			0x1
 #	define	USB_BIDIR			0x2
 #	define	USB_BIDIR_TLL			0x3
-#	define	USBT0WRMODEI(x)		((x) << 22)
-#	define	USBT1WRMODEI(x)		((x) << 20)
-#	define	USBT2WRMODEI(x)		((x) << 18)
+#	define	USBTXWRMODEI(port, x)	((x) << (22 - (port * 2)))
 #	define	USBT2TLL5PI		(1 << 17)
 #	define	USB0PUENACTLOI		(1 << 16)
 #	define	USBSTANDBYCTRL		(1 << 15)

Index: linux-omap/arch/arm/plat-omap/common.c
===================================================================
@@ -38,6 +38,8 @@
 
 #define NO_LENGTH_CHECK 0xffffffff
 
+u32 omap2_ctrl_base; /* until we have a better place to put it */
+
 unsigned char omap_bootloader_tag[512];
 int omap_bootloader_tag_len;
 

@@ -242,6 +244,7 @@
 {
 	omap2_sdrc_base = OMAP2420_SDRC_BASE;
 	omap2_sms_base = OMAP2420_SMS_BASE;
+	omap2_ctrl_base = OMAP2420_CTRL_BASE;
 }
 #endif
 

@@ -250,6 +253,7 @@
 {
 	omap2_sdrc_base = OMAP243X_SDRC_BASE;
 	omap2_sms_base = OMAP243X_SMS_BASE;
+	omap2_ctrl_base = OMAP243X_CTRL_BASE;
 }
 #endif
 

@@ -258,6 +262,7 @@
 {
 	omap2_sdrc_base = OMAP343X_SDRC_BASE;
 	omap2_sms_base = OMAP343X_SMS_BASE;
+	omap2_ctrl_base = OMAP343X_CTRL_BASE;
 }
 #endif
 

Index: linux-omap/arch/arm/plat-omap/mux.c
===================================================================
@@ -30,6 +30,10 @@
 #include <linux/spinlock.h>
 #include <asm/arch/mux.h>
 
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+# include "../mach-omap2/control.h"
+#endif
+
 #ifdef CONFIG_OMAP_MUX
 
 #define OMAP24XX_PULL_ENA	(1 << 3)

@@ -75,6 +79,7 @@
 
 	cfg = (struct pin_config *)&pin_table[index];
 #ifdef CONFIG_ARCH_OMAP24XX
+	/* REVISIT: Convert this code to use ctrl_{read,write}_reg */
 	if (cpu_is_omap24xx()) {
 		u8 reg = 0;
 

@@ -85,7 +90,7 @@
 			reg |= OMAP24XX_PULL_UP;
 #if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
 		{
-			u8 orig = omap_readb(OMAP2_CTRL_BASE + cfg->mux_reg);
+			u8 orig = omap_readb(omap2_ctrl_base + cfg->mux_reg);
 			u8 debug = 0;
 
 #ifdef	CONFIG_OMAP_MUX_DEBUG

@@ -93,13 +98,13 @@
 #endif
 			warn = (orig != reg);
 			if (debug || warn)
-				printk("MUX: setup %s (0x%08x): 0x%02x -> 0x%02x\n",
+				printk("MUX: setup %s (0x%08lx): 0x%02x -> 0x%02x\n",
 						cfg->name,
-						OMAP2_CTRL_BASE + cfg->mux_reg,
+						omap2_ctrl_base + cfg->mux_reg,
 						orig, reg);
 		}
 #endif
-		omap_writeb(reg, OMAP2_CTRL_BASE + cfg->mux_reg);
+		omap_writeb(reg, omap2_ctrl_base + cfg->mux_reg);
 
 		return 0;
 	}

Index: linux-omap/arch/arm/mach-omap2/id.c
===================================================================
@@ -17,6 +17,8 @@
 
 #include <asm/io.h>
 
+#include "control.h"
+
 #if defined(CONFIG_ARCH_OMAP2420)
 #define TAP_BASE	io_p2v(0x48014000)
 #elif defined(CONFIG_ARCH_OMAP2430)

@@ -160,7 +162,7 @@
 	/* Embedding the ES revision info in type field */
 	system_rev = omap_ids[j].type;
 
-	ctrl_status = omap_readl(OMAP2_CONTROL_STATUS);
+	ctrl_status = ctrl_read_reg(CONTROL_STATUS);
 	system_rev |= (ctrl_status & 0x3f);
 	system_rev |= (ctrl_status & 0x700);