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handle MC threshold registers for Barcelona

PATCH Applied Christoph Egger 2 participants 2 messages Nov 22, 2007

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Christoph Egger

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#0 lore raw

PATCH 1/1 handle MC threshold registers for Barcelona

Hi!

Subject says it all

Signed-off-by Christoph Egger <[email protected]>
Signature · 12 lines
AMD Saxony, Dresden, Germany
Operating System Research Center

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xen/arch/x86/hvm/svm/svm.c +2 -0
diff -r 980b8d1a5541 xen/arch/x86/hvm/svm/svm.c
@@ -133,6 +133,7 @@ static enum handler_return long_mode_do_
         break;
 
     case MSR_IA32_MC4_MISC: /* Threshold register */
+    case MSR_F10_MC4_MISC1 ... MSR_F10_MC4_MISC3:
         /*
          * MCA/MCE: Threshold register is reported to be locked, so we ignore
          * all write accesses. This behaviour matches real HW, so guests should

@@ -1777,6 +1778,7 @@ static void svm_do_msr_access(
             break;
 
         case MSR_IA32_MC4_MISC: /* Threshold register */
+        case MSR_F10_MC4_MISC1 ... MSR_F10_MC4_MISC3:
             /*
              * MCA/MCE: We report that the threshold register is unavailable
              * for OS use (locked by the BIOS).

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Applied
#1 lore raw

Applied. If someone at AMD would produce the list of patches in xen-unstable for Family10 support, I'd consider them for backport to 3.1 branch for 3.1.3.

-- Keir

Quoted 7 lines · Christoph Egger

Hi!

Subject says it all

Signed-off-by Christoph Egger <[email protected]>