Skip to contentSkip to conversation

ppc4xx: Problems running POST on PPC405GPr board

U-Boot-Users Niklaus Giger 3 participants 3 messages Jan 11, 2008

lore
Share & tools
lore
#0 lore raw

Hi

I am trying to add POST for my PPC405GPr based boards and I am running into a few problems:

a) the post/cpu/ppc4xx/uart.c assumed 4 UARTS. I would rather try only as much UARTs as defined by the CPUs. Would a patch like the attached one be considered a good solution for this problem?

b) looking at the log I get
<4>POST cache FAILED
<4>POST i2c PASSED
<4>POST cpu PASSED
<4>POST ethernet PASSED
<4>POST spr The value of PIR special register is incorrect: 0x0000005F <4>The value of IVOR0 special register is incorrect: 0x2000005F <4>The value of IVOR1 special register is incorrect: 0x2000005F <4>The value of IVOR2 special register is incorrect: 0x2000005F <4>The value of IVOR3 special register is incorrect: 0x2000005F <4>The value of IVOR4 special register is incorrect: 0x2000005F <4>The value of IVOR5 special register is incorrect: 0x2000005F <4>The value of IVOR6 special register is incorrect: 0x2000005F <4>The value of IVOR7 special register is incorrect: 0x2000005F <4>The value of IVOR8 special register is incorrect: 0x2000005F <4>The value of IVOR10 special register is incorrect: 0x2000005F <4>The value of IVOR13 special register is incorrect: 0x2000005F <4>The value of IVOR14 special register is incorrect: 0x2000005F <4>The value of IVOR15 special register is incorrect: 0x2000005F <4>The value of DVLIM special register is incorrect: 0x2000005F <4>The value of IVLIM special register is incorrect: 0x2000005F <4>FAILED

What would be the correct #if to exclude the IVOR<x> part in post/cpu/ppc4xx/spr.c, as it make no sense to test these non existant registers on a PPC405 processor?

Has anybody a suggestion how to fill in a good value for for the PIR (Processor Identification Register)?

c) I will investigate the exact cause for the POST cache FAILED.

Best regards

Niklaus
-------------- next part --------------
A non-text attachment was scrubbed...
Name: post.diff
Type: text/x-diff
Size: 1187 bytes
Desc: not available
Url : http://lists.denx.de/pipermail/u-boot/attachments/20080111/dc354a32/attachment.diff

#1 lore raw

Dear Niklaus,

Quoted 7 lines · in message <[email protected]> you wrote:

I am trying to add POST for my PPC405GPr based boards and I am running into a few problems:

a) the post/cpu/ppc4xx/uart.c assumed 4 UARTS. I would rather try only as much UARTs as defined by the CPUs. Would a patch like the attached one be considered a good solution for this problem?

Nope, that's too ugly.

Quoted 1 line

b) looking at the log I get

...

Quoted 3 lines

What would be the correct #if to exclude the IVOR<x> part in post/cpu/ppc4xx/spr.c, as it make no sense to test these non existant registers on a PPC405 processor?

Maybe the test should be skipped on processors that don't have it - how about testing the PVR?

Best regards,

Wolfgang Denk

Signature · 5 lines
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
In theory, there is no difference between  theory  and  practice.  In
practice, however, there is.
#2 lore raw
In reply to Niklaus Giger

Hi Niklaus,

Quoted 6 lines · Niklaus Giger

I am trying to add POST for my PPC405GPr based boards and I am running into a few problems:

a) the post/cpu/ppc4xx/uart.c assumed 4 UARTS. I would rather try only as much UARTs as defined by the CPUs. Would a patch like the attached one be considered a good solution for this problem?

It's not a good solution, since you can't select for example to only test UART0 and UART2.

Quoted 23 lines

b) looking at the log I get
<4>POST cache FAILED
<4>POST i2c PASSED
<4>POST cpu PASSED
<4>POST ethernet PASSED
<4>POST spr The value of PIR special register is incorrect: 0x0000005F <4>The value of IVOR0 special register is incorrect: 0x2000005F <4>The value of IVOR1 special register is incorrect: 0x2000005F <4>The value of IVOR2 special register is incorrect: 0x2000005F <4>The value of IVOR3 special register is incorrect: 0x2000005F <4>The value of IVOR4 special register is incorrect: 0x2000005F <4>The value of IVOR5 special register is incorrect: 0x2000005F <4>The value of IVOR6 special register is incorrect: 0x2000005F <4>The value of IVOR7 special register is incorrect: 0x2000005F <4>The value of IVOR8 special register is incorrect: 0x2000005F <4>The value of IVOR10 special register is incorrect: 0x2000005F <4>The value of IVOR13 special register is incorrect: 0x2000005F <4>The value of IVOR14 special register is incorrect: 0x2000005F <4>The value of IVOR15 special register is incorrect: 0x2000005F <4>The value of DVLIM special register is incorrect: 0x2000005F <4>The value of IVLIM special register is incorrect: 0x2000005F <4>FAILED

Quoted 3 lines

What would be the correct #if to exclude the IVOR<x> part in post/cpu/ppc4xx/spr.c, as it make no sense to test these non existant registers on a PPC405 processor?

#if defined(CONFIG_440)

Quoted 4 lines

Has anybody a suggestion how to fill in a good value for for the PIR (Processor Identification Register)?

c) I will investigate the exact cause for the POST cache FAILED.

Please take a look at the zeus port. This is a quite new port for 405EP with some POST support.

Best regards,
Stefan

=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================