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use correct at91rm9200 register name

PATCH New David Brownell 3 participants 4 messages Jan 18, 2008 – Mar 30, 2008

Subsystems (2)
Arm/Microchip (AT91) SoC support Arm/actions semi architecture
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David Brownell

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#0 lore raw

PATCH 3/3 use correct at91rm9200 register name

This fixes a naming bug for at91rm9200 lowlevel init code:
NOR boot flash is on chipselect 0, not chipselect 2. This makes code use the register name from chip datasheets.

Signed-off-by David Brownell <[email protected]>
---
 cpu/arm920t/at91rm9200/lowlevel_init.S |    6 +++---
 include/configs/at91rm9200dk.h         |    2 +-
 include/configs/cmc_pu2.h              |    2 +-
 include/configs/csb637.h               |    2 +-
 include/configs/mp2usb.h               |    2 +-
 5 files changed, 7 insertions(+), 7 deletions(-)
cpu/arm920t/at91rm9200/lowlevel_init.S +3 -3
@@ -46,7 +46,7 @@
 #define MC_ASR		0xFFFFFF04
 #define MC_AASR		0xFFFFFF08
 #define EBI_CFGR	0xFFFFFF64
-#define SMC2_CSR	0xFFFFFF70
+#define SMC_CSR0	0xFFFFFF70
 
 /* clocks */
 #define PLLAR		0xFFFFFC28

@@ -146,8 +146,8 @@ SMRDATA:
 	.word MC_AASR_VAL
 	.word EBI_CFGR
 	.word EBI_CFGR_VAL
-	.word SMC2_CSR
-	.word SMC2_CSR_VAL
+	.word SMC_CSR0
+	.word SMC_CSR0_VAL
 	.word PLLAR
 	.word PLLAR_VAL
 	.word PLLBR
include/configs/at91rm9200dk.h +1 -1
@@ -51,7 +51,7 @@
 #define MC_ASR_VAL	0x00000000
 #define MC_AASR_VAL	0x00000000
 #define EBI_CFGR_VAL	0x00000000
-#define SMC2_CSR_VAL	0x00003284 /* 16bit, 2 TDF, 4 WS */
+#define SMC_CSR0_VAL	0x00003284 /* 16bit, 2 TDF, 4 WS */
 
 /* clocks */
 #define PLLAR_VAL	0x20263E04 /* 179.712000 MHz for PCK */
include/configs/cmc_pu2.h +1 -1
@@ -50,7 +50,7 @@
 #define MC_ASR_VAL	0x00000000
 #define MC_AASR_VAL	0x00000000
 #define EBI_CFGR_VAL	0x00000000
-#define SMC2_CSR_VAL	0x100032ad /* 16bit, 2 TDF, 4 WS */
+#define SMC_CSR0_VAL	0x100032ad /* 16bit, 2 TDF, 4 WS */
 
 /* clocks */
 #define PLLAR_VAL	0x2026BE04 /* 179,712 MHz for PCK */
include/configs/csb637.h +1 -1
@@ -51,7 +51,7 @@
 #define MC_ASR_VAL	0x00000000
 #define MC_AASR_VAL	0x00000000
 #define EBI_CFGR_VAL	0x00000000
-#define SMC2_CSR_VAL	0x00003284 /* 16bit, 2 TDF, 4 WS */
+#define SMC_CSR0_VAL	0x00003284 /* 16bit, 2 TDF, 4 WS */
 
 /* clocks */
 #define PLLAR_VAL	0x2031BE01 /* 184.320000 MHz for PCK */
include/configs/mp2usb.h +1 -1
@@ -55,7 +55,7 @@
 #define MC_ASR_VAL	0x00000000
 #define MC_AASR_VAL	0x00000000
 #define EBI_CFGR_VAL	0x00000000
-#define SMC2_CSR_VAL	0x00003084 /* 16bit, 2 TDF, 4 WS */
+#define SMC_CSR0_VAL	0x00003084 /* 16bit, 2 TDF, 4 WS */
 
 /* clocks */
 #define PLLAR_VAL	0x20263E04 /* 180 MHz for PCK */
#1 lore raw

PATCH 3/3 use correct at91rm9200 register name

Dear Jean-Christophe,

Quoted 3 lines · in message <[email protected]> you wrote:

This fixes a naming bug for at91rm9200 lowlevel init code:
NOR boot flash is on chipselect 0, not chipselect 2. This makes code use the register name from chip datasheets.

It seems to me that this patch as well as the other two poatches posted by David Brownell on 18 Jan 2008 have not been applied yet:

01/18 David Brownell     [U-Boot-Users] [patch u-boot git 1/3] add missing ARM boards to MAKEA
01/18 David Brownell     [U-Boot-Users] [patch u-boot git 2/3] better ARM9 compiler options
01/18 David Brownell     [U-Boot-Users] [patch u-boot git 3/3] use correct at91rm9200 register

Could you please check?

Best regards,

Wolfgang Denk

Signature · 4 lines
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The only perfect science is hind-sight.
#3 lore raw

PATCH 1/1 use correct at91rm9200 register name in m501sk board

This fixes a naming bug for at91rm9200 lowlevel init code:
NOR boot flash is on chipselect 0, not chipselect 2. This makes code use the register name from chip datasheets.

Signed-off-by Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
board/m501sk/memsetup.S +4 -4
index 9e174b5..6aea723 100644
@@ -52,8 +52,8 @@
 #define MC_AASR_VAL 0x00000000
 #define EBI_CFGR 0xFFFFFF64
 #define EBI_CFGR_VAL 0x00000000
-#define SMC2_CSR 0xFFFFFF70
-#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
+#define SMC_CSR0 0xFFFFFF70
+#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
 
 /* clocks */
 #define PLLAR 0xFFFFFC28

@@ -141,8 +141,8 @@ SMRDATA:
 	.word MC_AASR_VAL
 	.word EBI_CFGR
 	.word EBI_CFGR_VAL
-	.word SMC2_CSR
-	.word SMC2_CSR_VAL
+	.word SMC_CSR0
+	.word SMC_CSR0_VAL
 	.word PLLAR
 	.word PLLAR_VAL
 	.word PLLBR
Signature · 1 line
1.5.4.1