sh: use ctrl_in/out for on chip pci access

PATCH Applied Magnus Damm 2 participants 2 messages Feb 14, 2008 SuperH

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Magnus Damm

author

2008-02-14 04:52 UTC #0 lore raw

PATCH 1/1 sh: use ctrl_in/out for on chip pci access

This patch makes sure ctrl_inN/outN are used instead of inN/outN for on chip pci registers. Without this patch addresses may be adjusted using the value in generic_io_base. This patch makes it possible to set generic_io_base and have pci without reading and writing all over the place.

Signed-off-by Magnus Damm <[email protected]>

Acked-by Katsuya MATSUBARA <[email protected]>

---

 arch/sh/drivers/pci/fixups-lboxre2.c    |    4 +-
 arch/sh/drivers/pci/fixups-rts7751r2d.c |    4 +-
 arch/sh/drivers/pci/ops-dreamcast.c     |   44 +++++++++++++++----------------
 arch/sh/drivers/pci/pci-sh4.h           |    4 +-
 arch/sh/drivers/pci/pci-sh7751.c        |   16 +++++------
 arch/sh/drivers/pci/pci-sh7780.c        |    2 -
 6 files changed, 37 insertions(+), 37 deletions(-)

arch/sh/drivers/pci/fixups-lboxre2.c +2 -2

@@ -18,7 +18,7 @@ int pci_fixup_pcic(void)
 {
 	unsigned long bcr1, mcr;
 
-	bcr1 = inl(SH7751_BCR1);
+	bcr1 = ctrl_inl(SH7751_BCR1);
 	bcr1 |= 0x40080000;	/* Enable Bit 19 BREQEN, set PCIC to slave */
 	pci_write_reg(bcr1, SH4_PCIBCR1);

@@ -28,7 +28,7 @@ int pci_fixup_pcic(void)
 	pci_write_reg(0xfb900047, SH7751_PCICONF1);
 	pci_write_reg(0xab000001, SH7751_PCICONF4);
 
-	mcr = inl(SH7751_MCR);
+	mcr = ctrl_inl(SH7751_MCR);
 	mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
 	pci_write_reg(mcr, SH4_PCIMCR);

arch/sh/drivers/pci/fixups-rts7751r2d.c +2 -2

@@ -19,7 +19,7 @@ int pci_fixup_pcic(void)
 {
 	unsigned long bcr1, mcr;
 
-	bcr1 = inl(SH7751_BCR1);
+	bcr1 = ctrl_inl(SH7751_BCR1);
 	bcr1 |= 0x40080000;	/* Enable Bit 19 BREQEN, set PCIC to slave */
 	pci_write_reg(bcr1, SH4_PCIBCR1);

@@ -30,7 +30,7 @@ int pci_fixup_pcic(void)
 	pci_write_reg(0xfb900047, SH7751_PCICONF1);
 	pci_write_reg(0xab000001, SH7751_PCICONF4);
 
-	mcr = inl(SH7751_MCR);
+	mcr = ctrl_inl(SH7751_MCR);
 	mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
 	pci_write_reg(mcr, SH4_PCIMCR);

arch/sh/drivers/pci/ops-dreamcast.c +22 ~~-22~~

76 lines not on this page · raw message

arch/sh/drivers/pci/pci-sh4.h +2 -2

@@ -172,11 +172,11 @@ struct sh4_pci_address_map {
 
 static inline void pci_write_reg(unsigned long val, unsigned long reg)
 {
-	outl(val, PCI_REG(reg));
+	ctrl_outl(val, PCI_REG(reg));
 }
 
 static inline unsigned long pci_read_reg(unsigned long reg)
 {
-	return inl(PCI_REG(reg));
+	return ctrl_inl(PCI_REG(reg));
 }
 #endif /* __PCI_SH4_H */

arch/sh/drivers/pci/pci-sh7751.c +8 -8

@@ -58,7 +58,7 @@ static int __init __area_sdram_check(uns
 {
 	u32 word;
 
-	word = inl(SH7751_BCR1);
+	word = ctrl_inl(SH7751_BCR1);
 	/* check BCR for SDRAM in area */
 	if (((word >> area) & 1) = 0) {
 		printk("PCI: Area %d is not configured for SDRAM. BCR1=0x%x\n",

@@ -67,7 +67,7 @@ static int __init __area_sdram_check(uns
 	}
 	pci_write_reg(word, SH4_PCIBCR1);
 
-	word = (u16)inw(SH7751_BCR2);
+	word = (u16)ctrl_inw(SH7751_BCR2);
 	/* check BCR2 for 32bit SDRAM interface*/
 	if (((word >> (area << 1)) & 0x3) != 0x3) {
 		printk("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%x\n",

@@ -85,9 +85,9 @@ int __init sh7751_pcic_init(struct sh4_p
 	u32 word;
 
 	/* Set the BCR's to enable PCI access */
-	reg = inl(SH7751_BCR1);
+	reg = ctrl_inl(SH7751_BCR1);
 	reg |= 0x80000;
-	outl(reg, SH7751_BCR1);
+	ctrl_outl(reg, SH7751_BCR1);
 
 	/* Turn the clocks back on (not done in reset)*/
 	pci_write_reg(0, SH4_PCICLKR);

@@ -179,13 +179,13 @@ int __init sh7751_pcic_init(struct sh4_p
 		return 0;
 
 	/* configure the wait control registers */
-	word = inl(SH7751_WCR1);
+	word = ctrl_inl(SH7751_WCR1);
 	pci_write_reg(word, SH4_PCIWCR1);
-	word = inl(SH7751_WCR2);
+	word = ctrl_inl(SH7751_WCR2);
 	pci_write_reg(word, SH4_PCIWCR2);
-	word = inl(SH7751_WCR3);
+	word = ctrl_inl(SH7751_WCR3);
 	pci_write_reg(word, SH4_PCIWCR3);
-	word = inl(SH7751_MCR);
+	word = ctrl_inl(SH7751_MCR);
 	pci_write_reg(word, SH4_PCIMCR);
 
 	/* NOTE: I'm ignoring the PCI error IRQs for now..

arch/sh/drivers/pci/pci-sh7780.c +1 -1

@@ -52,7 +52,7 @@ static int __init sh7780_pci_init(void)
 
 	pr_debug("PCI: Starting intialization.\n");
 
-	outl(0x00000001, SH7780_PCI_VCR2); /* Enable PCIC */
+	ctrl_outl(0x00000001, SH7780_PCI_VCR2); /* Enable PCIC */
 
 	/* check for SH7780/SH7780R hardware */
 	id = pci_read_reg(SH7780_PCIVID);

Paul Mundt

Applied

2008-02-14 05:23 UTC #1 lore raw

Quoted 4 lines · Magnus Damm

This patch makes sure ctrl_inN/outN are used instead of inN/outN for on chip pci registers. Without this patch addresses may be adjusted using the value in generic_io_base. This patch makes it possible to set generic_io_base and have pci without reading and writing all over the place.

Quoted 14 lines · Magnus Damm

This patch is a fix to make sure readsN/writesN are used over insN/outsN for ioreadN_rep/iowriteN_rep.
The current state of the sh io code is that mmio operations like readN/writeN and ioreadN/iowriteN are unaffected by the value of generic_io_base. This is different fom port based io like inN/outN which gets adjusted using the value in generic_io_base.
Without this patch ioreadN_rep/iowriteN_rep get their addresses adjusted. The address for mmio access is adjusted using generic_io_base. This is wrong. The ata core code currently crashes if generic_io_base is set.
This patch changes ioreadN_rep/iowriteN_rep to follow the same rules as the rest of the mmio operations, ie don't adjust using generic_io_base.

Quoted 5 lines · Magnus Damm

Use generic_io_base to point out the pci io window, and make sure the highest port address used is SH7751_PCI_IO_SIZE - 1.
This patch fixes pci io port access for the r2d boards - CONFIG_8139TOO_PIO now works as expected. So does the alsa driver for CMI8738.

Applied, thanks.