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mpc83xx: Add MPC837x PCIE controller RC mode

PATCH New Anton Vorontsov 5 participants 5 messages Mar 24, 2008 – Mar 25, 2008

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Anton Vorontsov

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#0 lore raw

PATCH 1/2 mpc83xx: Add MPC837x PCIE controller RC mode

From: Li Li <[email protected]>

This patch is based on Dave Liu`s previously sent MPC837x patches.

Initial the MPC837x PCIE controller.
Note that configue address bit field is not compatible with PCIE spec 10a. So, the pci command output is not reliable.
Just map 16M pci configure space which corresponding to a bus configure space at once. If want to access bus number other than 0. Need to remap the pci configure window by hand.

Signed-off-by Tony Li <[email protected]>

[ AV: rebased on top of current mpc83xx.git, added mpc83xx_pcie
header file, plus removed MPC837XEMDS specific changes ]

Signed-off-by Anton Vorontsov <[email protected]>
---
 cpu/mpc83xx/Makefile           |    1 +
 cpu/mpc83xx/pcie.c             |  273 ++++++++++++++++++++++++++++++++++++++++
 include/asm-ppc/immap_83xx.h   |  119 +++++++++++++++++-
 include/asm-ppc/mpc83xx_pcie.h |   14 ++
 include/configs/MPC8360ERDK.h  |    4 +-
 include/mpc83xx.h              |   42 ++++++
 include/pci.h                  |    4 +
 7 files changed, 449 insertions(+), 8 deletions(-)
 create mode 100644 cpu/mpc83xx/pcie.c
 create mode 100644 include/asm-ppc/mpc83xx_pcie.h
cpu/mpc83xx/Makefile +1 -0
index fcb6a52..dd35e6b 100644
@@ -39,6 +39,7 @@ COBJS-y += ecc.o
 COBJS-$(CONFIG_QE) += qe_io.o
 COBJS-$(CONFIG_FSL_SERDES) += serdes.o
 COBJS-$(CONFIG_83XX_GENERIC_PCI) += pci.o
+COBJS-$(CONFIG_83XX_GENERIC_PCIE) += pcie.o
 COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
 
 COBJS	:= $(COBJS-y)
cpu/mpc83xx/pcie.c new file +273 -0

273 lines not on this page · raw message

include/asm-ppc/immap_83xx.h +113 -6

142 lines not on this page · raw message

include/asm-ppc/mpc83xx_pcie.h new file +14 -0
new file mode 100644
index 0000000..c621ce7
@@ -0,0 +1,14 @@
+#ifndef __ASM_MPC83XX_PCIE
+#define __ASM_MPC83XX_PCIE
+
+#include <pci.h>
+
+#ifdef CONFIG_PCIE
+extern void mpc83xx_pcie_init(int num_buses, struct pci_region **reg,
+			      int warmboot);
+#else 
+static void mpc83xx_pcie_init(int num_buses, struct pci_region **reg,
+			      int warmboot) {}
+#endif
+
+#endif /* __ASM_MPC83XX_PCIE */
include/configs/MPC8360ERDK.h +2 -2
index 27b037a..1588610 100644
@@ -290,7 +290,7 @@
 #define CFG_UEC1_TX_CLK		QE_CLK9
 #define CFG_UEC1_ETH_TYPE	GIGA_ETH
 #define CFG_UEC1_PHY_ADDR	2
-#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII
+#define CFG_UEC1_INTERFACE_MODE ENET_1000_RGMII_RXID
 #endif
 
 #define CONFIG_UEC_ETH2		/* GETH2 */

@@ -301,7 +301,7 @@
 #define CFG_UEC2_TX_CLK		QE_CLK4
 #define CFG_UEC2_ETH_TYPE	GIGA_ETH
 #define CFG_UEC2_PHY_ADDR	4
-#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII
+#define CFG_UEC2_INTERFACE_MODE ENET_1000_RGMII_RXID
 #endif
 
 /*
include/mpc83xx.h +42 -0

48 lines not on this page · raw message

include/pci.h +4 -0
index 8e5dacc..a0a84c9 100644
@@ -374,6 +374,8 @@ extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev
 
 #define MAX_PCI_REGIONS		7
 
+#define INDIRECT_TYPE_NO_PCIE_LINK	1
+
 /*
  * Structure of a PCI controller (host bridge)
  */

@@ -386,6 +388,8 @@ struct pci_controller {
 	volatile unsigned int *cfg_addr;
 	volatile unsigned char *cfg_data;
 
+	int indirect_type;
+
 	struct pci_region regions[MAX_PCI_REGIONS];
 	int region_count;
Signature · 1 line
1.5.2.2
#1 lore raw

PATCH 1/2 mpc83xx: Add MPC837x PCIE controller RC mode

Quoted 8 lines

Initial the MPC837x PCIE controller.
Note that configue address bit field is not compatible with PCIE spec 10a.
So, the pci command output is not reliable.
Just map 16M pci configure space which corresponding to a bus configure space at once.
If want to access bus number other than 0. Need to remap the pci configure window by hand.

Anton, this code still has some issue on it.
We have update from the state of this code.

Thanks,
Dave

#2 lore raw

PATCH 1/2 mpc83xx: Add MPC837x PCIE controller RC mode

In reply to Anton Vorontsov

cpu/mpc83xx/pcie.c line 47

Quoted 12 lines
cpu/mpc83xx/pcie.c new file +12 -0
+static struct pci_controller pcie_hose[PCIE_MAX_BUSES];
+static int pcie_num_buses;
+
+#define cfg_read(val, addr, type, op)	*val = op((type)(addr))
+#define cfg_write(val, addr, type, op)	op((type *)(addr), (val))
+
+#define PCIE_OP(rw, size, type, op)						\
+static int									\
+pcie_##rw##_config_##size(struct pci_controller *hose,				\
+			pci_dev_t dev, int offset, type val)			\
+{										\
+	u32 b, d, f;								\

Please add empty line

Quoted 36 lines
cpu/mpc83xx/pcie.c new file +36 -0
+	if (hose->indirect_type == INDIRECT_TYPE_NO_PCIE_LINK)			\
+		return -1;							\
+	b = PCI_BUS(dev); d = PCI_DEV(dev) & 0x1f; f = PCI_FUNC(dev) & 0x7;	\
+	b = b - hose->first_busno;						\
+	dev = (b << 24) | (((d << 3) | f) << 16) | (offset & 0xfff);		\
+	cfg_##rw(val, (u32)hose->cfg_addr + (u32)dev, type, op);		\
+	return 0;								\
+}
+
+PCIE_OP(read, byte, u8 *, in_8)
+PCIE_OP(read, word, u16 *, in_le16)
+PCIE_OP(read, dword, u32 *, in_le32)
+PCIE_OP(write, byte, u8, out_8)
+PCIE_OP(write, word, u16, out_le16)
+PCIE_OP(write, dword, u32, out_le32)
+
+	static int max_bus = 0;
+	unsigned int ram_sz, barl, tar;
+	u16 reg16;
+	int i, j;
+
+	/* Enable pex csb bridge inbound & outbound transactions */
+	out_le32(&pex->bridge.pex_csb_ctrl,
+		in_le32(&pex->bridge.pex_csb_ctrl) | PEX_CSB_CTRL_OBPIOE |
+		PEX_CSB_CTRL_IBPIOE);
+
+	/* Enable bridge outbound */
+	out_le32(&pex->bridge.pex_csb_obctrl, PEX_CSB_OBCTRL_PIOE |
+		PEX_CSB_OBCTRL_MEMWE | PEX_CSB_OBCTRL_IOWE |
+		PEX_CSB_OBCTRL_CFGWE);
+
+	out_win = &pex->bridge.pex_outbound_win[0];
+	if (bus) {
+		out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG |
+			CFG_PCIE2_CFG_SIZE);
+		out_le32(&out_win->bar, CFG_PCIE2_CFG_BASE);

cpu/mpc83xx/pcie.c line 114

Quoted 10 lines
cpu/mpc83xx/pcie.c new file +10 -0
+	} else {
+		out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG |
+			CFG_PCIE1_CFG_SIZE);
+		out_le32(&out_win->bar, CFG_PCIE1_CFG_BASE);
+	}
+	out_le32(&out_win->tarl, 0);
+	out_le32(&out_win->tarh, 0);
+
+	for (i = 0; i < 2; i++, reg++) {
+		u32 ar;

please add empty line

Quoted 21 lines
cpu/mpc83xx/pcie.c new file +21 -0
+		if (reg->size == 0)
+			break;
+
+		hose->regions[i] = *reg;
+		hose->region_count++;
+
+		out_win = &pex->bridge.pex_outbound_win[i + 1];
+		out_le32(&out_win->bar, reg->phys_start);
+		out_le32(&out_win->tarl, reg->bus_start);
+		out_le32(&out_win->tarh, 0);
+		ar = PEX_OWAR_EN | (reg->size & PEX_OWAR_SIZE);
+		if (reg->flags & PCI_REGION_IO)
+			ar |= PEX_OWAR_TYPE_IO;
+		else
+			ar |= PEX_OWAR_TYPE_MEM;
+		out_le32(&out_win->ar, ar);
+	}
+
+	out_le32(&pex->bridge.pex_csb_ibctrl, PEX_CSB_IBCTRL_PIOE);
+
+

cpu/mpc83xx/pcie.c line 234

Quoted 10 lines
cpu/mpc83xx/pcie.c new file +9 -0
 
+	printf("PCIE%d: ", bus);
+
+	reg16 = in_le16(hose_cfg_base + PEX_LTSSM_STAT);
+	if (reg16 < 0x16) {
+		printf("No link\n");
+		hose->indirect_type = INDIRECT_TYPE_NO_PCIE_LINK;
+	} else {
+		printf("link\n");
+	}

please remove the bracket on the else

Quoted 23 lines
cpu/mpc83xx/pcie.c new file +14 -0
+
+#ifdef CONFIG_PCI_SCAN_SHOW
+	printf("PCI:   Bus Dev VenId DevId Class Int\n");
+#endif
+
+	/*
+	 * Hose scan.
+	 */
+	hose->last_busno = pci_hose_scan(hose);
+	max_bus = hose->last_busno + 1;
+}
+
+	struct pex_csb_bridge bridge;
+	u8 res12[0x160];
 } pex83xx_t;
 
 /*
include/asm-ppc/mpc83xx_pcie.h new file +0 -0
new file mode 100644
index 0000000..c621ce7

include/asm-ppc/mpc83xx_pcie.h line 9

Quoted 9 lines
include/asm-ppc/mpc83xx_pcie.h new file +9 -0
@@ -0,0 +1,14 @@
+#ifndef __ASM_MPC83XX_PCIE
+#define __ASM_MPC83XX_PCIE
+
+#include <pci.h>
+
+#ifdef CONFIG_PCIE
+extern void mpc83xx_pcie_init(int num_buses, struct pci_region **reg,
+			      int warmboot);
+#else 

        ^

Whitespace please remvoe

include/asm-ppc/mpc83xx_pcie.h line 11

Quoted 2 lines
include/asm-ppc/mpc83xx_pcie.h new file +2 -0
+static void mpc83xx_pcie_init(int num_buses, struct pci_region **reg,
+			      int warmboot) {}

Why not create it as inline?

include/asm-ppc/mpc83xx_pcie.h line 14

Quoted 3 lines
include/asm-ppc/mpc83xx_pcie.h new file +3 -0
+#endif
+
+#endif /* __ASM_MPC83XX_PCIE */

Best Regards,
J.

#3 lore raw

PATCH 1/2 mpc83xx: Add MPC837x PCIE controller RC mode

Quoted 9 lines · Jean-Christophe PLAGNIOL-VILLARD

cpu/mpc83xx/pcie.c line 234

Quoted 8 lines
cpu/mpc83xx/pcie.c new file +8 -0
+
+	reg16 = in_le16(hose_cfg_base + PEX_LTSSM_STAT);
+	if (reg16 < 0x16) {
+		printf("No link\n");
+		hose->indirect_type = INDIRECT_TYPE_NO_PCIE_LINK;
+	} else {
+		printf("link\n");
+	}

please remove the bracket on the else

Come on, this is being ridiculously pedantic.

And wrong by Linux coding style. Quoting from Documentation/CodingStyle

Do not unnecessarily use braces where a single statement will do.

if (condition)

        action();

This does not apply if one branch of a conditional statement is a single statement. Use braces in both branches.

if (condition) {
        do_this();
        do_that();
} else {
        otherwise();
}

Best regards

Markus Klotzbuecher

--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de

#4 lore raw

PATCH 1/2 mpc83xx: Add MPC837x PCIE controller RC mode

Quoted 12 lines · Markus Klotzb?cher
Quoted 9 lines · Jean-Christophe PLAGNIOL-VILLARD

cpu/mpc83xx/pcie.c line 234

Quoted 8 lines
cpu/mpc83xx/pcie.c new file +8 -0
+
+	reg16 = in_le16(hose_cfg_base + PEX_LTSSM_STAT);
+	if (reg16 < 0x16) {
+		printf("No link\n");
+		hose->indirect_type = INDIRECT_TYPE_NO_PCIE_LINK;
+	} else {
+		printf("link\n");
+	}

please remove the bracket on the else

Quoted 1 line

Come on, this is being ridiculously pedantic.

Absolutely agree.

In my opinion, extra braces should just acceptable and even encouraged.

jdl