ADS5121 IO Pin Configuration

Adds configurable IO Pin initialization for ADS5121 and consolidates existing IO pin initialization.

---
 board/ads5121/ads5121.c   |   10 +--
 cpu/mpc512x/Makefile      |    2 +-
 cpu/mpc512x/fec.c         |   15 ----
 cpu/mpc512x/iopin.c       |   72 ++++++++++++++++
 cpu/mpc512x/iopin.h       |  200
+++++++++++++++++++++++++++++++++++++++++++++
 include/configs/ads5121.h |    1 +
 6 files changed, 277 insertions(+), 23 deletions(-)
 create mode 100644 cpu/mpc512x/iopin.c
 create mode 100644 cpu/mpc512x/iopin.h

index 35544f1..69bf4b5 100644
@@ -47,6 +47,7 @@
 #define CSAW_STOP(start, size)	(((start) + (size) - 1) >> 16)
 
 long int fixed_sdram(void);
+extern void iopin_initialize (void);
 
 int board_early_init_f (void)
 {

@@ -204,17 +205,12 @@ int checkboard (void)
 {
 	ushort brd_rev = *(vu_short *) (CFG_CPLD_BASE + 0x00);
 	uchar cpld_rev = *(vu_char *) (CFG_CPLD_BASE + 0x02);
-	volatile immap_t *im = (immap_t *) CFG_IMMR;
-	volatile unsigned long *reg;
-	int i;
 
 	printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
 		brd_rev, cpld_rev);
+	/* initialize function mux & slew rate IO inter alia on IO Pins

*/
+ iopin_initialize();

- /* change the slew rate on all pata pins to max */
- reg = (unsigned long *) &(im->io_ctrl.regs[PATA_CE1_IDX]);
- for (i = 0; i < 9; i++)
- reg[i] |= 0x00000003;
return 0;
}
#ifdef CONFIG_MISC_INIT_R

index 2be35b2..8ba8ae8 100644
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(CPU).a
 
 START	= start.o
-COBJS	= traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o fec.o i2c.o
+COBJS	= traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o fec.o i2c.o

iopin.o

SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))

index c226a8a..e9df7de 100644
@@ -604,13 +604,10 @@ static int mpc512x_fec_recv (struct eth_device *dev)
 /********************************************************************/
 int mpc512x_fec_initialize (bd_t * bis)
 {
-
-	immap_t *im = (immap_t*) CFG_IMMR;
 	mpc512x_fec_priv *fec;
 	struct eth_device *dev;
 	int i;
 	char *tmp, *end, env_enetaddr[6];
-	uint32 *reg;
 	void * bd;
 
 	fec = (mpc512x_fec_priv *) malloc (sizeof(*fec));

@@ -639,18 +636,6 @@ int mpc512x_fec_initialize (bd_t * bis)
 			fec512x_miiphy_read, fec512x_miiphy_write);
 #endif
 
-	/*
-	 * Initialize I\O pins
-	 */
-	reg = (uint32 *) &(im->io_ctrl.regs[PSC0_0_IDX]);
-
-	for (i = 0; i < 15; i++)
-		reg[i] = IOCTRL_MUX_FEC | 0x00000001;
-
-	im->io_ctrl.regs[SPDIF_TXCLOCK_IDX] = IOCTRL_MUX_FEC | 0x00000001;
-	im->io_ctrl.regs[SPDIF_TX_IDX] = IOCTRL_MUX_FEC | 0x00000001;
-	im->io_ctrl.regs[SPDIF_RX_IDX] = IOCTRL_MUX_FEC | 0x00000001;
-
 	/* Clean up space FEC's MIB and FIFO RAM ...*/
 	memset ((void *) MPC512X_FEC + 0x200, 0x00, 0x400);
 

new file mode 100644
index 0000000..e2b536b
@@ -0,0 +1,72 @@
+/*
+ * mpc512x I/O pin/pad initialization
+ */
+#include <common.h>
+#include <linux/types.h>
+#include "iopin.h"
+
+/*
+ * IO PAD TYPES for all types fmux is used to select the funtion and ds

sets the slew rate
+ * STD nothing extra (can set ds & fmux only)
+ * STD_PU pue=1 to enable the pull & pud sets whether up or down
resistors
+ * STD_ST can set the Schmitt trigger
+ * STD_PU_ST pue & pud sets pull-up/down resistors & st sets the
Schmitt trigger
+ * PCI hold sets output delay
+ * PCI_ST hold sets output delay and st sets the Schmitt trigger
+ */
+static struct iopin_t {
+ u_short p_offset; /* offset from IOCTL_MEM_OFFSET
*/
+ u_short p_no; /* number of pins to set this way
*/
+ u_short bit_or:7; /* Do bitwise OR instead of setting
*/
+ u_short fmux:2; /* pad function select 0-3
*/
+ u_short hold:2; /* PCI pad types only;
*/
+ u_short pud:1; /* pull resistor; PU types only;
*/
+ /* if pue=1 then 0=pull-down, 1=pull-up
*/
+ u_short pue:1; /* Pull resistor enable; _PU types only
*/
+ u_short st:1; /* Schmitt trigger enable; _ST types only
*/
+ u_short ds:2; /* Slew rate class, 0=class1, ..., 3=class4
*/
+ } ioregs_init[] = {
+#ifdef CONFIG_ADS5121
+/* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
+ {IOCTL_SPDIF_TXCLK, 3, 0, 1, 0, 0, 0, 0, 3},
+/* Set highest Slew on 9 PATA pins */
+ {IOCTL_PATA_CE1, 9, 1, 0, 0, 0, 0, 0, 3},
+/* FUNC1=FEC_COL Sets Next 15 to FEC pads */
+ {IOCTL_PSC0_0, 15, 0, 1, 0, 0, 0, 0, 3},
+/* FUNC1=SPDIF_TXCLK */
+ {IOCTL_LPC_CS1, 1, 0, 1, 0, 0, 0, 1, 3},
+/* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
+ {IOCTL_I2C1_SCL, 2, 0, 2, 0, 0, 0, 1, 3},
+/* FUNC2=DIU CLK */
+ {IOCTL_PSC6_0, 1, 0, 2, 0, 0, 0, 1, 3},
+/* FUNC2=DIU_HSYNC */
+ {IOCTL_PSC6_1, 1, 0, 2, 0, 0, 0, 0, 3},
+/* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
+ {IOCTL_PSC6_4, 26, 0, 2, 0, 0, 0, 0, 3}
+#endif
+ };
+
+void iopin_initialize(void)
+{
+ short i, j, n, p;
+ u_long *reg;
+
+ if (sizeof(ioregs_init) == 0)
+ return;
+
+ immap_t *im = (immap_t *)CFG_IMMR;
+ reg = (u_long *)&(im->io_ctrl.regs[0]);
+ n = sizeof(ioregs_init) / sizeof(ioregs_init[0]);
+
+ for (i = 0; i < n; i++) {
+ for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long);
+ p < ioregs_init[i].p_no; p++, j++) {
+ /* lowest 9 bits sets the register */
+ if (ioregs_init[i].bit_or)
+ reg[j] |= *((u_long *) &ioregs_init[i].p_no)
& 0x000001ff;
+ else
+ reg[j] = *((u_long *) &ioregs_init[i].p_no)
& 0x000001ff;
+ }
+ }
+ return;
+}

index 5f82855..04b2a96 100644
@@ -27,6 +27,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_ADS5121 1
 /*
  * Memory map for the ADS5121 board:
  *

1.5.2.4

Please add a correct sob

Your patch is corrupted by your e-mail client
please use git-send-email

and you add some whitespaces >20

Please fix adn resubmit

Best Regards,
J.

^^^^^^^^^^^^^^^^^^^^^^^

Patch again corrupted due to line wrapping.

^^^^^^^^^^^^^^^^^^^^^
Lines wrapped.

^^^^^^^^^^^^^^^^^^^^^
Lines wrapped.

Also, please keep lisys sorted, and mind the maximum line length.

^^^^^^^^^^^^^^^^^^^^^
Lines wrapped (many more lines following).

+ } ioregs_init[] = {
+#ifdef CONFIG_ADS5121
+/* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
+ {IOCTL_SPDIF_TXCLK, 3, 0, 1, 0, 0, 0, 0, 3},
+/* Set highest Slew on 9 PATA pins */
+ {IOCTL_PATA_CE1, 9, 1, 0, 0, 0, 0, 0, 3},
+/* FUNC1=FEC_COL Sets Next 15 to FEC pads */
+ {IOCTL_PSC0_0, 15, 0, 1, 0, 0, 0, 0, 3},
+/* FUNC1=SPDIF_TXCLK */
+ {IOCTL_LPC_CS1, 1, 0, 1, 0, 0, 0, 1, 3},
+/* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
+ {IOCTL_I2C1_SCL, 2, 0, 2, 0, 0, 0, 1, 3},
+/* FUNC2=DIU CLK */
+ {IOCTL_PSC6_0, 1, 0, 2, 0, 0, 0, 1, 3},
+/* FUNC2=DIU_HSYNC */
+ {IOCTL_PSC6_1, 1, 0, 2, 0, 0, 0, 0, 3},
+/* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
+ {IOCTL_PSC6_4, 26, 0, 2, 0, 0, 0, 0, 3}
+#endif

No. Please avoid such board specific #ifdef'ed initializers in common code. Please move this board specific data into board specific files.

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The reasonable man adapts himself to the world; the unreasonable  one
persists  in  trying  to  adapt  the  world to himself. Therefore all
progress depends on the unreasonable man."      - George Bernard Shaw