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S3C64XX support (v2)

RFC PATCH New Kyungmin Park 1 participant 1 message Dec 16, 2008

Subsystems (4)
Arm (32-bit) Arm sub-architectures Memory technology devices (MTD) Arm Samsung Exynos
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Kyungmin Park

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RFC PATCH 1/1 S3C64XX support (v2)

S3C64XX has its own OneNAND controller and interface To do this there are two choices, New implementation or hook the required function

In this implementation I choose latter.
To work with current OneNAND, I emulate the BufferRAM at system memory So it's not need to modify OneNAND base file as previous one

This patch will be merged after s3c64xx kernel tree merged.

Note:
header file will be located at arch/arm/plat-s3c64xx/include/plat But this patch doesn't since there's no plat-s3c64xx
Also cpu_is_s3c64xx and cpu_is_s3c6400 is simply redefined as same reason.

Thank you,
Kyungmin Park

Signed-off-by Kyungmin Park <[email protected]>

---

arch/arm/plat-s3c/include/plat/regs-onenand.h new file +88 -0
new file mode 100644
index 0000000..6087866
@@ -0,0 +1,88 @@
+/*
+ * linux/arch/arm/plat-s3c64xx/include/plat/regs-onenand.h
+ *
+ *  Copyright (C) 2008 Samsung Electronics
+ *  Kyungmin Park <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __S3C64XX_ONENAND_H__
+#define __S3C64XX_ONENAND_H__
+
+#include <mach/hardware.h>
+
+/*
+ * OneNAND Controller
+ */
+#define S3C64XX_ONENAND0_BASE	0x70100000
+#define S3C64XX_ONENAND1_BASE	0x70200000
+
+#define MEM_CFG_OFFSET		0x0000
+#define BURST_LEN_OFFSET	0x0010
+#define MEM_RESET_OFFSET	0x0020
+#define INT_ERR_STAT_OFFSET	0x0030
+#define INT_ERR_MASK_OFFSET	0x0040
+#define INT_ERR_ACK_OFFSET	0x0050
+#define ECC_ERR_STAT_OFFSET	0x0060
+#define MANUFACT_ID_OFFSET	0x0070
+#define DEVICE_ID_OFFSET	0x0080
+#define DATA_BUF_SIZE_OFFSET	0x0090
+#define BOOT_BUF_SIZE_OFFSET	0x00A0
+#define BUF_AMOUNT_OFFSET	0x00B0
+#define TECH_OFFSET		0x00C0
+#define FBA_WIDTH_OFFSET	0x00D0
+#define FPA_WIDTH_OFFSET	0x00E0
+#define FSA_WIDTH_OFFSET	0x00F0
+#define TRANS_SPARE_OFFSET	0x0140
+#define DBS_DFS_WIDTH_OFFSET	0x0160
+#define INT_PIN_ENABLE_OFFSET	0x01A0
+#define ACC_CLOCK_OFFSET	0x01C0
+#define FLASH_VER_ID_OFFSET	0x01F0
+#define FLASH_AUX_CNTRL_OFFSET	0x0300
+
+#ifndef __KERNEL__
+#define MEM_CFG0_REG		__REG(S3C64XX_ONENAND0_BASE + MEM_CFG_OFFSET)
+#define BURST_LEN0_REG		__REG(S3C64XX_ONENAND0_BASE + BURST_LEN_OFFSET)
+#define MEM_RESET0_REG		__REG(S3C64XX_ONENAND0_BASE + MEM_RESET_OFFSET)
+#define INT_ERR_STAT0_REG	__REG(S3C64XX_ONENAND0_BASE + INT_ERR_STAT_OFFSET)
+#define INT_ERR_MASK0_REG	__REG(S3C64XX_ONENAND0_BASE + INT_ERR_MASK_OFFSET)
+#define INT_ERR_ACK0_REG	__REG(S3C64XX_ONENAND0_BASE + INT_ERR_ACK_OFFSET)
+#define ECC_ERR_STAT0_REG	__REG(S3C64XX_ONENAND0_BASE + ECC_ERR_STAT_OFFSET)
+#define MANUFACT_ID0_REG	__REG(S3C64XX_ONENAND0_BASE + MANUFACT_ID_OFFSET)
+#define DEVICE_ID0_REG		__REG(S3C64XX_ONENAND0_BASE + DEVICE_ID_OFFSET)
+#define DATA_BUF_SIZE0_REG	__REG(S3C64XX_ONENAND0_BASE + DATA_BUF_SIZE_OFFSET)
+#define FBA_WIDTH0_REG		__REG(S3C64XX_ONENAND0_BASE + FBA_WIDTH_OFFSET)
+#define FPA_WIDTH0_REG		__REG(S3C64XX_ONENAND0_BASE + FPA_WIDTH_OFFSET)
+#define FSA_WIDTH0_REG		__REG(S3C64XX_ONENAND0_BASE + FSA_WIDTH_OFFSET)
+#define TRANS_SPARE0_REG	__REG(S3C64XX_ONENAND0_BASE + TRANS_SPARE_OFFSET)
+#define DBS_DFS_WIDTH0_REG	__REG(S3C64XX_ONENAND0_BASE + DBS_DFS_WIDTH_OFFSET)
+#define INT_PIN_ENABLE0_REG	__REG(S3C64XX_ONENAND0_BASE + INT_PIN_ENABLE_OFFSET)
+#define ACC_CLOCK0_REG		__REG(S3C64XX_ONENAND0_BASE + ACC_CLOCK_OFFSET)
+#define FLASH_VER_ID0_REG	__REG(S3C64XX_ONENAND0_BASE + FLASH_VER_ID_OFFSET)
+#define FLASH_AUX_CNTRL0_REG	__REG(S3C64XX_ONENAND0_BASE + FLASH_AUX_CNTRL_OFFSET)
+#endif
+
+#define ONENAND_MEM_RESET_HOT	0x3
+#define ONENAND_MEM_RESET_COLD	0x2
+#define ONENAND_MEM_RESET_WARM	0x1
+
+#define CACHE_OP_ERR		(1 << 13)
+#define RST_CMP			(1 << 12)
+#define RDY_ACT			(1 << 11)
+#define INT_ACT			(1 << 10)
+#define UNSUP_CMD		(1 << 9)
+#define LOCKED_BLK		(1 << 8)
+#define BLK_RW_CMP		(1 << 7)
+#define ERS_CMP			(1 << 6)
+#define PGM_CMP			(1 << 5)
+#define LOAD_CMP		(1 << 4)
+#define ERS_FAIL		(1 << 3)
+#define PGM_FAIL		(1 << 2)
+#define INT_TO			(1 << 1)
+#define LD_FAIL_ECC_ERR		(1 << 0)
+
+#define TSRF			(1 << 0)
+
+#endif
drivers/mtd/onenand/Kconfig +8 -0
index 0c8fa54..dfcb4be 100644
@@ -34,6 +34,14 @@ config MTD_ONENAND_OMAP2
 	  Support for a OneNAND flash device connected to an OMAP2/OMAP3 CPU
 	  via the GPMC memory controller.
 
+config MTD_ONENAND_S3C64XX
+	tristate "OneNAND on S3C64XX support"
+	depends on MTD_ONENAND && ARCH_S3C64XX
+	help
+	  Support for a OneNAND flash device connected to an S3C64XX CPU
+	  via the Denali OneNAND controller.
+
+
 config MTD_ONENAND_OTP
 	bool "OneNAND OTP Support"
 	select HAVE_MTD_OTP
drivers/mtd/onenand/Makefile +2 -0
index 64b6cc6..3e1ac5f 100644
@@ -8,6 +8,8 @@ obj-$(CONFIG_MTD_ONENAND)		+= onenand.o
 # Board specific.
 obj-$(CONFIG_MTD_ONENAND_GENERIC)	+= generic.o
 obj-$(CONFIG_MTD_ONENAND_OMAP2)		+= omap2.o
+#obj-$(CONFIG_MTD_ONENAND_S3C64XX)	+= s3c64xx.o
+obj-y					+= s3c64xx.o
 
 # Simulator
 obj-$(CONFIG_MTD_ONENAND_SIM)		+= onenand_sim.o
drivers/mtd/onenand/s3c64xx.c new file +694 -0

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