OMAP3: update omap_chip flags; mark USBTLL SAR for ES3.1 only

PATCH New Paul Walmsley 1 participant 3 messages Jan 29, 2009

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Arm (32-bit) Arm sub-architectures OMAP2+ support OMAP clock framework support

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Paul Walmsley

author maintainer

2009-01-29 09:16 UTC #0 lore raw

cover OMAP3: update omap_chip flags; mark USBTLL SAR for ES3.1 only

Hello,

this series marks USBTLL SAR as being available on ES3.1 and beyond only, per

http://marc.info/?l=linux-arm-kernel&m=123319614808833&w=2

To do this, the omap_chip flags had to be updated. Now, ES2+ features are marked as CHIP_GE_OMAP3430ES2. ES3.1+ features are similarly marked as CHIP_GE_OMAP3430ES3_1.

Tested on ES2.1 Beagle. Further testing on ES3+ boards is very welcome.

---

Paul Walmsley (2):
OMAP3 powerdomains: make USBTLL SAR only available on ES3.1 and beyond
OMAP3: update ES level flags to discriminate between post-ES2 revisions

 arch/arm/mach-omap2/clockdomains.h     |    6 +++---
 arch/arm/mach-omap2/id.c               |    7 ++++++-
 arch/arm/mach-omap2/powerdomains.h     |    4 ++--
 arch/arm/mach-omap2/powerdomains34xx.h |   16 +++++++++-------
 arch/arm/plat-omap/include/mach/cpu.h  |   26 ++++++++++++++++++++------
 5 files changed, 40 insertions(+), 19 deletions(-)

Paul Walmsley

author maintainer

2009-01-29 09:16 UTC #1 lore raw

PATCH 1/2 OMAP3: update ES level flags to discriminate between post-ES2 revisions

Some OMAP3 chip behaviors change in ES levels after ES2. Modify the existing omap_chip flags to add options for ES3.0 and ES3.1.

Add a new macro, CHIP_GE_OMAP3430ES2, to cover ES levels from ES2 onwards - a common pattern for OMAP3 features. Update all current users of the omap_chip macros to use this new macro.

Also add CHIP_GE_OMAP3430ES3_1 to cover the USBTLL SAR errata case (described and fixed in the following patch)

Signed-off-by Paul Walmsley <[email protected]>

---
 arch/arm/mach-omap2/clockdomains.h     |    6 +++---
 arch/arm/mach-omap2/id.c               |    7 ++++++-
 arch/arm/mach-omap2/powerdomains34xx.h |    8 ++++----
 arch/arm/plat-omap/include/mach/cpu.h  |   26 ++++++++++++++++++++------
 4 files changed, 33 insertions(+), 14 deletions(-)

arch/arm/mach-omap2/clockdomains.h +3 -3

index 3d4eaca..a21df93 100644
@@ -185,7 +185,7 @@ static struct clockdomain sgx_clkdm = {
 	.pwrdm		= { .name = "sgx_pwrdm" },
 	.flags		= CLKDM_CAN_HWSUP_SWSUP,
 	.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
-	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
 };
 
 /*

@@ -240,7 +240,7 @@ static struct clockdomain usbhost_clkdm = {
 	.pwrdm		= { .name = "usbhost_pwrdm" },
 	.flags		= CLKDM_CAN_HWSUP_SWSUP,
 	.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
-	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
 };
 
 static struct clockdomain per_clkdm = {

@@ -290,7 +290,7 @@ static struct clockdomain dpll4_clkdm = {
 static struct clockdomain dpll5_clkdm = {
 	.name		= "dpll5_clkdm",
 	.pwrdm		= { .name = "dpll5_pwrdm" },
-	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
 };
 
 #endif   /* CONFIG_ARCH_OMAP34XX */

arch/arm/mach-omap2/id.c +6 -1

index 7cd1b2e..32ceaa6 100644
@@ -239,8 +239,13 @@ void __init omap2_check_revision(void)
 		omap_chip.oc = CHIP_IS_OMAP3430;
 		if (omap_rev() == OMAP3430_REV_ES1_0)
 			omap_chip.oc |= CHIP_IS_OMAP3430ES1;
-		else if (omap_rev() > OMAP3430_REV_ES1_0)
+		else if (omap_rev() >= OMAP3430_REV_ES2_0 &&
+			 omap_rev() <= OMAP3430_REV_ES2_1)
 			omap_chip.oc |= CHIP_IS_OMAP3430ES2;
+		else if (omap_rev() == OMAP3430_REV_ES3_0)
+			omap_chip.oc |= CHIP_IS_OMAP3430ES3_0;
+		else if (omap_rev() == OMAP3430_REV_ES3_1)
+			omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
 	} else {
 		pr_err("Uninitialized omap_chip, please fix!\n");
 	}

arch/arm/mach-omap2/powerdomains34xx.h +4 -4

index edfad42..6b9d126 100644
@@ -221,7 +221,7 @@ static struct powerdomain core_34xx_es1_pwrdm = {
 static struct powerdomain core_34xx_es2_pwrdm = {
 	.name		  = "core_pwrdm",
 	.prcm_offs	  = CORE_MOD,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
 	.pwrsts		  = PWRSTS_OFF_RET_ON,
 	.dep_bit	  = OMAP3430_EN_CORE_SHIFT,
 	.flags		  = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */

@@ -263,7 +263,7 @@ static struct powerdomain dss_pwrdm = {
 static struct powerdomain sgx_pwrdm = {
 	.name		  = "sgx_pwrdm",
 	.prcm_offs	  = OMAP3430ES2_SGX_MOD,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
 	.wkdep_srcs	  = gfx_sgx_wkdeps,
 	.sleepdep_srcs	  = cam_gfx_sleepdeps,
 	/* XXX This is accurate for 3430 SGX, but what about GFX? */

@@ -331,7 +331,7 @@ static struct powerdomain neon_pwrdm = {
 static struct powerdomain usbhost_pwrdm = {
 	.name		  = "usbhost_pwrdm",
 	.prcm_offs	  = OMAP3430ES2_USBHOST_MOD,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
 	.wkdep_srcs	  = per_usbhost_wkdeps,
 	.sleepdep_srcs	  = dss_per_usbhost_sleepdeps,
 	.pwrsts		  = PWRSTS_OFF_RET_ON,

@@ -373,7 +373,7 @@ static struct powerdomain dpll4_pwrdm = {
 static struct powerdomain dpll5_pwrdm = {
 	.name		= "dpll5_pwrdm",
 	.prcm_offs	= PLL_MOD,
-	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
 };

arch/arm/plat-omap/include/mach/cpu.h +20 -6

index a8e1178..40d1196 100644
@@ -355,13 +355,27 @@ IS_OMAP_TYPE(3430, 0x3430)
  * use omap_chip_is().
  *
  */
-#define CHIP_IS_OMAP2420       (1 << 0)
-#define CHIP_IS_OMAP2430       (1 << 1)
-#define CHIP_IS_OMAP3430       (1 << 2)
-#define CHIP_IS_OMAP3430ES1    (1 << 3)
-#define CHIP_IS_OMAP3430ES2    (1 << 4)
+#define CHIP_IS_OMAP2420		(1 << 0)
+#define CHIP_IS_OMAP2430		(1 << 1)
+#define CHIP_IS_OMAP3430		(1 << 2)
+#define CHIP_IS_OMAP3430ES1		(1 << 3)
+#define CHIP_IS_OMAP3430ES2		(1 << 4)
+#define CHIP_IS_OMAP3430ES3_0		(1 << 5)
+#define CHIP_IS_OMAP3430ES3_1		(1 << 6)
+
+#define CHIP_IS_OMAP24XX		(CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
+
+/* 
+ * "GE" here represents "greater than or equal to" in terms of ES
+ * levels.  So CHIP_GE_OMAP3430ES2 is intended to match all OMAP3430
+ * chips at ES2 and beyond, but not, for example, any OMAP lines after
+ * OMAP3.
+ */
+#define CHIP_GE_OMAP3430ES2		(CHIP_IS_OMAP3430ES2 | \
+					 CHIP_IS_OMAP3430ES3_0 | \
+					 CHIP_IS_OMAP3430ES3_1)
+#define CHIP_GE_OMAP3430ES3_1		(CHIP_IS_OMAP3430ES3_1)
 
-#define CHIP_IS_OMAP24XX       (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
 
 int omap_chip_is(struct omap_chip_id oci);
 int omap_type(void);

Paul Walmsley

author maintainer

2009-01-29 09:16 UTC #2 lore raw

PATCH 2/2 OMAP3 powerdomains: make USBTLL SAR only available on ES3.1 and beyond

In reply to Paul Walmsley

Richard Woodruff writes that chip errata prevent USBTLL SAR from working on OMAP3 ES levels before ES3.1:

http://marc.info/?l=linux-arm-kernel&m=123319614808833&w=2

Update the OMAP3 powerdomain structures appropriately.

Signed-off-by Paul Walmsley <[email protected]>

Cc Richard Woodruff <[email protected]>

---
 arch/arm/mach-omap2/powerdomains.h     |    4 ++--
 arch/arm/mach-omap2/powerdomains34xx.h |   10 ++++++----
 2 files changed, 8 insertions(+), 6 deletions(-)

arch/arm/mach-omap2/powerdomains.h +2 -2

index 51623e2..691470e 100644
@@ -171,8 +171,8 @@ static struct powerdomain *powerdomains_omap[] __initdata = {
 	&iva2_pwrdm,
 	&mpu_34xx_pwrdm,
 	&neon_pwrdm,
-	&core_34xx_es1_pwrdm,
-	&core_34xx_es2_pwrdm,
+	&core_34xx_pre_es3_1_pwrdm,
+	&core_34xx_es3_1_pwrdm,
 	&cam_pwrdm,
 	&dss_pwrdm,
 	&per_pwrdm,

arch/arm/mach-omap2/powerdomains34xx.h +6 -4

index 6b9d126..4dcf94b 100644
@@ -200,10 +200,12 @@ static struct powerdomain mpu_34xx_pwrdm = {
 };
 
 /* No wkdeps or sleepdeps for 34xx core apparently */
-static struct powerdomain core_34xx_es1_pwrdm = {
+static struct powerdomain core_34xx_pre_es3_1_pwrdm = {
 	.name		  = "core_pwrdm",
 	.prcm_offs	  = CORE_MOD,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
+					   CHIP_IS_OMAP3430ES2 |
+					   CHIP_IS_OMAP3430ES3_0),
 	.pwrsts		  = PWRSTS_OFF_RET_ON,
 	.dep_bit	  = OMAP3430_EN_CORE_SHIFT,
 	.banks		  = 2,

@@ -218,10 +220,10 @@ static struct powerdomain core_34xx_es1_pwrdm = {
 };
 
 /* No wkdeps or sleepdeps for 34xx core apparently */
-static struct powerdomain core_34xx_es2_pwrdm = {
+static struct powerdomain core_34xx_es3_1_pwrdm = {
 	.name		  = "core_pwrdm",
 	.prcm_offs	  = CORE_MOD,
-	.omap_chip	  = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
+	.omap_chip	  = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1),
 	.pwrsts		  = PWRSTS_OFF_RET_ON,
 	.dep_bit	  = OMAP3430_EN_CORE_SHIFT,
 	.flags		  = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */