sh: multiple vectors per irq - sh7780
PATCH 3/4 sh: multiple vectors per irq - sh7780
From: Magnus Damm <[email protected]>
Update intc tables and platform data to use one linux irq per maskable interrupt source instead of keeping the one-to-one mapping between vectors and linux irqs.
This fixes potential irq masking issues for sh7780 hardware blocks such as SCIF/RTC/DMAC/PCIC5/MMCIF/FLCTL/GPIO
Signed-off-by Magnus Damm <[email protected]>
---
Depends on the sh-rtc-single-irq-support patch.
Tested on a r7780mp board.
arch/sh/kernel/cpu/sh4a/setup-sh7780.c | 97 +++++++++----------------------- 1 file changed, 30 insertions(+), 67 deletions(-)
arch/sh/kernel/cpu/sh4a/setup-sh7780.c +30 -67
@@ -20,17 +20,7 @@ static struct resource rtc_resources[] .flags = IORESOURCE_IO, }, [1] = { - /* Period IRQ */ - .start = 21, - .flags = IORESOURCE_IRQ, - }, - [2] = { - /* Carry IRQ */ - .start = 22, - .flags = IORESOURCE_IRQ, - }, - [3] = { - /* Alarm IRQ */ +/* Shared Period/Carry/Alarm IRQ */ .start = 20, .flags = IORESOURCE_IRQ, },
@@ -48,12 +38,12 @@ static struct plat_sci_port sci_platform .mapbase = 0xffe00000, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, - .irqs = { 40, 41, 43, 42 }, + .irqs = { 40, 40, 40, 40 }, }, { .mapbase =0xffe10000 , .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, - .irqs = { 76, 77, 79, 78 }, + .irqs = { 76, 76, 76, 76 }, }, { .flags = 0, }
@@ -90,82 +80,55 @@ enum {IRL_HHLL ,IRL_HHLH ,IRL_HHHL ,IRQ0 ,IRQ1 ,IRQ2 ,IRQ3 ,IRQ4 ,IRQ5 ,IRQ6 ,IRQ7 , -RTC_ATI ,RTC_PRI ,RTC_CUI , -WDT , -TMU0 ,TMU1 ,TMU2 ,TMU2_TICPI , -HUDI , -DMAC0_DMINT0 ,DMAC0_DMINT1 ,DMAC0_DMINT2 ,DMAC0_DMINT3 ,DMAC0_DMAE , -SCIF0_ERI ,SCIF0_RXI ,SCIF0_BRI ,SCIF0_TXI , -DMAC0_DMINT4 ,DMAC0_DMINT5 ,DMAC1_DMINT6 ,DMAC1_DMINT7 , -CMT ,HAC , -PCISERR ,PCIINTA ,PCIINTB ,PCIINTC ,PCIINTD , -PCIERR ,PCIPWD3 ,PCIPWD2 ,PCIPWD1 ,PCIPWD0 , -SCIF1_ERI ,SCIF1_RXI ,SCIF1_BRI ,SCIF1_TXI , -SIOF ,HSPI , -MMCIF_FSTAT ,MMCIF_TRAN ,MMCIF_ERR ,MMCIF_FRDY , -DMAC1_DMINT8 ,DMAC1_DMINT9 ,DMAC1_DMINT10 ,DMAC1_DMINT11 , -TMU3 ,TMU4 ,TMU5 , -SSI , -FLCTL_FLSTE ,FLCTL_FLEND ,FLCTL_FLTRQ0 ,FLCTL_FLTRQ1 , -GPIOI0 ,GPIOI1 ,GPIOI2 ,GPIOI3 , +RTC ,WDT ,TMU0 ,TMU1 ,TMU2 ,TMU2_TICPI , +HUDI ,DMAC0 ,SCIF0 ,DMAC1 ,CMT ,HAC , +PCISERR ,PCIINTA ,PCIINTB ,PCIINTC ,PCIINTD ,PCIC5 , +SCIF1 ,SIOF ,HSPI ,MMCIF ,TMU3 ,TMU4 ,TMU5 ,SSI ,FLCTL ,GPIO ,/* interrupt groups */ -RTC ,TMU012 ,DMAC0 ,SCIF0 ,DMAC45 ,DMAC1 , - PCIC5, SCIF1, MMCIF, TMU345, FLCTL, GPIO, + TMU012, TMU345, };static struct intc_vect vectors[]__initdata = { -INTC_VECT (RTC_ATI ,0x480 ),INTC_VECT (RTC_PRI ,0x4a0 ), -INTC_VECT (RTC_CUI ,0x4c0 ), +INTC_VECT (RTC ,0x480 ),INTC_VECT (RTC ,0x4a0 ), +INTC_VECT (RTC ,0x4c0 ),INTC_VECT (WDT ,0x560 ),INTC_VECT (TMU0 ,0x580 ),INTC_VECT (TMU1 ,0x5a0 ),INTC_VECT (TMU2 ,0x5c0 ),INTC_VECT (TMU2_TICPI ,0x5e0 ),INTC_VECT (HUDI ,0x600 ), -INTC_VECT (DMAC0_DMINT0 ,0x640 ),INTC_VECT (DMAC0_DMINT1 ,0x660 ), -INTC_VECT (DMAC0_DMINT2 ,0x680 ),INTC_VECT (DMAC0_DMINT3 ,0x6a0 ), -INTC_VECT (DMAC0_DMAE ,0x6c0 ), -INTC_VECT (SCIF0_ERI ,0x700 ),INTC_VECT (SCIF0_RXI ,0x720 ), -INTC_VECT (SCIF0_BRI ,0x740 ),INTC_VECT (SCIF0_TXI ,0x760 ), -INTC_VECT (DMAC0_DMINT4 ,0x780 ),INTC_VECT (DMAC0_DMINT5 ,0x7a0 ), -INTC_VECT (DMAC1_DMINT6 ,0x7c0 ),INTC_VECT (DMAC1_DMINT7 ,0x7e0 ), +INTC_VECT (DMAC0 ,0x640 ),INTC_VECT (DMAC0 ,0x660 ), +INTC_VECT (DMAC0 ,0x680 ),INTC_VECT (DMAC0 ,0x6a0 ), +INTC_VECT (DMAC0 ,0x6c0 ), +INTC_VECT (SCIF0 ,0x700 ),INTC_VECT (SCIF0 ,0x720 ), +INTC_VECT (SCIF0 ,0x740 ),INTC_VECT (SCIF0 ,0x760 ), +INTC_VECT (DMAC0 ,0x780 ),INTC_VECT (DMAC0 ,0x7a0 ), +INTC_VECT (DMAC1 ,0x7c0 ),INTC_VECT (DMAC1 ,0x7e0 ),INTC_VECT (CMT ,0x900 ),INTC_VECT (HAC ,0x980 ),INTC_VECT (PCISERR ,0xa00 ),INTC_VECT (PCIINTA ,0xa20 ),INTC_VECT (PCIINTB ,0xa40 ),INTC_VECT (PCIINTC ,0xa60 ), -INTC_VECT (PCIINTD ,0xa80 ),INTC_VECT (PCIERR ,0xaa0 ), -INTC_VECT (PCIPWD3 ,0xac0 ),INTC_VECT (PCIPWD2 ,0xae0 ), -INTC_VECT (PCIPWD1 ,0xb00 ),INTC_VECT (PCIPWD0 ,0xb20 ), -INTC_VECT (SCIF1_ERI ,0xb80 ),INTC_VECT (SCIF1_RXI ,0xba0 ), -INTC_VECT (SCIF1_BRI ,0xbc0 ),INTC_VECT (SCIF1_TXI ,0xbe0 ), +INTC_VECT (PCIINTD ,0xa80 ),INTC_VECT (PCIC5 ,0xaa0 ), +INTC_VECT (PCIC5 ,0xac0 ),INTC_VECT (PCIC5 ,0xae0 ), +INTC_VECT (PCIC5 ,0xb00 ),INTC_VECT (PCIC5 ,0xb20 ), +INTC_VECT (SCIF1 ,0xb80 ),INTC_VECT (SCIF1 ,0xba0 ), +INTC_VECT (SCIF1 ,0xbc0 ),INTC_VECT (SCIF1 ,0xbe0 ),INTC_VECT (SIOF ,0xc00 ),INTC_VECT (HSPI ,0xc80 ), -INTC_VECT (MMCIF_FSTAT ,0xd00 ),INTC_VECT (MMCIF_TRAN ,0xd20 ), -INTC_VECT (MMCIF_ERR ,0xd40 ),INTC_VECT (MMCIF_FRDY ,0xd60 ), -INTC_VECT (DMAC1_DMINT8 ,0xd80 ),INTC_VECT (DMAC1_DMINT9 ,0xda0 ), -INTC_VECT (DMAC1_DMINT10 ,0xdc0 ),INTC_VECT (DMAC1_DMINT11 ,0xde0 ), +INTC_VECT (MMCIF ,0xd00 ),INTC_VECT (MMCIF ,0xd20 ), +INTC_VECT (MMCIF ,0xd40 ),INTC_VECT (MMCIF ,0xd60 ), +INTC_VECT (DMAC1 ,0xd80 ),INTC_VECT (DMAC1 ,0xda0 ), +INTC_VECT (DMAC1 ,0xdc0 ),INTC_VECT (DMAC1 ,0xde0 ),INTC_VECT (TMU3 ,0xe00 ),INTC_VECT (TMU4 ,0xe20 ),INTC_VECT (TMU5 ,0xe40 ),INTC_VECT (SSI ,0xe80 ), -INTC_VECT (FLCTL_FLSTE ,0xf00 ),INTC_VECT (FLCTL_FLEND ,0xf20 ), -INTC_VECT (FLCTL_FLTRQ0 ,0xf40 ),INTC_VECT (FLCTL_FLTRQ1 ,0xf60 ), -INTC_VECT (GPIOI0 ,0xf80 ),INTC_VECT (GPIOI1 ,0xfa0 ), -INTC_VECT (GPIOI2 ,0xfc0 ),INTC_VECT (GPIOI3 ,0xfe0 ), +INTC_VECT (FLCTL ,0xf00 ),INTC_VECT (FLCTL ,0xf20 ), +INTC_VECT (FLCTL ,0xf40 ),INTC_VECT (FLCTL ,0xf60 ), +INTC_VECT (GPIO ,0xf80 ),INTC_VECT (GPIO ,0xfa0 ), +INTC_VECT (GPIO ,0xfc0 ),INTC_VECT (GPIO ,0xfe0 ), };static struct intc_group groups[]__initdata = { -INTC_GROUP (RTC ,RTC_ATI ,RTC_PRI ,RTC_CUI ),INTC_GROUP (TMU012 ,TMU0 ,TMU1 ,TMU2 ,TMU2_TICPI ), -INTC_GROUP (DMAC0 ,DMAC0_DMINT0 ,DMAC0_DMINT1 ,DMAC0_DMINT2 , -DMAC0_DMINT3 ,DMAC0_DMINT4 ,DMAC0_DMINT5 ,DMAC0_DMAE ), -INTC_GROUP (SCIF0 ,SCIF0_ERI ,SCIF0_RXI ,SCIF0_BRI ,SCIF0_TXI ), -INTC_GROUP (DMAC1 ,DMAC1_DMINT6 ,DMAC1_DMINT7 ,DMAC1_DMINT8 , -DMAC1_DMINT9 ,DMAC1_DMINT10 ,DMAC1_DMINT11 ), -INTC_GROUP (PCIC5 ,PCIERR ,PCIPWD3 ,PCIPWD2 ,PCIPWD1 ,PCIPWD0 ), -INTC_GROUP (SCIF1 ,SCIF1_ERI ,SCIF1_RXI ,SCIF1_BRI ,SCIF1_TXI ), -INTC_GROUP (MMCIF ,MMCIF_FSTAT ,MMCIF_TRAN ,MMCIF_ERR ,MMCIF_FRDY ),INTC_GROUP (TMU345 ,TMU3 ,TMU4 ,TMU5 ), -INTC_GROUP (FLCTL ,FLCTL_FLSTE ,FLCTL_FLEND , -FLCTL_FLTRQ0 ,FLCTL_FLTRQ1 ), -INTC_GROUP (GPIO ,GPIOI0 ,GPIOI1 ,GPIOI2 ,GPIOI3 ), }; static struct intc_mask_reg mask_registers[] __initdata = {