sh4a: add L2 cache support
Quoted 28 lines · Kuninori Morimoto
Signed-off-by Kuninori Morimoto <[email protected]>--- arch/sh/include/cpu-sh4/cpu/cache.h | 5 +++++ arch/sh/kernel/cpu/init.c | 8 ++++++++ arch/sh/mm/Kconfig | 5 +++++ 3 files changed, 18 insertions(+), 0 deletions(-)arch/sh/include/cpu-sh4/cpu/cache.h +5
-0@@ -31,6 +31,11 @@#define CCR_CACHE_EMODE 0x80000000/* EMODE Enable */ #endif +#define RAMCR 0xFF000074 +#define RAMCR_CACHE_L2FC 0x0002 +#define RAMCR_CACHE_L2E 0x0001 +#define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC) +/* Default CCR setup: 8k+16k-byte cache,P1-wb,enable */ #define CCR_CACHE_ENABLE (CCR_CACHE_OCE|CCR_CACHE_ICE)#define CCR_CACHE_INVALIDATE (CCR_CACHE_OCI|CCR_CACHE_ICI)arch/sh/kernel/cpu/init.c +0
-0
arch/sh/kernel/cpu/init.c static void __uses_jump_to_uncached cache_init(void) · line 152
Quoted 7 lines
arch/sh/kernel/cpu/init.c +4
-0@@ -146,6 +146,14 @@ static void __uses_jump_to_uncached cache_init(void) flags &= ~CCR_CACHE_ENABLE ;#endif +#ifdef CONFIG_L2_CACHE_ENABLE +/* Enabel L2 cache */ +if (current_cpu_data.flags &CPU_HAS_L2_CACHE ) { +ctrl_outl (flags & ~CCR_CACHE_ENABLE ,CCR );
What is the purpose of this? This suggests that we don't have to care about things like the OCE and ICE bits if the L2 cache is enabled, but I don't see this mentioned anywhere in the specification.
arch/sh/kernel/cpu/init.c static void __uses_jump_to_uncached cache_init(void) · line 157
Quoted 5 lines
arch/sh/kernel/cpu/init.c +4
-0+ ctrl_outl(L2_CACHE_ENABLE, RAMCR); + } +#endif +ctrl_outl (flags,CCR );
And it will be clobbered here anyways, so I expect this part was at least not verified.
Quoted 7 lines
arch/sh/kernel/cpu/init.c +0
-0back_to_cached (); }arch/sh/mm/Kconfig +0
-0
arch/sh/mm/Kconfig config CACHE_OFF · line 298
Quoted 8 lines
arch/sh/mm/Kconfig +5
-0@@ -291,4 +291,9 @@ config CACHE_OFF endchoice +config L2_CACHE_ENABLE + bool "L2 Cache Enable" + depends on CACHE_WRITEBACK || CACHE_WRITETHROUGH + depends on CPU_SH4 +
There is no point in having this as a config option, we always want it enabled, and only want it disabled if we build an uncached kernel.
Unfortunately each CPU that implements the L2 seems to do so in totally different ways, so this is something that will have to be done by the CPU code. Shoving these bits in RAMCR seems pretty dubious to start with, and no other sane CPU (ie, SH7786) does this, although obviously in the case of SH7724 this is just reusing the low reserved RAMCR bits rather than adding a proper L2CR.
The behaviour also seems to differ. While SH7786 specifically has I/D-cache fetch bits for the L2, SH7724 seems to skip this and write in to the addres array directly. The ICE/OCE implications are less obvious in the case of SH7786, though.