Skip to contentSkip to conversation

intr-remap: generic support for remapping HPET MSIs

PATCH In review Suresh Siddha 3 participants 8 messages Aug 4, 2009 – Aug 27, 2009

Subsystems (5)
x86 ACPI PCI Hpet: x86 +1 more subsystems
lore
Share & tools
lore
author
#1 lore raw

PATCH 2/2 x86: arch specific support for remapping HPET MSIs

In reply to Suresh Siddha

x86 arch support for remapping HPET MSI's by associating the HPET timer block with the interrupt-remapping HW unit and setting up appropriate irq_chip

Signed-off-by Suresh Siddha <[email protected]>
Cc Venkatesh Pallipadi <[email protected]>
Cc David Woodhouse <[email protected]>
Cc Jesse Barnes <[email protected]>
Cc Jay Fenlason <[email protected]>

---

arch/x86/include/asm/hpet.h +3 -2
Index: tip/arch/x86/include/asm/hpet.h
===================================================================
@@ -65,6 +65,7 @@
 /* hpet memory map physical address */
 extern unsigned long hpet_address;
 extern unsigned long force_hpet_address;
+extern u8 hpet_blockid;
 extern int hpet_force_user;
 extern int is_hpet_enabled(void);
 extern int hpet_enable(void);

@@ -78,9 +79,9 @@ extern void hpet_msi_write(unsigned int 
 extern void hpet_msi_read(unsigned int irq, struct msi_msg *msg);
 
 #ifdef CONFIG_PCI_MSI
-extern int arch_setup_hpet_msi(unsigned int irq);
+extern int arch_setup_hpet_msi(unsigned int irq, unsigned int id);
 #else
-static inline int arch_setup_hpet_msi(unsigned int irq)
+static inline int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
 {
 	return -EINVAL;
 }
arch/x86/kernel/acpi/boot.c +1 -0
Index: tip/arch/x86/kernel/acpi/boot.c
===================================================================
@@ -624,6 +624,7 @@ static int __init acpi_parse_hpet(struct
 	}
 
 	hpet_address = hpet_tbl->address.address;
+	hpet_blockid = hpet_tbl->sequence;
 
 	/*
 	 * Some broken BIOSes advertise HPET at 0x0. We really do not
arch/x86/kernel/apic/io_apic.c +41 -8

95 lines not on this page · raw message

arch/x86/kernel/hpet.c +2 -1
Index: tip/arch/x86/kernel/hpet.c
===================================================================
@@ -33,6 +33,7 @@
  * HPET address is set in acpi/boot.c, when an ACPI entry exists
  */
 unsigned long				hpet_address;
+u8					hpet_blockid; /* OS timer block num */
 #ifdef CONFIG_PCI_MSI
 static unsigned long			hpet_num_timers;
 #endif

@@ -467,7 +468,7 @@ static int hpet_msi_next_event(unsigned 
 
 static int hpet_setup_msi_irq(unsigned int irq)
 {
-	if (arch_setup_hpet_msi(irq)) {
+	if (arch_setup_hpet_msi(irq, hpet_blockid)) {
 		destroy_irq(irq);
 		return -EINVAL;
 	}

Suresh Siddha

author
#0 lore raw

PATCH 1/2 intr-remap: generic support for remapping HPET MSIs

Generic support for remapping HPET MSI's by parsing the HPET timer block device scope in the ACPI DRHD tables. This is needed for platforms supporting interrupt-remapping and MSI capable HPET timer block.

Signed-off-by Suresh Siddha <[email protected]>
Cc David Woodhouse <[email protected]>
Cc Jesse Barnes <[email protected]>
Cc Venkatesh Pallipadi <[email protected]>
Cc Jay Fenlason <[email protected]>

---

drivers/pci/intr_remapping.c +85 -4
Index: tip/drivers/pci/intr_remapping.c
===================================================================
@@ -2,6 +2,7 @@
 #include <linux/dmar.h>
 #include <linux/spinlock.h>
 #include <linux/jiffies.h>
+#include <linux/hpet.h>
 #include <linux/pci.h>
 #include <linux/irq.h>
 #include <asm/io_apic.h>

@@ -14,7 +15,8 @@
 #include "pci.h"
 
 static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
-static int ir_ioapic_num;
+static struct hpet_scope ir_hpet[MAX_HPET_TBS];
+static int ir_ioapic_num, ir_hpet_num;
 int intr_remapping_enabled;
 
 static int disable_intremap;

@@ -351,6 +353,16 @@ int flush_irte(int irq)
 	return rc;
 }
 
+struct intel_iommu *map_hpet_to_ir(u8 hpet_id)
+{
+	int i;
+
+	for (i = 0; i < MAX_HPET_TBS; i++)
+		if (ir_hpet[i].id == hpet_id)
+			return ir_hpet[i].iommu;
+	return NULL;
+}
+
 struct intel_iommu *map_ioapic_to_ir(int apic)
 {
 	int i;

@@ -478,6 +490,36 @@ int set_ioapic_sid(struct irte *irte, in
 	return 0;
 }
 
+int set_hpet_sid(struct irte *irte, u8 id)
+{
+	int i;
+	u16 sid = 0;
+
+	if (!irte)
+		return -1;
+
+	for (i = 0; i < MAX_HPET_TBS; i++) {
+		if (ir_hpet[i].id == id) {
+			sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn;
+			break;
+		}
+	}
+
+	if (sid == 0) {
+		pr_warning("Failed to set source-id of HPET block (%d)\n", id);
+		return -1;
+	}
+
+	/*
+	 * Should really use SQ_ALL_16. Some platforms are broken.
+	 * While we figure out the right quirks for these broken platforms, use
+	 * SQ_13_IGNORE_3 for now.
+	 */
+	set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid);
+
+	return 0;
+}
+
 int set_msi_sid(struct irte *irte, struct pci_dev *dev)
 {
 	struct pci_dev *bridge;

@@ -711,6 +753,34 @@ error:
 	return -1;
 }
 
+static void ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope,
+				      struct intel_iommu *iommu)
+{
+	struct acpi_dmar_pci_path *path;
+	u8 bus;
+	int count;
+
+	bus = scope->bus;
+	path = (struct acpi_dmar_pci_path *)(scope + 1);
+	count = (scope->length - sizeof(struct acpi_dmar_device_scope))
+		/ sizeof(struct acpi_dmar_pci_path);
+
+	while (--count > 0) {
+		/*
+		 * Access PCI directly due to the PCI
+		 * subsystem isn't initialized yet.
+		 */
+		bus = read_pci_config_byte(bus, path->dev, path->fn,
+					   PCI_SECONDARY_BUS);
+		path++;
+	}
+	ir_hpet[ir_hpet_num].bus   = bus;
+	ir_hpet[ir_hpet_num].devfn = PCI_DEVFN(path->dev, path->fn);
+	ir_hpet[ir_hpet_num].iommu = iommu;
+	ir_hpet[ir_hpet_num].id    = scope->enumeration_id;
+	ir_hpet_num++;
+}
+
 static void ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope,
 				      struct intel_iommu *iommu)
 {

@@ -740,8 +810,8 @@ static void ir_parse_one_ioapic_scope(st
 	ir_ioapic_num++;
 }
 
-static int ir_parse_ioapic_scope(struct acpi_dmar_header *header,
-				 struct intel_iommu *iommu)
+static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header,
+				      struct intel_iommu *iommu)
 {
 	struct acpi_dmar_hardware_unit *drhd;
 	struct acpi_dmar_device_scope *scope;

@@ -765,6 +835,17 @@ static int ir_parse_ioapic_scope(struct 
 			       drhd->address);
 
 			ir_parse_one_ioapic_scope(scope, iommu);
+		} else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET) {
+			if (ir_hpet_num == MAX_HPET_TBS) {
+				printk(KERN_WARNING "Exceeded Max HPET blocks\n");
+				return -1;
+			}
+
+			printk(KERN_INFO "HPET id %d under DRHD base"
+			       " 0x%Lx\n", scope->enumeration_id,
+			       drhd->address);
+
+			ir_parse_one_hpet_scope(scope, iommu);
 		}
 		start += scope->length;
 	}

@@ -785,7 +866,7 @@ int __init parse_ioapics_under_ir(void)
 		struct intel_iommu *iommu = drhd->iommu;
 
 		if (ecap_ir_support(iommu->ecap)) {
-			if (ir_parse_ioapic_scope(drhd->hdr, iommu))
+			if (ir_parse_ioapic_hpet_scope(drhd->hdr, iommu))
 				return -1;
 
 			ir_supported = 1;
drivers/pci/intr_remapping.h +7 -0
Index: tip/drivers/pci/intr_remapping.h
===================================================================
@@ -7,4 +7,11 @@ struct ioapic_scope {
 	unsigned int devfn;	/* PCI devfn number */
 };
 
+struct hpet_scope {
+	struct intel_iommu *iommu;
+	u8 id;
+	unsigned int bus;
+	unsigned int devfn;
+};
+
 #define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0)
include/linux/dmar.h +10 -0
Index: tip/include/linux/dmar.h
===================================================================
@@ -126,7 +126,9 @@ extern int free_irte(int irq);
 extern int irq_remapped(int irq);
 extern struct intel_iommu *map_dev_to_ir(struct pci_dev *dev);
 extern struct intel_iommu *map_ioapic_to_ir(int apic);
+extern struct intel_iommu *map_hpet_to_ir(u8 id);
 extern int set_ioapic_sid(struct irte *irte, int apic);
+extern int set_hpet_sid(struct irte *irte, u8 id);
 extern int set_msi_sid(struct irte *irte, struct pci_dev *dev);
 #else
 static inline int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)

@@ -158,10 +160,18 @@ static inline struct intel_iommu *map_io
 {
 	return NULL;
 }
+static inline struct intel_iommu *map_hpet_to_ir(unsigned int hpet_id)
+{
+	return NULL;
+}
 static inline int set_ioapic_sid(struct irte *irte, int apic)
 {
 	return 0;
 }
+static inline int set_hpet_sid(struct irte *irte, u8 id)
+{
+	return -1;
+}
 static inline int set_msi_sid(struct irte *irte, struct pci_dev *dev)
 {
 	return 0;
include/linux/hpet.h +2 -0
Index: tip/include/linux/hpet.h
===================================================================
@@ -126,4 +126,6 @@ struct hpet_info {
 #define	HPET_DPI	_IO('h', 0x05)	/* disable periodic */
 #define	HPET_IRQFREQ	_IOW('h', 0x6, unsigned long)	/* IRQFREQ usec */
 
+#define MAX_HPET_TBS	8		/* maximum hpet timer blocks */
+
 #endif				/* !__HPET__ */
#2 lore raw

Re: [patch 2/2] x86: arch specific support for remapping HPET MSIs

In reply to Suresh Siddha
Quoted 3 lines · Suresh Siddha

x86 arch support for remapping HPET MSI's by associating the HPET timer block with the interrupt-remapping HW unit and setting up appropriate irq_chip

interesting. This means we'd materially utilize the irq-remapper not just on relatively obscure, virtualization related setups, but also in the native x86 bootup mode, on all (hpet+remap capable) Linux systems?

I like it - but i'll defer to Thomas to queue it up.

Ingo

#3 lore raw

Re: [patch 2/2] x86: arch specific support for remapping HPET MSIs

Quoted 7 lines · On Sat, 8 Aug 2009 17:12:54 +0200 Ingo Molnar <[email protected]> wrote:
Quoted 3 lines · Suresh Siddha

x86 arch support for remapping HPET MSI's by associating the HPET timer block with the interrupt-remapping HW unit and setting up appropriate irq_chip

Quoted 6 lines

interesting. This means we'd materially utilize the irq-remapper not just on relatively obscure, virtualization related setups, but also in the native x86 bootup mode, on all (hpet+remap capable) Linux systems?

I like it - but i'll defer to Thomas to queue it up.

I guess this set should go through either the iommu or -tip tree.

Signature · 1 line
Jesse Barnes, Intel Open Source Technology Center
author
#4 lore raw

Re: [patch 2/2] x86: arch specific support for remapping HPET MSIs

In reply to Ingo Molnar
Quoted 10 lines · Ingo Molnar
Quoted 3 lines · Suresh Siddha

x86 arch support for remapping HPET MSI's by associating the HPET timer block with the interrupt-remapping HW unit and setting up appropriate irq_chip

interesting. This means we'd materially utilize the irq-remapper not just on relatively obscure, virtualization related setups, but also in the native x86 bootup mode, on all (hpet+remap capable) Linux systems?

Ingo, For native linux kernel, interrupt-remapping allows simple and reliable irq migration from the process context (in addition to its need for supporting cpu's capable of x2apic). And as such solves the issues we had in the past with cpu hotplug and irq migration.

Quoted 1 line

I like it - but i'll defer to Thomas to queue it up.

thanks,
suresh

#5 lore raw

Re: [patch 2/2] x86: arch specific support for remapping HPET MSIs

Quoted 12 lines · Suresh Siddha
Quoted 10 lines · Ingo Molnar
Quoted 3 lines · Suresh Siddha

x86 arch support for remapping HPET MSI's by associating the HPET timer block with the interrupt-remapping HW unit and setting up appropriate irq_chip

interesting. This means we'd materially utilize the irq-remapper not just on relatively obscure, virtualization related setups, but also in the native x86 bootup mode, on all (hpet+remap capable) Linux systems?

Quoted 5 lines

Ingo, For native linux kernel, interrupt-remapping allows simple and reliable irq migration from the process context (in addition to its need for supporting cpu's capable of x2apic). And as such solves the issues we had in the past with cpu hotplug and irq migration.

It's something much more directly useful than a fix for race conditions, and it would be used in a broader range of hardware than x2apic. (Not to denounce its other uses - i was just upbeat about it getting even more mainstream use.)

Ingo

author
#7 lore raw
In reply to Suresh Siddha
Commit-ID:  20f3097bfe5fb5ced0b14f9ea2620c4039bf1dde
Gitweb:     http://git.kernel.org/tip/20f3097bfe5fb5ced0b14f9ea2620c4039bf1dde
Author:     Suresh Siddha <[email protected]>
AuthorDate: Tue, 4 Aug 2009 12:07:08 -0700
Committer:  Thomas Gleixner <[email protected]>
CommitDate: Thu, 27 Aug 2009 23:33:20 +0200

intr-remap: generic support for remapping HPET MSIs

Generic support for remapping HPET MSI's by parsing the HPET timer block device scope in the ACPI DRHD tables. This is needed for platforms supporting interrupt-remapping and MSI capable HPET timer block.

Signed-off-by Suresh Siddha <[email protected]>
Cc David Woodhouse <[email protected]>
Cc Jesse Barnes <[email protected]>
Cc Venkatesh Pallipadi <[email protected]>
Cc Jay Fenlason <[email protected]>

LKML-Reference: <[email protected]>

Signed-off-by Thomas Gleixner <[email protected]>
---
 drivers/pci/intr_remapping.c |   89 ++++++++++++++++++++++++++++++++++++++++--
 drivers/pci/intr_remapping.h |    7 +++
 include/linux/dmar.h         |   10 +++++
 include/linux/hpet.h         |    2 +
 4 files changed, 104 insertions(+), 4 deletions(-)
drivers/pci/intr_remapping.c +85 -4
index 4f5b871..2cc3f70 100644
@@ -2,6 +2,7 @@
 #include <linux/dmar.h>
 #include <linux/spinlock.h>
 #include <linux/jiffies.h>
+#include <linux/hpet.h>
 #include <linux/pci.h>
 #include <linux/irq.h>
 #include <asm/io_apic.h>

@@ -14,7 +15,8 @@
 #include "pci.h"
 
 static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
-static int ir_ioapic_num;
+static struct hpet_scope ir_hpet[MAX_HPET_TBS];
+static int ir_ioapic_num, ir_hpet_num;
 int intr_remapping_enabled;
 
 static int disable_intremap;

@@ -351,6 +353,16 @@ int flush_irte(int irq)
 	return rc;
 }
 
+struct intel_iommu *map_hpet_to_ir(u8 hpet_id)
+{
+	int i;
+
+	for (i = 0; i < MAX_HPET_TBS; i++)
+		if (ir_hpet[i].id == hpet_id)
+			return ir_hpet[i].iommu;
+	return NULL;
+}
+
 struct intel_iommu *map_ioapic_to_ir(int apic)
 {
 	int i;

@@ -478,6 +490,36 @@ int set_ioapic_sid(struct irte *irte, int apic)
 	return 0;
 }
 
+int set_hpet_sid(struct irte *irte, u8 id)
+{
+	int i;
+	u16 sid = 0;
+
+	if (!irte)
+		return -1;
+
+	for (i = 0; i < MAX_HPET_TBS; i++) {
+		if (ir_hpet[i].id == id) {
+			sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn;
+			break;
+		}
+	}
+
+	if (sid == 0) {
+		pr_warning("Failed to set source-id of HPET block (%d)\n", id);
+		return -1;
+	}
+
+	/*
+	 * Should really use SQ_ALL_16. Some platforms are broken.
+	 * While we figure out the right quirks for these broken platforms, use
+	 * SQ_13_IGNORE_3 for now.
+	 */
+	set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid);
+
+	return 0;
+}
+
 int set_msi_sid(struct irte *irte, struct pci_dev *dev)
 {
 	struct pci_dev *bridge;

@@ -711,6 +753,34 @@ error:
 	return -1;
 }
 
+static void ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope,
+				      struct intel_iommu *iommu)
+{
+	struct acpi_dmar_pci_path *path;
+	u8 bus;
+	int count;
+
+	bus = scope->bus;
+	path = (struct acpi_dmar_pci_path *)(scope + 1);
+	count = (scope->length - sizeof(struct acpi_dmar_device_scope))
+		/ sizeof(struct acpi_dmar_pci_path);
+
+	while (--count > 0) {
+		/*
+		 * Access PCI directly due to the PCI
+		 * subsystem isn't initialized yet.
+		 */
+		bus = read_pci_config_byte(bus, path->dev, path->fn,
+					   PCI_SECONDARY_BUS);
+		path++;
+	}
+	ir_hpet[ir_hpet_num].bus   = bus;
+	ir_hpet[ir_hpet_num].devfn = PCI_DEVFN(path->dev, path->fn);
+	ir_hpet[ir_hpet_num].iommu = iommu;
+	ir_hpet[ir_hpet_num].id    = scope->enumeration_id;
+	ir_hpet_num++;
+}
+
 static void ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope,
 				      struct intel_iommu *iommu)
 {

@@ -740,8 +810,8 @@ static void ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope,
 	ir_ioapic_num++;
 }
 
-static int ir_parse_ioapic_scope(struct acpi_dmar_header *header,
-				 struct intel_iommu *iommu)
+static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header,
+				      struct intel_iommu *iommu)
 {
 	struct acpi_dmar_hardware_unit *drhd;
 	struct acpi_dmar_device_scope *scope;

@@ -765,6 +835,17 @@ static int ir_parse_ioapic_scope(struct acpi_dmar_header *header,
 			       drhd->address);
 
 			ir_parse_one_ioapic_scope(scope, iommu);
+		} else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET) {
+			if (ir_hpet_num == MAX_HPET_TBS) {
+				printk(KERN_WARNING "Exceeded Max HPET blocks\n");
+				return -1;
+			}
+
+			printk(KERN_INFO "HPET id %d under DRHD base"
+			       " 0x%Lx\n", scope->enumeration_id,
+			       drhd->address);
+
+			ir_parse_one_hpet_scope(scope, iommu);
 		}
 		start += scope->length;
 	}

@@ -785,7 +866,7 @@ int __init parse_ioapics_under_ir(void)
 		struct intel_iommu *iommu = drhd->iommu;
 
 		if (ecap_ir_support(iommu->ecap)) {
-			if (ir_parse_ioapic_scope(drhd->hdr, iommu))
+			if (ir_parse_ioapic_hpet_scope(drhd->hdr, iommu))
 				return -1;
 
 			ir_supported = 1;
drivers/pci/intr_remapping.h +7 -0
index 63a263c..5662fec 100644
@@ -7,4 +7,11 @@ struct ioapic_scope {
 	unsigned int devfn;	/* PCI devfn number */
 };
 
+struct hpet_scope {
+	struct intel_iommu *iommu;
+	u8 id;
+	unsigned int bus;
+	unsigned int devfn;
+};
+
 #define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0)
include/linux/dmar.h +10 -0
index 4a2b162..69a6fba 100644
@@ -126,7 +126,9 @@ extern int free_irte(int irq);
 extern int irq_remapped(int irq);
 extern struct intel_iommu *map_dev_to_ir(struct pci_dev *dev);
 extern struct intel_iommu *map_ioapic_to_ir(int apic);
+extern struct intel_iommu *map_hpet_to_ir(u8 id);
 extern int set_ioapic_sid(struct irte *irte, int apic);
+extern int set_hpet_sid(struct irte *irte, u8 id);
 extern int set_msi_sid(struct irte *irte, struct pci_dev *dev);
 #else
 static inline int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)

@@ -158,10 +160,18 @@ static inline struct intel_iommu *map_ioapic_to_ir(int apic)
 {
 	return NULL;
 }
+static inline struct intel_iommu *map_hpet_to_ir(unsigned int hpet_id)
+{
+	return NULL;
+}
 static inline int set_ioapic_sid(struct irte *irte, int apic)
 {
 	return 0;
 }
+static inline int set_hpet_sid(struct irte *irte, u8 id)
+{
+	return -1;
+}
 static inline int set_msi_sid(struct irte *irte, struct pci_dev *dev)
 {
 	return 0;
include/linux/hpet.h +2 -0
index 79f63a2..219ca4f 100644
@@ -126,4 +126,6 @@ struct hpet_info {
 #define	HPET_DPI	_IO('h', 0x05)	/* disable periodic */
 #define	HPET_IRQFREQ	_IOW('h', 0x6, unsigned long)	/* IRQFREQ usec */
 
+#define MAX_HPET_TBS	8		/* maximum hpet timer blocks */
+
 #endif				/* !__HPET__ */
author
#6 lore raw

[tip:timers/hpet] x86: arch specific support for remapping HPET MSIs

In reply to Suresh Siddha
Commit-ID:  c8bc6f3c806f1fcbfdbf0b1ff6c52dba59192d3b
Gitweb:     http://git.kernel.org/tip/c8bc6f3c806f1fcbfdbf0b1ff6c52dba59192d3b
Author:     Suresh Siddha <[email protected]>
AuthorDate: Tue, 4 Aug 2009 12:07:09 -0700
Committer:  Thomas Gleixner <[email protected]>
CommitDate: Thu, 27 Aug 2009 23:33:20 +0200

x86: arch specific support for remapping HPET MSIs

x86 arch support for remapping HPET MSI's by associating the HPET timer block with the interrupt-remapping HW unit and setting up appropriate irq_chip

Signed-off-by Suresh Siddha <[email protected]>
Cc Venkatesh Pallipadi <[email protected]>
Cc David Woodhouse <[email protected]>
Cc Jesse Barnes <[email protected]>
Cc Jay Fenlason <[email protected]>

LKML-Reference: <[email protected]>

Signed-off-by Thomas Gleixner <[email protected]>
---
 arch/x86/include/asm/hpet.h    |    5 ++-
 arch/x86/kernel/acpi/boot.c    |    1 +
 arch/x86/kernel/apic/io_apic.c |   49 +++++++++++++++++++++++++++++++++------
 arch/x86/kernel/hpet.c         |    3 +-
 4 files changed, 47 insertions(+), 11 deletions(-)
arch/x86/include/asm/hpet.h +3 -2
index 65847c5..5d89fd2 100644
@@ -65,6 +65,7 @@
 /* hpet memory map physical address */
 extern unsigned long hpet_address;
 extern unsigned long force_hpet_address;
+extern u8 hpet_blockid;
 extern int hpet_force_user;
 extern int is_hpet_enabled(void);
 extern int hpet_enable(void);

@@ -78,9 +79,9 @@ extern void hpet_msi_write(unsigned int irq, struct msi_msg *msg);
 extern void hpet_msi_read(unsigned int irq, struct msi_msg *msg);
 
 #ifdef CONFIG_PCI_MSI
-extern int arch_setup_hpet_msi(unsigned int irq);
+extern int arch_setup_hpet_msi(unsigned int irq, unsigned int id);
 #else
-static inline int arch_setup_hpet_msi(unsigned int irq)
+static inline int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
 {
 	return -EINVAL;
 }
arch/x86/kernel/acpi/boot.c +1 -0
index 6b8ca3a..eae642b 100644
@@ -624,6 +624,7 @@ static int __init acpi_parse_hpet(struct acpi_table_header *table)
 	}
 
 	hpet_address = hpet_tbl->address.address;
+	hpet_blockid = hpet_tbl->sequence;
 
 	/*
 	 * Some broken BIOSes advertise HPET at 0x0. We really do not
arch/x86/kernel/apic/io_apic.c +41 -8

95 lines not on this page · raw message

arch/x86/kernel/hpet.c +2 -1
index ba575f0..7f024ff 100644
@@ -33,6 +33,7 @@
  * HPET address is set in acpi/boot.c, when an ACPI entry exists
  */
 unsigned long				hpet_address;
+u8					hpet_blockid; /* OS timer block num */
 #ifdef CONFIG_PCI_MSI
 static unsigned long			hpet_num_timers;
 #endif

@@ -467,7 +468,7 @@ static int hpet_msi_next_event(unsigned long delta,
 
 static int hpet_setup_msi_irq(unsigned int irq)
 {
-	if (arch_setup_hpet_msi(irq)) {
+	if (arch_setup_hpet_msi(irq, hpet_blockid)) {
 		destroy_irq(irq);
 		return -EINVAL;
 	}