MIPS: deal with larger physical offset
PATCH 3/4 MIPS: deal with larger physical offset
AR7 has a larger physical offset than other MIPS based systems and therefore needs to setup handlers differently. This version uses uasm instead of the hand crafted assembly previously sent. This modification is also required for running the kernel in mapped address space.
---
arch/mips/kernel/traps.c +14 -3
@@ -51,6 +51,8 @@#include <asm/stacktrace.h> #include <asm/irq.h> +#include "../mm/uasm.h" +extern void check_wait (void ); extern asmlinkage void r4k_wait(void); extern asmlinkage void rollback_handle_int(void);
@@ -1283,9 +1285,18 @@ void *set_except_vector(int n, void *addr) exception_handlers[n] = handler;if (n ==0 && cpu_has_divec) { - *(u32 *)(ebase +0x200 ) =0x08000000 | - (0x03ffffff & (handler >>2 )); -local_flush_icache_range (ebase +0x200 , ebase +0x204 ); +unsigned long jump_mask = ~((1 <<28 ) -1 ); +u32 *buf = (u32 *)(ebase +0x200 ); +unsigned int k0 =26 ; +if ((handler & jump_mask) == ((ebase +0x200 ) & jump_mask)) { +uasm_i_j (&buf, handler & jump_mask); +uasm_i_nop (&buf); + }else { +UASM_i_LA (&buf, k0, handler); +uasm_i_jr (&buf, k0); +uasm_i_nop (&buf); + } +local_flush_icache_range (ebase +0x200 , (unsigned long )buf); }return (void *)old_handler; }
Quoted 15 lines · Florian Fainelli
AR7 has a larger physical offset than other MIPS based systems and therefore needs to setup handlers differently. This version uses uasm instead of the hand crafted assembly previously sent. This modification is also required for running the kernel in mapped address space.
Signed-off-by David Daney <[email protected]>Signed-off-by Eugene Konev <[email protected]>Signed-off-by Florian Fainelli <[email protected]>---
arch/mips/kernel/traps.c +0
-0
arch/mips/kernel/traps.c line 55
Quoted 5 lines
arch/mips/kernel/traps.c +2
-0@@ -51,6 +51,8 @@#include <asm/stacktrace.h> #include <asm/irq.h> +#include "../mm/uasm.h" +
The first time this came up, it was suggested that uasm.h move to asm/uasm.h so that we don't have this ugliness. I think it is still a good idea.
Quoted 12 lines
arch/mips/kernel/traps.c +2
-3extern void check_wait (void ); extern asmlinkage void r4k_wait(void); extern asmlinkage void rollback_handle_int(void);@@ -1283,9 +1285,18 @@ void *set_except_vector(int n, void *addr) exception_handlers[n] = handler;if (n ==0 && cpu_has_divec) { - *(u32 *)(ebase +0x200 ) =0x08000000 | - (0x03ffffff & (handler >>2 )); -local_flush_icache_range (ebase +0x200 , ebase +0x204 ); +unsigned long jump_mask = ~((1 <<28 ) -1 ); +u32 *buf = (u32 *)(ebase +0x200 );
arch/mips/kernel/traps.c void *set_except_vector(int n, void *addr) · line 1299
Quoted 10 lines
arch/mips/kernel/traps.c +10
-0+unsigned int k0 =26 ; +if ((handler & jump_mask) == ((ebase +0x200 ) & jump_mask)) { +uasm_i_j (&buf, handler & jump_mask); +uasm_i_nop (&buf); + }else { +UASM_i_LA (&buf, k0, handler); +uasm_i_jr (&buf, k0); +uasm_i_nop (&buf); + } +local_flush_icache_range (ebase +0x200 , (unsigned long )buf);
I would expect that this causes section mismatch build warnings.
You may have to make this function __init or __cpu_init (and change trap_init() to __cpu_init too).
You should also fix the comment, as after the patch it is no longer accurate.
Quoted 5 lines
arch/mips/kernel/traps.c +0
-0}return (void *)old_handler; }