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Support for IA32_ENERGY_PERF_BIAS MSR

PATCH In review [email protected] 4 participants 16 messages Mar 3, 2010 – Mar 6, 2010

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Documentation x86 ACPI
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#1 lore raw

PATCH 1/2 x86: Look for IA32_ENERGY_PERF_BIAS support

In reply to [email protected]

There is a new hardware feature, which lets system software to set Energy Performance Preference. This is a opaque knob in the form of IA32_ENERGY_PERF_BIAS MSR, which has a 4 bit Energy Performance Preference Hint. When supported, hardware can use this hint to resolve energy-performance tradeoffs. The support for this feature is indicated by CPUID.06H.ECX.bit3. Refer to Intel Architectures Software Developer's Manual for more info.

This patch, looks up for the support of this feature. It shows up as "epb" in /proc/cpuinfo flags, when supported.

Signed-off-by Venkatesh Pallipadi <[email protected]>
---
 arch/x86/include/asm/cpufeature.h          |    1 +
 arch/x86/include/asm/msr-index.h           |    2 ++
 arch/x86/kernel/cpu/addon_cpuid_features.c |    1 +
 3 files changed, 4 insertions(+), 0 deletions(-)
arch/x86/include/asm/cpufeature.h +1 -0
index 0cd82d0..0e1d52c 100644
@@ -161,6 +161,7 @@
  */
 #define X86_FEATURE_IDA		(7*32+ 0) /* Intel Dynamic Acceleration */
 #define X86_FEATURE_ARAT	(7*32+ 1) /* Always Running APIC Timer */
+#define X86_FEATURE_EPB		(7*32+ 2) /* IA32_ENERGY_PERF_BIAS support */
 
 /* Virtualization flags: Linux defined */
 #define X86_FEATURE_TPR_SHADOW  (8*32+ 0) /* Intel TPR Shadow */
arch/x86/include/asm/msr-index.h +2 -0
index 1cd58cd..feeb918 100644
@@ -230,6 +230,8 @@
 
 #define MSR_IA32_MISC_ENABLE		0x000001a0
 
+#define MSR_IA32_ENERGY_PERF_BIAS	0x000001b0
+
 /* MISC_ENABLE bits: architectural */
 #define MSR_IA32_MISC_ENABLE_FAST_STRING	(1ULL << 0)
 #define MSR_IA32_MISC_ENABLE_TCC		(1ULL << 1)
arch/x86/kernel/cpu/addon_cpuid_features.c +1 -0
index 97ad79c..3bc5eda 100644
@@ -32,6 +32,7 @@ void __cpuinit init_scattered_cpuid_features(struct cpuinfo_x86 *c)
 	static const struct cpuid_bit __cpuinitconst cpuid_bits[] = {
 		{ X86_FEATURE_IDA, CR_EAX, 1, 0x00000006 },
 		{ X86_FEATURE_ARAT, CR_EAX, 2, 0x00000006 },
+		{ X86_FEATURE_EPB, CR_ECX, 3, 0x00000006 },
 		{ X86_FEATURE_NPT,   CR_EDX, 0, 0x8000000a },
 		{ X86_FEATURE_LBRV,  CR_EDX, 1, 0x8000000a },
 		{ X86_FEATURE_SVML,  CR_EDX, 2, 0x8000000a },
Signature · 3 lines
1.6.0.6

--

[email protected]

author
#0 lore raw

cover Support for IA32_ENERGY_PERF_BIAS MSR

There is a new hardware feature, which lets system software to set Energy Performance Preference. This is a opaque knob in the form of IA32_ENERGY_PERF_BIAS MSR, which has a 4 bit Energy Performance Preference Hint.

The support for this feature is indicated by CPUID.06H.ECX.bit3. Refer to Intel Architectures Software Developer's Manual for more info.

Signed-off-by Venkatesh Pallipadi <[email protected]>
author
#2 lore raw

PATCH 2/2 x86: Manage ENERGY_PERF_BIAS based on cpufreq governor

Manage IA32_ENERGY_PERF_BIAS setting.

By default, this driver sets IA32_ENERGY_PERF_BIAS as follows 0 when cpufreq performance governor is being used 15 when cpufreq powersave governor is being used
7 otherwise

There is an option to disable setting IA32_ENERGY_PERF_BIAS using epb=disable boot option.
There is an option to manual override IA32_ENERGY_PERF_BIAS using epb=<0..15> where user set energy_perf_bias value will be set, irrespective of cpufreq governor.

Signed-off-by Venkatesh Pallipadi <[email protected]>
---
 Documentation/kernel-parameters.txt            |    4 +
 arch/x86/kernel/cpu/cpufreq/Kconfig            |    6 +
 arch/x86/kernel/cpu/cpufreq/Makefile           |    1 +
 arch/x86/kernel/cpu/cpufreq/energy_perf_bias.c |  186 ++++++++++++++++++++++++
 4 files changed, 197 insertions(+), 0 deletions(-)
 create mode 100644 arch/x86/kernel/cpu/cpufreq/energy_perf_bias.c
Documentation/kernel-parameters.txt +4 -0
index 8c666d8..4945add 100644
@@ -749,6 +749,10 @@ and is between 256 and 4096 characters. It is defined in the file
 			Default value is 0.
 			Value can be changed at runtime via /selinux/enforce.
 
+	epb		[X86] Control IA32_ENERGY_PERF_BIAS setting
+			"disable" - Kernel will not modify this MSR
+			<0..15> - Kernel will set this MSR to i/p static value
+
 	ether=		[HW,NET] Ethernet cards parameters
 			This option is obsoleted by the "netdev=" option, which
 			has equivalent usage. See its documentation for details.
arch/x86/kernel/cpu/cpufreq/Kconfig +6 -0
index f138c6c..1addc05 100644
@@ -26,6 +26,12 @@ config X86_ACPI_CPUFREQ
 
 	  If in doubt, say N.
 
+config X86_ENERGY_PERF_BIAS
+	def_bool y
+	depends on X86_ACPI_CPUFREQ
+	help
+	  Support for x86 Intel ENERGY_PERF_BIAS MSR
+
 config ELAN_CPUFREQ
 	tristate "AMD Elan SC400 and SC410"
 	select CPU_FREQ_TABLE
arch/x86/kernel/cpu/cpufreq/Makefile +1 -0
index 509296d..5290428 100644
@@ -18,3 +18,4 @@ obj-$(CONFIG_X86_SPEEDSTEP_SMI)		+= speedstep-smi.o
 obj-$(CONFIG_X86_SPEEDSTEP_CENTRINO)	+= speedstep-centrino.o
 obj-$(CONFIG_X86_P4_CLOCKMOD)		+= p4-clockmod.o
 obj-$(CONFIG_X86_CPUFREQ_NFORCE2)	+= cpufreq-nforce2.o
+obj-$(CONFIG_X86_ENERGY_PERF_BIAS)	+= energy_perf_bias.o
arch/x86/kernel/cpu/cpufreq/energy_perf_bias.c new file +186 -0

186 lines not on this page · raw message

Signature · 3 lines
1.6.0.6

--
#3 lore raw

Re: [patch 2/2] x86: Manage ENERGY_PERF_BIAS based on cpufreq governor

On 03/02/10 16:06, [email protected] wrote:

{bah, more difficult to review an attachment, so no leading '>'}

Documentation/kernel-parameters.txt +4 -0
index 8c666d8..4945add 100644
@@ -749,6 +749,10 @@ and is between 256 and 4096 characters. It is defined in the file
 			Default value is 0.
 			Value can be changed at runtime via /selinux/enforce.
 
+	epb		[X86] Control IA32_ENERGY_PERF_BIAS setting
+			"disable" - Kernel will not modify this MSR
+			<0..15> - Kernel will set this MSR to i/p static value
+

Should be more like:

epb= [X86] Control IA32_ENERGY_PERF_BIAS setting
Format: { disable | <0...15> }
"disable" - Kernel will not modify this MSR <0..15> - Kernel will set this MSR to i/p static value

But what is "i/p"? Use whatever word it should be, please. What do the values mean?
And what does IA32 have to do with this? does it not apply to x86_64?

thanks,

Signature · 1 line
~Randy
author
#4 lore raw

Re: [patch 2/2] x86: Manage ENERGY_PERF_BIAS based on cpufreq governor

In reply to Randy Dunlap
Quoted 3 lines · Randy Dunlap

On 03/02/10 16:06, [email protected] wrote:

{bah, more difficult to review an attachment, so no leading '>'}

Sorry. Not sure why/how you are seeing attachment issue. I used quilt mail to send this out (I have used this method earlier as well) and I do see patches inline .

Quoted 17 lines
Documentation/kernel-parameters.txt +4 -0
index 8c666d8..4945add 100644
@@ -749,6 +749,10 @@ and is between 256 and 4096 characters. It is defined in the file
 			Default value is 0.
 			Value can be changed at runtime via /selinux/enforce.
 
+	epb		[X86] Control IA32_ENERGY_PERF_BIAS setting
+			"disable" - Kernel will not modify this MSR
+			<0..15> - Kernel will set this MSR to i/p static value
+

Should be more like:

Quoted 2 lines
	epb=		[X86] Control IA32_ENERGY_PERF_BIAS setting
			Format: { disable | <0...15> }

OK. Will change.

Quoted 5 lines

"disable" - Kernel will not modify this MSR <0..15> - Kernel will set this MSR to i/p static value

But what is "i/p"? Use whatever word it should be, please.

I meant input. will change to something like "specified value"

Quoted 1 line

What do the values mean?

The way MSR is defined, the value is opaque. It can be used for different optimizations in different CPUs.

Quoted 1 line

And what does IA32 have to do with this? does it not apply to x86_64?

IA32_ in any MSR name is the convention that is generally followed for all MSRs in Intel SDM. It means that the MSR is architectural (can be detected with CPUID or some other standard way and not CPU Model specific.

Thanks,
Venki

author
#15 lore raw

Re: [patch 2/2] x86: Manage ENERGY_PERF_BIAS based on cpufreq governor

In reply to Matthew Garrett
Quoted 3 lines · Matthew Garrett

Have you done any measurements with this bit being set dynamically by ondemand depending on the target frequency?

The not so good part about this feature is that its setting is opaque. Different CPUs can use this value for different optimizations. So, in future we may have to change the value of this MSR based on frequency or other metrics. But, for CPUs which support this MSR today, changing the value with frequency do not make any difference.

Thanks,
Venki

#5 lore raw

Re: [patch 2/2] x86: Manage ENERGY_PERF_BIAS based on cpufreq governor

In reply to Randy Dunlap

Hi!

Quoted 21 lines

index 8c666d8..4945add 100644

Documentation/kernel-parameters.txt +4 -0
@@ -749,6 +749,10 @@ and is between 256 and 4096 characters. It is defined in the file
 			Default value is 0.
 			Value can be changed at runtime via /selinux/enforce.
 
+	epb		[X86] Control IA32_ENERGY_PERF_BIAS setting
+			"disable" - Kernel will not modify this MSR
+			<0..15> - Kernel will set this MSR to i/p static value
+

Should be more like:

epb= [X86] Control IA32_ENERGY_PERF_BIAS setting
Format: { disable | <0...15> }
"disable" - Kernel will not modify this MSR <0..15> - Kernel will set this MSR to i/p static value

Quoted 3 lines

But what is "i/p"? Use whatever word it should be, please. What do the values mean?
And what does IA32 have to do with this? does it not apply to x86_64?

Exactly. This is end user documentation, it should not even talk about MSRs. Tell us what the setting does...

Also... does it make change to tweak the setting during runtime? Maybe different settings for AC and battery power?

Pavel

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author
#6 lore raw

Re: [patch 2/2] x86: Manage ENERGY_PERF_BIAS based on cpufreq governor

Quoted 23 lines · Pavel Machek

Hi!

Quoted 21 lines

index 8c666d8..4945add 100644

Documentation/kernel-parameters.txt +4 -0
@@ -749,6 +749,10 @@ and is between 256 and 4096 characters. It is defined in the file
 			Default value is 0.
 			Value can be changed at runtime via /selinux/enforce.
 
+	epb		[X86] Control IA32_ENERGY_PERF_BIAS setting
+			"disable" - Kernel will not modify this MSR
+			<0..15> - Kernel will set this MSR to i/p static value
+

Should be more like:

epb= [X86] Control IA32_ENERGY_PERF_BIAS setting
Format: { disable | <0...15> }
"disable" - Kernel will not modify this MSR <0..15> - Kernel will set this MSR to i/p static value

Quoted 6 lines
Quoted 3 lines

But what is "i/p"? Use whatever word it should be, please. What do the values mean?
And what does IA32 have to do with this? does it not apply to x86_64?

Exactly. This is end user documentation, it should not even talk about MSRs. Tell us what the setting does...

The not so good part of this feature is that the setting here is opaque. Software can set this based on its preference, for example 0 for performance 15 for power and 7 for balanced. Different CPUs can use this information to do different optimizations or power-performance tradeoffs in the hardware. The only thing that user knows here is that there is this dial with 16 possible values. I can remove the MSR name here. But, I think that will end up confusing the end user on what this thing is and how it is related to all the other tunables we have in the kernel. Having the MSR name gives a hint.

Also, the expectation here is that kernel will do the right thing by default. The option here is to the user who_knows_what_he_is_doing to override the kernel default.

Quoted 3 lines

Also... does it make change to tweak the setting during runtime? Maybe different settings for AC and battery power?

Yes. Matthew mentioned in other response aboue setting this based on freq. For the CPUs that support this feature currently, we don't see advantage in setting this feature at run time.

Thanks,
Venki

#7 lore raw

Re: [patch 2/2] x86: Manage ENERGY_PERF_BIAS based on cpufreq governor

Quoted 31 lines · Pavel Machek
Quoted 23 lines

Hi!

Quoted 21 lines

index 8c666d8..4945add 100644

Documentation/kernel-parameters.txt +4 -0
@@ -749,6 +749,10 @@ and is between 256 and 4096 characters. It is defined in the file
 			Default value is 0.
 			Value can be changed at runtime via /selinux/enforce.
 
+	epb		[X86] Control IA32_ENERGY_PERF_BIAS setting
+			"disable" - Kernel will not modify this MSR
+			<0..15> - Kernel will set this MSR to i/p static value
+

Should be more like:

epb= [X86] Control IA32_ENERGY_PERF_BIAS setting
Format: { disable | <0...15> }
"disable" - Kernel will not modify this MSR <0..15> - Kernel will set this MSR to i/p static value

Quoted 6 lines
Quoted 3 lines

But what is "i/p"? Use whatever word it should be, please. What do the values mean?
And what does IA32 have to do with this? does it not apply to x86_64?

Exactly. This is end user documentation, it should not even talk about MSRs. Tell us what the setting does...

Quoted 9 lines

The not so good part of this feature is that the setting here is opaque. Software can set this based on its preference, for example 0 for performance 15 for power and 7 for balanced. Different CPUs can use this information to do different optimizations or power-performance tradeoffs in the hardware. The only thing that user knows here is that there is this dial with 16 possible values. I can remove the MSR name here. But, I think that will end up confusing the end user on what this thing is and how it is related to all the other tunables we have in the kernel. Having the MSR name gives a hint.

You should say what the setting does; you can mention below what MSR it corresponds to, but "Control IA32_ENERGY_PERF_BIAS setting" is not suitable user documentation.

Quoted 3 lines

Also, the expectation here is that kernel will do the right thing by default. The option here is to the user who_knows_what_he_is_doing to override the kernel default.

You did not give user enough information to do anything intelligent...

Quoted 6 lines
Quoted 2 lines

Also... does it make change to tweak the setting during runtime? Maybe different settings for AC and battery power?

Yes. Matthew mentioned in other response aboue setting this based on freq. For the CPUs that support this feature currently, we don't see advantage in setting this feature at run time.

If the feature is useless, then why set it at all?
Pavel

Signature · 2 lines
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(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
author
#8 lore raw

RE: [patch 2/2] x86: Manage ENERGY_PERF_BIAS based on cpufreq governor

Quoted 70 lines

-----Original Message-----
From: Pavel Machek [mailto:[email protected]]
Sent: Friday, March 05, 2010 1:20 AM
To: Pallipadi, Venkatesh
Cc: Randy Dunlap; Ingo Molnar; H Peter Anvin; Thomas Gleixner; Len Brown; Dave Jones; [email protected]; [email protected]
Subject: Re: [patch 2/2] x86: Manage ENERGY_PERF_BIAS based on cpufreq governor

Quoted 7 lines · Pavel Machek
Quoted 6 lines

Hi!

Documentation/kernel-parameters.txt and is between 256 and 4096

Quoted 4 lines

index 8c666d8..4945add 100644

Documentation/kernel-parameters.txt +0 -0
@@ -749,6 +749,10 @@ and is between 256 and 4096

characters. It is defined in the file

Quoted 2 lines
Quoted 2 lines

Documentation/kernel-parameters.txt and is between 256 and 4096 · line 750

Quoted 2 lines
Documentation/kernel-parameters.txt +0 -0
 			Default value is 0.
 			Value can be changed at runtime

via /selinux/enforce.

Quoted 2 lines
Quoted 2 lines

Documentation/kernel-parameters.txt and is between 256 and 4096 · line 751

Quoted 2 lines
Documentation/kernel-parameters.txt +1 -0
+	epb		[X86] Control

IA32_ENERGY_PERF_BIAS setting

Quoted 1 line
Quoted 1 line

Documentation/kernel-parameters.txt and is between 256 and 4096 · line 752

Quoted 1 line
Documentation/kernel-parameters.txt +1 -0
+			"disable" - Kernel will not

modify this MSR

Quoted 1 line
Quoted 1 line

Documentation/kernel-parameters.txt and is between 256 and 4096 · line 753

Quoted 1 line
Documentation/kernel-parameters.txt +1 -0
+			<0..15> - Kernel will set this

MSR to i/p static value

Quoted 9 lines
Quoted 9 lines
Quoted 9 lines
Documentation/kernel-parameters.txt +1 -0
+

Should be more like:

epb= [X86] Control IA32_ENERGY_PERF_BIAS setting
Format: { disable | <0...15> } "disable" - Kernel will not modify this MSR <0..15> - Kernel will set this MSR to

i/p static value

Quoted 5 lines
Quoted 5 lines
Quoted 5 lines

But what is "i/p"? Use whatever word it should be, please. What do the values mean?
And what does IA32 have to do with this? does it not

apply to x86_64?

Quoted 2 lines
Quoted 2 lines

Exactly. This is end user documentation, it should not

even talk about

Quoted 3 lines
Quoted 1 line

MSRs. Tell us what the setting does...

The not so good part of this feature is that the setting

here is opaque.

Quoted 2 lines

Software can set this based on its preference, for example 0 for performance 15 for power and 7 for balanced. Different CPUs

can use this

Quoted 1 line

information to do different optimizations or

power-performance tradeoffs

Quoted 2 lines

in the hardware. The only thing that user knows here is that there is this dial with 16 possible values. I can remove the MSR name

here. But,

Quoted 2 lines

I think that will end up confusing the end user on what this thing is and how it is related to all the other tunables we have in

the kernel.

Quoted 1 line

Having the MSR name gives a hint.

You should say what the setting does; you can mention below what MSR it corresponds to, but "Control IA32_ENERGY_PERF_BIAS setting" is not suitable user documentation.

Quoted 5 lines
Quoted 3 lines

Also, the expectation here is that kernel will do the right thing by default. The option here is to the user who_knows_what_he_is_doing to override the kernel default.

You did not give user enough information to do anything intelligent...

I have rephrased it in the newer version sent yday with more info.

Quoted 9 lines
Quoted 1 line
Quoted 1 line

Also... does it make change to tweak the setting during

runtime? Maybe

Quoted 5 lines
Quoted 1 line

different settings for AC and battery power?

Yes. Matthew mentioned in other response aboue setting this based on freq. For the CPUs that support this feature currently, we don't see advantage in setting this feature at run time.

If the feature is useless, then why set it at all?

I just said changing it at run time doesn't give us benefits. Not that the feature is useless. Having the default value for the tunable in mid-range does increase energy-efficiency than the tunable being at performance level.

Thanks,
Venki

#9 lore raw

Re: [patch 2/2] x86: Manage ENERGY_PERF_BIAS based on cpufreq governor

Hi!

Quoted 11 lines
Quoted 9 lines

You should say what the setting does; you can mention below what MSR it corresponds to, but "Control IA32_ENERGY_PERF_BIAS setting" is not suitable user documentation.

Quoted 3 lines

Also, the expectation here is that kernel will do the right thing by default. The option here is to the user who_knows_what_he_is_doing to override the kernel default.

You did not give user enough information to do anything intelligent...

I have rephrased it in the newer version sent yday with more info.

Good.

Quoted 4 lines
Quoted 4 lines
Quoted 1 line
Quoted 1 line

Also... does it make change to tweak the setting during

runtime? Maybe

Quoted 2 lines
Quoted 1 line

different settings for AC and battery power?

Quoted 8 lines
Quoted 5 lines
Quoted 3 lines

Yes. Matthew mentioned in other response aboue setting this based on freq. For the CPUs that support this feature currently, we don't see advantage in setting this feature at run time.

If the feature is useless, then why set it at all?

I just said changing it at run time doesn't give us benefits. Not that

That can be only true if it does not give benefits period... AC and battery power are quite different scenarios.

Quoted 3 lines

the feature is useless. Having the default value for the tunable in mid-range does increase energy-efficiency than the tunable being at performance level.

So... what does it really do? What is the difference in power consumption, and what is the difference in performance?
Pavel

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#10 lore raw

Re: [patch 2/2] x86: Manage ENERGY_PERF_BIAS based on cpufreq governor

Quoted 2 lines · Pavel Machek

That can be only true if it does not give benefits period... AC and battery power are quite different scenarios.

No, they're not.

Signature · 1 line
Matthew Garrett | [email protected]
#11 lore raw

Re: [patch 2/2] x86: Manage ENERGY_PERF_BIAS based on cpufreq governor

Quoted 6 lines · Matthew Garrett
Quoted 2 lines · Pavel Machek

That can be only true if it does not give benefits period... AC and battery power are quite different scenarios.

No, they're not.

Yes, they are.

Would you care to elaborate? I may very well want top power on AC power, and max powersavings on battery; most people do.
Pavel

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#12 lore raw

Re: [patch 2/2] x86: Manage ENERGY_PERF_BIAS based on cpufreq governor

Quoted 6 lines · Pavel Machek
Quoted 5 lines · Matthew Garrett
Quoted 2 lines · Pavel Machek

That can be only true if it does not give benefits period... AC and battery power are quite different scenarios.

Quoted 6 lines
Quoted 1 line

No, they're not.

Yes, they are.

Would you care to elaborate? I may very well want top power on AC power, and max powersavings on battery; most people do.

You may want that. But power constraints aren't limited to battery, and being on battery doesn't inherently mean that you're power constrained. Mixing these concepts results in all kinds of issues.

Signature · 1 line
Matthew Garrett | [email protected]
#13 lore raw

Re: [patch 2/2] x86: Manage ENERGY_PERF_BIAS based on cpufreq governor

Quoted 9 lines · Matthew Garrett
Quoted 8 lines · Pavel Machek
Quoted 6 lines · Matthew Garrett
Quoted 2 lines · Pavel Machek

That can be only true if it does not give benefits period... AC and battery power are quite different scenarios.

No, they're not.

Quoted 8 lines
Quoted 4 lines

Yes, they are.

Would you care to elaborate? I may very well want top power on AC power, and max powersavings on battery; most people do.

You may want that. But power constraints aren't limited to battery, and being on battery doesn't inherently mean that you're power constrained. Mixing these concepts results in all kinds of issues.

That's of course true.

But if something gives so limited benefit that it does not make sense to tweak between power constrained and not-power-constrained environments (I used AC and battery as an example), it is useless.
Pavel

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