Support for IA32_ENERGY_PERF_BIAS MSR - v2
Subsystems (3)
PATCH 1/2 x86: Look for IA32_ENERGY_PERF_BIAS support - v2
In reply to [email protected]There is a new hardware feature, which lets system software to set Energy Performance Preference. This is a opaque knob in the form of IA32_ENERGY_PERF_BIAS MSR, which has a 4 bit Energy Performance Preference Hint. When supported, hardware can use this hint to resolve energy-performance tradeoffs. The support for this feature is indicated by CPUID.06H.ECX.bit3. Refer to Intel Architectures Software Developer's Manual for more info.
This patch, looks up for the support of this feature. It shows up as "epb" in /proc/cpuinfo flags, when supported.
--- arch/x86/include/asm/cpufeature.h | 1 + arch/x86/include/asm/msr-index.h | 2 ++ arch/x86/kernel/cpu/addon_cpuid_features.c | 1 + 3 files changed, 4 insertions(+), 0 deletions(-)
arch/x86/include/asm/cpufeature.h +1 -0
@@ -161,6 +161,7 @@*/ #define X86_FEATURE_IDA (7*32+ 0)/* Intel Dynamic Acceleration */ #define X86_FEATURE_ARAT (7*32+ 1)/* Always Running APIC Timer */ +#define X86_FEATURE_EPB (7*32+ 2)/* IA32_ENERGY_PERF_BIAS support */ /* Virtualization flags: Linux defined */ #define X86_FEATURE_TPR_SHADOW (8*32+ 0)/* Intel TPR Shadow */
arch/x86/include/asm/msr-index.h +2 -0
@@ -230,6 +230,8 @@#define MSR_IA32_MISC_ENABLE 0x000001a0 +#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 +/* MISC_ENABLE bits: architectural */ #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << 0)#define MSR_IA32_MISC_ENABLE_TCC (1ULL << 1)
arch/x86/kernel/cpu/addon_cpuid_features.c +1 -0
@@ -32,6 +32,7 @@ void __cpuinit init_scattered_cpuid_features(struct cpuinfo_x86 *c)static const struct cpuid_bit __cpuinitconst cpuid_bits[] = { {X86_FEATURE_IDA ,CR_EAX ,1 ,0x00000006 }, {X86_FEATURE_ARAT ,CR_EAX ,2 ,0x00000006 }, + {X86_FEATURE_EPB ,CR_ECX ,3 ,0x00000006 }, {X86_FEATURE_NPT ,CR_EDX ,0 ,0x8000000a }, {X86_FEATURE_LBRV ,CR_EDX ,1 ,0x8000000a }, {X86_FEATURE_SVML ,CR_EDX ,2 ,0x8000000a },
Signature · 3 lines
1.6.0.6 --
cover Support for IA32_ENERGY_PERF_BIAS MSR - v2
There is a new hardware feature, which lets system software to set Energy Performance Preference. This is a opaque knob in the form of IA32_ENERGY_PERF_BIAS MSR, which has a 4 bit Energy Performance Preference Hint.
The support for this feature is indicated by CPUID.06H.ECX.bit3. Refer to Intel Architectures Software Developer's Manual for more info.
---
Modification from first version - Revised kernel parameter documentation.
PATCH 2/2 x86: Manage ENERGY_PERF_BIAS based on cpufreq governor - v2
Manage IA32_ENERGY_PERF_BIAS setting.
By default, this driver sets IA32_ENERGY_PERF_BIAS as follows 0 when cpufreq performance governor is being used 15 when cpufreq powersave governor is being used
7 otherwise
There is an option to disable setting IA32_ENERGY_PERF_BIAS using epb=disable boot option.
There is an option to manual override IA32_ENERGY_PERF_BIAS using epb=<0..15> where user set energy_perf_bias value will be set, irrespective of cpufreq governor.
--- Documentation/kernel-parameters.txt | 10 ++ arch/x86/kernel/cpu/cpufreq/Kconfig | 6 + arch/x86/kernel/cpu/cpufreq/Makefile | 1 + arch/x86/kernel/cpu/cpufreq/energy_perf_bias.c | 186 ++++++++++++++++++++++++ 4 files changed, 203 insertions(+), 0 deletions(-) create mode 100644 arch/x86/kernel/cpu/cpufreq/energy_perf_bias.c
Documentation/kernel-parameters.txt +10 -0
@@ -759,6 +759,16 @@ and is between 256 and 4096 characters. It is defined in the file Default value is 0. Value can be changed at runtime via /selinux/enforce. + epb= [X86] Override CPU IA32_ENERGY_PERF_BIAS setting + Format: { disable | <0...15> } + IA32_ENERGY_PERF_BIAS is a 16 value knob with which + software can provide energy savings performance hint + to the CPU (0 for highest perf, 15 for energy save). + By default, kernel manages this MSR. But, user can + override it with this boot option. + "disable" - Kernel will not modify this MSR + <0..15> - Kernel will set this MSR to specified value + ether= [HW,NET] Ethernet cards parameters This option is obsoleted by the "netdev=" option, which has equivalent usage. See its documentation for details.
arch/x86/kernel/cpu/cpufreq/Kconfig +6 -0
@@ -26,6 +26,12 @@ config X86_ACPI_CPUFREQ If in doubt, say N. +config X86_ENERGY_PERF_BIAS + def_bool y + depends on X86_ACPI_CPUFREQ + help + Support for x86 Intel ENERGY_PERF_BIAS MSR + config ELAN_CPUFREQ tristate "AMD Elan SC400 and SC410" select CPU_FREQ_TABLE
arch/x86/kernel/cpu/cpufreq/Makefile +1 -0
@@ -18,3 +18,4 @@ obj-$(CONFIG_X86_SPEEDSTEP_SMI) += speedstep-smi.o obj-$(CONFIG_X86_SPEEDSTEP_CENTRINO) += speedstep-centrino.o obj-$(CONFIG_X86_P4_CLOCKMOD) += p4-clockmod.o obj-$(CONFIG_X86_CPUFREQ_NFORCE2) += cpufreq-nforce2.o +obj-$(CONFIG_X86_ENERGY_PERF_BIAS) += energy_perf_bias.o
arch/x86/kernel/cpu/cpufreq/energy_perf_bias.c new file +186 -0
186 lines not on this page · raw message
Signature · 3 lines
1.6.0.6 --
Re: [patch 2/2] x86: Manage ENERGY_PERF_BIAS based on cpufreq governor - v2
arch/x86/kernel/cpu/cpufreq/energy_perf_bias.c line 91
Quoted 9 lines · Venki Pallipadi
arch/x86/kernel/cpu/cpufreq/energy_perf_bias.c new file +9
-0+if (!strncmp (gov->name,"performance" ,strlen ("performance" ))) + epb_val =ENERGY_PERF_BIAS_PERF ; +else if (!strncmp (gov->name,"powersave" ,strlen ("powersave" ))) + epb_val =ENERGY_PERF_BIAS_POWER ; +else + epb_val =ENERGY_PERF_BIAS_ONDEMAND ; + +set_epb_on_cpu (epb_val, cpu); +return 0 ;
hardcoding a list of cpufreq governors is kinda icky, but I don't have a better solution. We'll just have to be mindful of it if we ever get around to finally making performance/powersave personalities of ondemand as was discussed years ago.
What if the governor is set to 'userspace' ? powernowd/cpufreqd are sort of ondemand-done-in-userspace, but there may also be other userspace governors we don't know about. I suppose it's not catastrophic..
Dave
RE: [patch 2/2] x86: Manage ENERGY_PERF_BIAS based on cpufreq governor - v2
Quoted 14 lines
-----Original Message-----
From: Dave Jones [mailto:[email protected]]
Sent: Thursday, March 04, 2010 3:28 PM
To: Pallipadi, Venkatesh
Cc: Ingo Molnar; H Peter Anvin; Thomas Gleixner; Len Brown; [email protected]; [email protected]; Venkatesh Pallipadi
Subject: Re: [patch 2/2] x86: ManageENERGY_PERF_BIASbased on cpufreq governor - v2On Thu, Mar 04, 2010 at 03:14:56PM -0800, Venki Pallipadi wrote:
Quoted 14 lines
arch/x86/kernel/cpu/cpufreq/energy_perf_bias.c line 91
Quoted 9 lines
arch/x86/kernel/cpu/cpufreq/energy_perf_bias.c new file +9
-0+if (!strncmp (gov->name,"performance" ,strlen ("performance" ))) + epb_val =ENERGY_PERF_BIAS_PERF ; +else if (!strncmp (gov->name,"powersave" ,strlen ("powersave" ))) + epb_val =ENERGY_PERF_BIAS_POWER ; +else + epb_val =ENERGY_PERF_BIAS_ONDEMAND ; + +set_epb_on_cpu (epb_val, cpu); +return 0 ;hardcoding a list of cpufreq governors is kinda icky, but I don't have a better solution. We'll just have to be mindful of it if we ever get around to finally making performance/powersave personalities of ondemand as was discussed years ago.
Yes. In that case we will have to find some other way to tie this to user preference.
Quoted 6 lines
What if the governor is set to 'userspace' ? powernowd/cpufreqd are sort of ondemand-done-in-userspace, but there may also be other userspace governors we don't know about. I suppose it's not catastrophic..
Userspace/ondemand/conservative can all be at middle ground here as they are mostly used where user expects adaptive kind of behaviour.
I did think about exporting this as a new tunable in /sys and let userspace deal with it. But, that doesn't help with having sane default values and users (background apps) may shoot themselves in the foot with it.
Thanks,
Venki
Len Brown
reviewerPATCH 1/1 x86: Look for IA32_ENERGY_PERF_BIAS support - v3
In reply to [email protected]From: Venkatesh Pallipadi <[email protected]>
The new IA32_ENERGY_PERF_BIAS MSR allows system software to give hardware a hint whether OS policy favors more power saving, or more performance. This allows the OS to have some influence on internal hardware power/performance tradeoffs where the OS has previously had no influence.
The support for this feature is indicated by CPUID.06H.ECX.bit3, as documented in the Intel Architectures Software Developer's Manual.
This patch discovers support of this feature and displays it as "epb" in /proc/cpuinfo.
---
lenb: v3 refreshes venki's original patch to apply to 2.6.35-rc1
arch/x86/include/asm/cpufeature.h | 1 + arch/x86/include/asm/msr-index.h | 2 ++ arch/x86/kernel/cpu/addon_cpuid_features.c | 1 + 3 files changed, 4 insertions(+), 0 deletions(-)
arch/x86/include/asm/cpufeature.h +1 -0
@@ -162,6 +162,7 @@#define X86_FEATURE_IDA (7*32+ 0)/* Intel Dynamic Acceleration */ #define X86_FEATURE_ARAT (7*32+ 1)/* Always Running APIC Timer */ #define X86_FEATURE_CPB (7*32+ 2)/* AMD Core Performance Boost */ +#define X86_FEATURE_EPB (7*32+ 3)/* IA32_ENERGY_PERF_BIAS support */ /* Virtualization flags: Linux defined */ #define X86_FEATURE_TPR_SHADOW (8*32+ 0)/* Intel TPR Shadow */
arch/x86/include/asm/msr-index.h +2 -0
@@ -238,6 +238,8 @@#define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 +#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 +/* MISC_ENABLE bits: architectural */ #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << 0)#define MSR_IA32_MISC_ENABLE_TCC (1ULL << 1)
arch/x86/kernel/cpu/addon_cpuid_features.c +1 -0
@@ -33,6 +33,7 @@ void __cpuinit init_scattered_cpuid_feat { X86_FEATURE_IDA, CR_EAX, 1, 0x00000006 }, { X86_FEATURE_ARAT, CR_EAX, 2, 0x00000006 }, { X86_FEATURE_APERFMPERF, CR_ECX, 0, 0x00000006 }, + { X86_FEATURE_EPB, CR_ECX, 3, 0x00000006 }, { X86_FEATURE_CPB, CR_EDX, 9, 0x80000007 }, { X86_FEATURE_NPT, CR_EDX, 0, 0x8000000a }, { X86_FEATURE_LBRV, CR_EDX, 1, 0x8000000a },
Len Brown
reviewerRE: [patch 2/2] x86: Manage ENERGY_PERF_BIAS based on cpufreq governor - v2
In reply to Pallipadi, VenkateshQuoted 20 lines
Quoted 5 lines
-----Original Message-----
From: Dave Jones [mailto:[email protected]]On Thu, Mar 04, 2010 at 03:14:56PM -0800, Venki Pallipadi wrote:
Quoted 14 lines
arch/x86/kernel/cpu/cpufreq/energy_perf_bias.c line 91
Quoted 9 lines
arch/x86/kernel/cpu/cpufreq/energy_perf_bias.c new file +9
-0+if (!strncmp (gov->name,"performance" ,strlen ("performance" ))) + epb_val =ENERGY_PERF_BIAS_PERF ; +else if (!strncmp (gov->name,"powersave" ,strlen ("powersave" ))) + epb_val =ENERGY_PERF_BIAS_POWER ; +else + epb_val =ENERGY_PERF_BIAS_ONDEMAND ; + +set_epb_on_cpu (epb_val, cpu); +return 0 ;hardcoding a list of cpufreq governors is kinda icky, but I don't have a better solution. We'll just have to be mindful of it if we ever get around to finally making performance/powersave personalities of ondemand as was discussed years ago.
Quoted 2 lines
Yes. In that case we will have to find some other way to tie this to user preference.
Lets cross that bridge when we come to it.
Quoted 7 lines
Quoted 4 lines
What if the governor is set to 'userspace' ? powernowd/cpufreqd are sort of ondemand-done-in-userspace, but there may also be other userspace governors we don't know about. I suppose it's not catastrophic..
Userspace/ondemand/conservative can all be at middle ground here as they are mostly used where user expects adaptive kind of behaviour.
Frankly, if somebody cares about power or performance, they shouldn't be running powernowd/cpufreqd, and so they should be blissfully ignorant and satisfied with the default, which is 'balanced'.
Quoted 4 lines
I did think about exporting this as a new tunable in /sys and let userspace deal with it. But, that doesn't help with having sane default values and users (background apps) may shoot themselves in the foot with it.
We really do need a central place for userspace to communicate power/performance bias policy to the kernel -- and for kernel drivers of all types to pick up that policy. I think that ideally the sysfs interface should be generic, and that on systems with this MSR, the MSR gets plugged into updates to that generic interface.
I think that this driver exposing the MSR to cpufreq is useful, but perhaps it is just a stepping stone to the generic I/F that we really should implement...
Len Brown,
Intel Open Source Technology Center
[tip:x86/cpu] x86: Look for IA32_ENERGY_PERF_BIAS support
In reply to Len BrownCommit-ID: 23016bf0d25d62c45d8b8f61d55b290d704f7a79 Gitweb: http://git.kernel.org/tip/23016bf0d25d62c45d8b8f61d55b290d704f7a79 Author: Venkatesh Pallipadi <[email protected]> AuthorDate: Thu, 3 Jun 2010 23:22:28 -0400 Committer: H. Peter Anvin <[email protected]> CommitDate: Wed, 16 Jun 2010 13:37:32 -0700
x86: Look for IA32_ENERGY_PERF_BIAS support
The new IA32_ENERGY_PERF_BIAS MSR allows system software to give hardware a hint whether OS policy favors more power saving, or more performance. This allows the OS to have some influence on internal hardware power/performance tradeoffs where the OS has previously had no influence.
The support for this feature is indicated by CPUID.06H.ECX.bit3, as documented in the Intel Architectures Software Developer's Manual.
This patch discovers support of this feature and displays it as "epb" in /proc/cpuinfo.
LKML-Reference: <[email protected]>
--- arch/x86/include/asm/cpufeature.h | 1 + arch/x86/include/asm/msr-index.h | 2 ++ arch/x86/kernel/cpu/addon_cpuid_features.c | 1 + 3 files changed, 4 insertions(+), 0 deletions(-)
arch/x86/include/asm/cpufeature.h +1 -0
@@ -162,6 +162,7 @@#define X86_FEATURE_IDA (7*32+ 0)/* Intel Dynamic Acceleration */ #define X86_FEATURE_ARAT (7*32+ 1)/* Always Running APIC Timer */ #define X86_FEATURE_CPB (7*32+ 2)/* AMD Core Performance Boost */ +#define X86_FEATURE_EPB (7*32+ 3)/* IA32_ENERGY_PERF_BIAS support */ /* Virtualization flags: Linux defined */ #define X86_FEATURE_TPR_SHADOW (8*32+ 0)/* Intel TPR Shadow */
arch/x86/include/asm/msr-index.h +2 -0
@@ -238,6 +238,8 @@#define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 +#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 +/* MISC_ENABLE bits: architectural */ #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << 0)#define MSR_IA32_MISC_ENABLE_TCC (1ULL << 1)
arch/x86/kernel/cpu/addon_cpuid_features.c +1 -0
@@ -33,6 +33,7 @@ void __cpuinit init_scattered_cpuid_features(struct cpuinfo_x86 *c) { X86_FEATURE_IDA, CR_EAX, 1, 0x00000006 }, { X86_FEATURE_ARAT, CR_EAX, 2, 0x00000006 }, { X86_FEATURE_APERFMPERF, CR_ECX, 0, 0x00000006 }, + { X86_FEATURE_EPB, CR_ECX, 3, 0x00000006 }, { X86_FEATURE_CPB, CR_EDX, 9, 0x80000007 }, { X86_FEATURE_NPT, CR_EDX, 0, 0x8000000a }, { X86_FEATURE_LBRV, CR_EDX, 1, 0x8000000a },