Add basic support for Telechips TCC8xxx SoCs

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+/*
+ * Copyright (C) 1999 ARM Limited
+ * Copyright (C) 2000 RidgeRun, Inc.
+ * Copyright (C) 2008-2009 Telechips
+ * Copyright (C) 2010 Hans J. Koch <[email protected]>
+ *
+ * Licensed under the terms of the GPL v2.
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET		UL(0x20000000)
+
+#endif
+

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+/*
+ * Author: <[email protected]>
+ * Created: June 10, 2008
+ * Description: LINUX SYSTEM FUNCTIONS for TCC83x
+ *
+ * Copyright (C) 2008-2009 Telechips
+ *
+ * Licensed under the terms of the GPL v2.
+ *
+ */
+
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+#include <linux/clk.h>
+
+#include <asm/mach-types.h>
+#include <mach/hardware.h>
+
+extern void plat_tcc_reboot(void);
+
+static inline void arch_idle(void)
+{
+	cpu_do_idle();
+}
+
+static inline void arch_reset(char mode, const char *cmd)
+{
+	plat_tcc_reboot();
+}
+
+#endif

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+/*
+ * Copyright (C) 2009 Hans J. Koch <[email protected]>
+ *
+ * This file is licensed under the terms of the GPL version 2.
+ */
+
+#include <linux/serial_reg.h>
+#include <linux/types.h>
+
+#include <mach/tcc8k-regs.h>
+
+unsigned int system_rev;
+
+#define ID_MASK			0x7fff
+
+static void putc(int c)
+{
+	u32 *uart_lsr = (u32 *)(UART_BASE_PHYS + (UART_LSR << 2));
+	u32 *uart_tx = (u32 *)(UART_BASE_PHYS + (UART_TX << 2));
+
+	while (!(*uart_lsr & UART_LSR_THRE))
+		barrier();
+	*uart_tx = c;
+}
+
+static inline void flush(void)
+{
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()

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+/*
+ * Author: <[email protected]>
+ * Created: June 10, 2008
+ *
+ * Copyright (C) 2000 Russell King.
+ * Copyright (C) 2008-2009 Telechips
+ *
+ * Licensed under the terms of the GPL v2.
+ */
+#define VMALLOC_END	0xf0000000UL
+

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+/*
+ * System functions for Telechips TCCxxxx SoCs
+ *
+ * Copyright (C) Hans J. Koch <[email protected]>
+ *
+ * Licensed under the terms of the GPL v2.
+ *
+ */
+
+#include <linux/io.h>
+
+#include <mach/tcc8k-regs.h>
+
+/* System reboot */
+void plat_tcc_reboot(void)
+{
+	/* Make sure clocks are on */
+	__raw_writel(0xffffffff, CKC_BASE + BCLKCTR0_OFFS);
+
+	/* Enable watchdog reset */
+	__raw_writel(0x49, TIMER_BASE + TWDCFG_OFFS);
+	/* Wait for reset */
+	while(1)
+		;
+}
+

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+#ifndef __ASM_MACH_CLKDEV_H
+#define __ASM_MACH_CLKDEV_H
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif

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index f3243eb..7a40aef 100644
@@ -30,13 +30,13 @@
 #define EXT_MEM_CTRL_BASE	0xf0000000
 #define EXT_MEM_CTRL_SIZE	SZ_4K
 
-#define CS1_BASE_VIRT		0xf7000000
-#define AHB_PERI_BASE_VIRT	0xf4000000
-#define APB0_PERI_BASE_VIRT	0xf1000000
-#define APB1_PERI_BASE_VIRT	0xf2000000
-#define EXT_MEM_CTRL_BASE_VIRT	0xf3000000
-#define INT_SRAM_BASE_VIRT	0xf5000000
-#define DATA_TCM_BASE_VIRT	0xf6000000
+#define CS1_BASE_VIRT		(void __iomem *)0xf7000000
+#define AHB_PERI_BASE_VIRT	(void __iomem *)0xf4000000
+#define APB0_PERI_BASE_VIRT	(void __iomem *)0xf1000000
+#define APB1_PERI_BASE_VIRT	(void __iomem *)0xf2000000
+#define EXT_MEM_CTRL_BASE_VIRT	(void __iomem *)0xf3000000
+#define INT_SRAM_BASE_VIRT	(void __iomem *)0xf5000000
+#define DATA_TCM_BASE_VIRT	(void __iomem *)0xf6000000
 
 #define __REG(x)     (*((volatile u32 *)(x)))
 

@@ -649,8 +649,7 @@
 #define PMGPIO_APB_OFFS		0x800
 
 /* Clock controller registers */
-#define CKC_BASE		(APB1_PERI_BASE_VIRT + 0x6000)
-#define CKC_BASE_PHYS		(APB1_PERI_BASE + 0x6000)
+#define CKC_BASE	((void __iomem *)(APB1_PERI_BASE_VIRT + 0x6000))
 
 #define CLKCTRL_OFFS		0x00
 #define PLL0CFG_OFFS		0x04

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+/*
+ * A definition needed by arch core code.
+ *
+ */
+#define CLOCK_TICK_RATE		(HZ * 100000UL)

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+/*
+ * IO definitions for TCC8000 processors and boards
+ *
+ * Copyright (C) 1997-1999 Russell King
+ * Copyright (C) 2008-2009 Telechips
+ * Copyright (C) 2010 Hans J. Koch <[email protected]>
+ *
+ * Licensed under the terms of the GNU Public License version 2.
+ */
+
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * We don't actually have real ISA nor PCI buses, but there is so many
+ * drivers out there that might just work if we fake them...
+ */
+#define __io(a)			__typesafe_io(a)
+#define __mem_pci(a)		(a)
+
+#endif

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+/*
+ * Some defines for arch/arm/mach-tcc8k/board-tcc8000-sdk.c
+ *
+ */
+
+#ifndef _BOARD_TCC_8000_SDK_H_
+#define _BOARD_TCC_8000_SDK_H_
+
+extern void __init tcc8k_init_irq(void);
+extern void __init tcc8k_map_common_io(void);
+extern int __init tcc_clocks_init(unsigned long xi_freq,
+					unsigned long xti_freq);
+extern struct platform_device tcc_nand_device;
+
+#define XI_FREQUENCY	12000000
+#define XTI_FREQUENCY	32768
+
+#endif

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+#ifndef __ASM_MACH_CLKDEV_H
+#define __ASM_MACH_CLKDEV_H
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif

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index f3243eb..1786867 100644
@@ -30,13 +30,13 @@
 #define EXT_MEM_CTRL_BASE	0xf0000000
 #define EXT_MEM_CTRL_SIZE	SZ_4K
 
-#define CS1_BASE_VIRT		0xf7000000
-#define AHB_PERI_BASE_VIRT	0xf4000000
-#define APB0_PERI_BASE_VIRT	0xf1000000
-#define APB1_PERI_BASE_VIRT	0xf2000000
-#define EXT_MEM_CTRL_BASE_VIRT	0xf3000000
-#define INT_SRAM_BASE_VIRT	0xf5000000
-#define DATA_TCM_BASE_VIRT	0xf6000000
+#define CS1_BASE_VIRT		(void __iomem *)0xf7000000
+#define AHB_PERI_BASE_VIRT	(void __iomem *)0xf4000000
+#define APB0_PERI_BASE_VIRT	(void __iomem *)0xf1000000
+#define APB1_PERI_BASE_VIRT	(void __iomem *)0xf2000000
+#define EXT_MEM_CTRL_BASE_VIRT	(void __iomem *)0xf3000000
+#define INT_SRAM_BASE_VIRT	(void __iomem *)0xf5000000
+#define DATA_TCM_BASE_VIRT	(void __iomem *)0xf6000000
 
 #define __REG(x)     (*((volatile u32 *)(x)))
 

@@ -649,8 +649,7 @@
 #define PMGPIO_APB_OFFS		0x800
 
 /* Clock controller registers */
-#define CKC_BASE		(APB1_PERI_BASE_VIRT + 0x6000)
-#define CKC_BASE_PHYS		(APB1_PERI_BASE + 0x6000)
+#define CKC_BASE	((void __iomem *)(APB1_PERI_BASE_VIRT + 0x6000))
 
 #define CLKCTRL_OFFS		0x00
 #define PLL0CFG_OFFS		0x04

@@ -724,8 +723,20 @@
 /* SWRESET1 bits */
 #define SWRESET1_USBH1		(1 << 20)
 
-/* System clock sources */
+/* System clock sources. 
+ * Note: These are the clock sources that serve as parents for
+ * all other clocks. They have no parents themselves.
+ *
+ * These values are used for struct clk->root_id. All clocks
+ * that are not system clock sources have this value set to
+ * CLK_SRC_NOROOT. 
+ * The values for system clocks start with CLK_SRC_PLL0 == 0
+ * because this gives us exactly the values needed for the lower
+ * 4 bits of ACLK_* registers. Therefore, CLK_SRC_NOROOT is
+ * defined as -1 to not disturb the order.
+ */
 enum root_clks {
+	CLK_SRC_NOROOT = -1,
 	CLK_SRC_PLL0 = 0,
 	CLK_SRC_PLL1,
 	CLK_SRC_PLL0DIV,

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+#ifndef __ASM_MACH_CLKDEV_H
+#define __ASM_MACH_CLKDEV_H
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif

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@@ -30,13 +30,13 @@
 #define EXT_MEM_CTRL_BASE	0xf0000000
 #define EXT_MEM_CTRL_SIZE	SZ_4K
 
-#define CS1_BASE_VIRT		0xf7000000
-#define AHB_PERI_BASE_VIRT	0xf4000000
-#define APB0_PERI_BASE_VIRT	0xf1000000
-#define APB1_PERI_BASE_VIRT	0xf2000000
-#define EXT_MEM_CTRL_BASE_VIRT	0xf3000000
-#define INT_SRAM_BASE_VIRT	0xf5000000
-#define DATA_TCM_BASE_VIRT	0xf6000000
+#define CS1_BASE_VIRT		(void __iomem *)0xf7000000
+#define AHB_PERI_BASE_VIRT	(void __iomem *)0xf4000000
+#define APB0_PERI_BASE_VIRT	(void __iomem *)0xf1000000
+#define APB1_PERI_BASE_VIRT	(void __iomem *)0xf2000000
+#define EXT_MEM_CTRL_BASE_VIRT	(void __iomem *)0xf3000000
+#define INT_SRAM_BASE_VIRT	(void __iomem *)0xf5000000
+#define DATA_TCM_BASE_VIRT	(void __iomem *)0xf6000000
 
 #define __REG(x)     (*((volatile u32 *)(x)))
 

@@ -649,8 +649,7 @@
 #define PMGPIO_APB_OFFS		0x800
 
 /* Clock controller registers */
-#define CKC_BASE		(APB1_PERI_BASE_VIRT + 0x6000)
-#define CKC_BASE_PHYS		(APB1_PERI_BASE + 0x6000)
+#define CKC_BASE	((void __iomem *)(APB1_PERI_BASE_VIRT + 0x6000))
 
 #define CLKCTRL_OFFS		0x00
 #define PLL0CFG_OFFS		0x04

@@ -724,8 +723,20 @@
 /* SWRESET1 bits */
 #define SWRESET1_USBH1		(1 << 20)
 
-/* System clock sources */
+/* System clock sources. 
+ * Note: These are the clock sources that serve as parents for
+ * all other clocks. They have no parents themselves.
+ *
+ * These values are used for struct clk->root_id. All clocks
+ * that are not system clock sources have this value set to
+ * CLK_SRC_NOROOT. 
+ * The values for system clocks start with CLK_SRC_PLL0 == 0
+ * because this gives us exactly the values needed for the lower
+ * 4 bits of ACLK_* registers. Therefore, CLK_SRC_NOROOT is
+ * defined as -1 to not disturb the order.
+ */
 enum root_clks {
+	CLK_SRC_NOROOT = -1,
 	CLK_SRC_PLL0 = 0,
 	CLK_SRC_PLL1,
 	CLK_SRC_PLL0DIV,