Skip to contentSkip to conversation

sh: boot kernel with SR.BL set

PATCH In review Magnus Damm 2 participants 2 messages Sep 24, 2010 – Sep 30, 2010 SuperH

lore
Share & tools
lore
#0 lore raw

PATCH 1/1 sh: boot kernel with SR.BL set

From: Magnus Damm <[email protected]>

Update the SH kernel to keep SR.BL set until the VBR register has been initialized. Useful to allow boot of the kernel even though exceptions are pending.

Without this patch there is a window of time when exceptions such as NMI are enabled but no exception handlers are installed.

This patch modifies both the zImage loader and the actual kernel to boot with BL=1, but the zImage loader is modfied in such a way that the init_sr value is unchanged to not break the zImage loader provided by kexec.

Tested on sh7724 Ecovec and on the SH4AL-DSP core included in sh7372.

---

 arch/sh/boot/compressed/head_32.S |    4 +++-
 arch/sh/kernel/head_32.S          |    2 +-
 arch/sh/kernel/traps_32.c         |    3 +++
 3 files changed, 7 insertions(+), 2 deletions(-)
arch/sh/boot/compressed/head_32.S +3 -1
@@ -91,7 +91,9 @@ bss_start_addr:
 end_addr:
 	.long	_end
 init_sr:
-	.long	0x400000F0	/* Privileged mode, Bank=0, Block=0, IMASK=0xF */
+	.long	0x500000F0	/* Privileged mode, Bank=0, Block=1, IMASK=0xF */
+kexec_magic:
+	.long	0x400000F0	/* magic used by kexec to parse zImage format */
 init_stack_addr:
 	.long	stack_start
 decompress_kernel_addr:
arch/sh/kernel/head_32.S +1 -1
@@ -330,7 +330,7 @@ ENTRY(_stext)
 #if defined(CONFIG_CPU_SH2)
 1:	.long	0x000000F0		! IMASK=0xF
 #else
-1:	.long	0x400080F0		! MD=1, RB=0, BL=0, FD=1, IMASK=0xF
+1:	.long	0x500080F0		! MD=1, RB=0, BL=1, FD=1, IMASK=0xF
 #endif
 ENTRY(stack_start)
 2:	.long	init_thread_union+THREAD_SIZE
arch/sh/kernel/traps_32.c +3 -0
@@ -802,6 +802,9 @@ void __cpuinit per_cpu_trap_init(void)
 		     : /* no output */
 		     : "r" (&vbr_base)
 		     : "memory");
+
+	/* disable exception blocking now when the vbr has been setup */
+	clear_bl_bit();
 }
 
 void *set_exception_table_vec(unsigned int vec, void *handler)
#1 lore raw
Quoted 16 lines · Magnus Damm

From: Magnus Damm <[email protected]>

Update the SH kernel to keep SR.BL set until the VBR register has been initialized. Useful to allow boot of the kernel even though exceptions are pending.

Without this patch there is a window of time when exceptions such as NMI are enabled but no exception handlers are installed.

This patch modifies both the zImage loader and the actual kernel to boot with BL=1, but the zImage loader is modfied in such a way that the init_sr value is unchanged to not break the zImage loader provided by kexec.

Quoted 4 lines

Tested on sh7724 Ecovec and on the SH4AL-DSP core included in sh7372.

I've applied this, but in the future make sure you update all of the CPUs when making changes to the boot path. Presently this is introducing a divergence for all of the nommu parts which we do not want.