s3fb: fix 15/16bpp modes with over 115MHz pixclocks on 86C365 Trio3D
PATCH 3/5 s3fb: fix 15/16bpp modes with over 115MHz pixclocks on 86C365 Trio3D
Enable pixel multiplexing in 15/16bpp modes when pixclock is over 115MHz on Trio3D (86C365) cards to fix artifacts on the left side of screen.
Signed-off-by Ondrej Zary <[email protected]>
drivers/video/s3fb.c +18 -0
@@ -675,6 +675,15 @@svga_wcrt_mask (par->state.vgabase,0x67 ,0x20 ,0xF0 ); else svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); + }else if (par->chip =CHIP_365_TRIO3D ) { +svga_wcrt_mask (par->state.vgabase,0x50 ,0x10 ,0x30 ); +if (info->var.pixclock >8695 ) { +svga_wcrt_mask (par->state.vgabase,0x67 ,0x30 ,0xF0 ); + hmul =2 ; + }else { +svga_wcrt_mask (par->state.vgabase,0x67 ,0x20 ,0xF0 ); + multiplex =1 ; + } }else {svga_wcrt_mask (par->state.vgabase,0x50 ,0x10 ,0x30 );svga_wcrt_mask (par->state.vgabase,0x67 ,0x30 ,0xF0 );
@@ -691,6 +700,15 @@svga_wcrt_mask (par->state.vgabase,0x67 ,0x40 ,0xF0 ); else svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); + }else if (par->chip =CHIP_365_TRIO3D ) { +svga_wcrt_mask (par->state.vgabase,0x50 ,0x10 ,0x30 ); +if (info->var.pixclock >8695 ) { +svga_wcrt_mask (par->state.vgabase,0x67 ,0x50 ,0xF0 ); + hmul =2 ; + }else { +svga_wcrt_mask (par->state.vgabase,0x67 ,0x40 ,0xF0 ); + multiplex =1 ; + } }else {svga_wcrt_mask (par->state.vgabase,0x50 ,0x10 ,0x30 );svga_wcrt_mask (par->state.vgabase,0x67 ,0x50 ,0xF0 );
Signature · 1 line
Ondrej Zary
Quoted 4 lines · Ondrej Zary
Enable pixel multiplexing in 15/16bpp modes when pixclock is over 115MHz on Trio3D (86C365) cards to fix artifacts on the left side of screen.
Signed-off-by Ondrej Zary <[email protected]>
Acked-by Ondrej Zajicek <[email protected]>
Signature · 5 lines
Elen sila lumenn' omentielvo Ondrej 'SanTiago' Zajicek (email: [email protected]) OpenPGP encrypted e-mails preferred (KeyID 0x11DEADC3, wwwkeys.pgp.net) "To err is human -- to blame it on a computer is even more so."