x86/cpu changes for v2.6.40
Subsystems (4)
Linus,
Please pull the latest x86-cpu-for-linus git tree from:
git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip.git x86-cpu-for-linus
Thanks,
Ingo
------------------>
Borislav Petkov (2):
x86, AMD, cacheinfo: Fix fallout caused by max3 conversion Documentation, ABI: Update L3 cache index disable text
Frank Arnold (1):
x86, AMD, cacheinfo: Fix L3 cache index disable checks
H. Peter Anvin (3):
x86, percpu: Use ASM_NOP4 instead of hardcoding P6_NOP4 x86, cpu: Clean up and unify the NOP selection infrastructure x86, cpu: Change NOP selection for certain Intel CPUs
Ian Campbell (1):
x86, cpu: Move AMD Elan Kconfig under "Processor family"
Ondrej Zary (1):
x86, cpu: Fix detection of Celeron Covington stepping A1 and B0
Documentation/ABI/testing/sysfs-devices-system-cpu | 34 ++-- arch/x86/Kconfig | 11 - arch/x86/Kconfig.cpu | 16 +- arch/x86/Makefile_32.cpu | 2 +- arch/x86/include/asm/alternative.h | 8 - arch/x86/include/asm/module.h | 2 +- arch/x86/include/asm/nops.h | 146 +++++++++------- arch/x86/include/asm/percpu.h | 2 +- arch/x86/kernel/alternative.c | 194 +++++++++++-------- arch/x86/kernel/cpu/cpufreq/Kconfig | 4 +- arch/x86/kernel/cpu/intel.c | 10 +- arch/x86/kernel/cpu/intel_cacheinfo.c | 20 +-- arch/x86/kernel/ftrace.c | 4 +- arch/x86/kernel/jump_label.c | 5 +- arch/x86/kernel/setup.c | 6 +- 15 files changed, 242 insertions(+), 222 deletions(-)
Documentation/ABI/testing/sysfs-devices-system-cpu +17 -17
@@ -183,21 +183,21 @@ Description: Discover and change clock speed of CPUs to learn how to control the knobs. -What: /sys/devices/system/cpu/cpu*/cache/index*/cache_disable_X -Date: August 2008 +What: /sys/devices/system/cpu/cpu*/cache/index3/cache_disable_{0,1} +Date: August 2008 KernelVersion: 2.6.27 -Contact: [email protected] -Description: These files exist in every cpu's cache index directories. - There are currently 2 cache_disable_# files in each - directory. Reading from these files on a supported - processor will return that cache disable index value - for that processor and node. Writing to one of these - files will cause the specificed cache index to be disabled. - - Currently, only AMD Family 10h Processors support cache index - disable, and only for their L3 caches. See the BIOS and - Kernel Developer's Guide at - http://support.amd.com/us/Embedded_TechDocs/31116-Public-GH-BKDG_3-28_5-28-09.pdf - for formatting information and other details on the - cache index disable. -Users: [email protected] +Contact: [email protected] +Description: Disable L3 cache indices + + These files exist in every CPU's cache/index3 directory. Each + cache_disable_{0,1} file corresponds to one disable slot which + can be used to disable a cache index. Reading from these files + on a processor with this functionality will return the currently + disabled index for that node. There is one L3 structure per + node, or per internal node on MCM machines. Writing a valid + index to one of these files will cause the specificed cache + index to be disabled. + + All AMD processors with L3 caches provide this functionality. + For details, see BKDGs at + http://developer.amd.com/documentation/guides/Pages/default.aspx
arch/x86/Kconfig +0 -11
@@ -365,17 +365,6 @@ config X86_UV # Following is an alphabetically sorted list of 32 bit extended platforms # Please maintain the alphabetic order if and when there are additions -config X86_ELAN - bool "AMD Elan" - depends on X86_32 - depends on X86_EXTENDED_PLATFORM - ---help--- - Select this for an AMD Elan processor. - - Do not use this option for K6/Athlon/Opteron processors! - - If unsure, choose "PC-compatible" instead. - config X86_INTEL_CE bool "CE4100 TV platform" depends on PCI
arch/x86/Kconfig.cpu +10 -6
@@ -1,6 +1,4 @@ # Put here option for CPU selection and depending optimization -if !X86_ELAN - choice prompt "Processor family" default M686 if X86_32
@@ -203,6 +201,14 @@ config MWINCHIP3D stores for this CPU, which can increase performance of some operations. +config MELAN + bool "AMD Elan" + depends on X86_32 + ---help--- + Select this for an AMD Elan processor. + + Do not use this option for K6/Athlon/Opteron processors! + config MGEODEGX1 bool "GeodeGX1" depends on X86_32
@@ -292,8 +298,6 @@ config X86_GENERIC This is really intended for distributors who need more generic optimizations. -endif - # # Define implied options from the CPU selection here config X86_INTERNODE_CACHE_SHIFT
@@ -312,7 +316,7 @@ config X86_L1_CACHE_SHIFT int default "7" if MPENTIUM4 || MPSC default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MATOM || MVIAC7 || X86_GENERIC || GENERIC_CPU - default "4" if X86_ELAN || M486 || M386 || MGEODEGX1 + default "4" if MELAN || M486 || M386 || MGEODEGX1 default "5" if MWINCHIP3D || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX config X86_XADD
@@ -358,7 +362,7 @@ config X86_POPAD_OK config X86_ALIGNMENT_16 def_bool y - depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || X86_ELAN || MK6 || M586MMX || M586TSC || M586 || M486 || MVIAC3_2 || MGEODEGX1 + depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MELAN || MK6 || M586MMX || M586TSC || M586 || M486 || MVIAC3_2 || MGEODEGX1 config X86_INTEL_USERCOPY def_bool y
arch/x86/Makefile_32.cpu +1 -1
@@ -37,7 +37,7 @@ cflags-$(CONFIG_MATOM) += $(call cc-option,-march=atom,$(call cc-option,-march= $(call cc-option,-mtune=atom,$(call cc-option,-mtune=generic)) # AMD Elan support -cflags-$(CONFIG_X86_ELAN) += -march=i486 +cflags-$(CONFIG_MELAN) += -march=i486 # Geode GX1 support cflags-$(CONFIG_MGEODEGX1) += -march=pentium-mmx
arch/x86/include/asm/alternative.h +0 -8
@@ -191,12 +191,4 @@ extern void *text_poke(void *addr, const void *opcode, size_t len);extern void *text_poke_smp (void *addr,const void *opcode,size_t len);extern void text_poke_smp_batch (struct text_poke_param *params,int n); -#if defined(CONFIG_DYNAMIC_FTRACE ) || defined(HAVE_JUMP_LABEL ) -#define IDEAL_NOP_SIZE_5 5 -extern unsigned char ideal_nop5[IDEAL_NOP_SIZE_5 ]; -extern void arch_init_ideal_nop5 (void ); -#else -static inline void arch_init_ideal_nop5 (void ) {} -#endif -#endif /* _ASM_X86_ALTERNATIVE_H */
arch/x86/include/asm/module.h +1 -1
@@ -35,7 +35,7 @@#define MODULE_PROC_FAMILY "K7 "#elif definedCONFIG_MK8 #define MODULE_PROC_FAMILY "K8 " -#elif definedCONFIG_X86_ELAN +#elif definedCONFIG_MELAN #define MODULE_PROC_FAMILY "ELAN "#elif definedCONFIG_MCRUSOE #define MODULE_PROC_FAMILY "CRUSOE "
arch/x86/include/asm/nops.h +84 -62
183 lines not on this page · raw message
arch/x86/include/asm/percpu.h +1 -1
@@ -517,7 +517,7 @@ do { \typeof (o2) __o2 = o2; \typeof (o2) __n2 = n2; \typeof (o2) __dummy; \ - alternative_io("call this_cpu_cmpxchg16b_emu\n\t" P6_NOP4, \ + alternative_io("call this_cpu_cmpxchg16b_emu\n\t" ASM_NOP4, \ "cmpxchg16b " __percpu_prefix "(%%rsi)\n\tsetz %0\n\t", \ X86_FEATURE_CX16, \ ASM_OUTPUT2("=a"(__ret), "=d"(__dummy)), \
arch/x86/kernel/alternative.c +112 -82
262 lines not on this page · raw message
arch/x86/kernel/cpu/cpufreq/Kconfig +2 -2
@@ -43,7 +43,7 @@ config X86_ACPI_CPUFREQ config ELAN_CPUFREQ tristate "AMD Elan SC400 and SC410" select CPU_FREQ_TABLE - depends on X86_ELAN + depends on MELAN ---help--- This adds the CPUFreq driver for AMD Elan SC400 and SC410 processors.
@@ -59,7 +59,7 @@ config ELAN_CPUFREQ config SC520_CPUFREQ tristate "AMD Elan SC520" select CPU_FREQ_TABLE - depends on X86_ELAN + depends on MELAN ---help--- This adds the CPUFreq driver for AMD Elan SC520 processor.
arch/x86/kernel/cpu/intel.c +4 -6
@@ -400,12 +400,10 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)switch (c->x86_model) {case 5 : -if (c->x86_mask ==0 ) { -if (l2 ==0 ) - p ="Celeron (Covington)" ; -else if (l2 ==256 ) - p ="Mobile Pentium II (Dixon)" ; - } +if (l2 ==0 ) + p ="Celeron (Covington)" ; +else if (l2 ==256 ) + p ="Mobile Pentium II (Dixon)" ;break ;case 6 :
arch/x86/kernel/cpu/intel_cacheinfo.c +4 -16
@@ -327,7 +327,6 @@ static void __cpuinit amd_calc_l3_indices(struct amd_l3_cache *l3) l3->subcaches[2 ] = sc2 = !(val &BIT (8 )) + !(val &BIT (9 )); l3->subcaches[3 ] = sc3 = !(val &BIT (12 )) + !(val &BIT (13 )); - l3->indices = (max (max (max (sc0, sc1), sc2), sc3) <<10 ) -1 ; l3->indices = (max (max3 (sc0, sc1, sc2), sc3) <<10 ) -1 ; }
@@ -454,27 +453,16 @@ int amd_set_l3_disable_slot(struct amd_l3_cache *l3, int cpu, unsigned slot, {int ret =0 ; -#define SUBCACHE_MASK (3UL << 20) -#define SUBCACHE_INDEX 0xfff - -/* -* check whether this slot is already used or -* the index is already disabled -*/ +/* check if @slot is already used or the index is already disabled */ ret =amd_get_l3_disable_slot (l3, slot);if (ret >=0 )return -EINVAL ; -/* -* check whether the other slot has disabled the -* same index already -*/ -if (index ==amd_get_l3_disable_slot (l3, !slot)) +if (index > l3->indices)return -EINVAL ; -/* do not allow writes outside of allowed bits */ -if ((index & ~(SUBCACHE_MASK |SUBCACHE_INDEX )) || - ((index &SUBCACHE_INDEX ) > l3->indices)) +/* check whether the other slot has disabled the same index already */ +if (index ==amd_get_l3_disable_slot (l3, !slot))return -EINVAL ;amd_l3_disable_index (l3, cpu, slot, index);
arch/x86/kernel/ftrace.c +2 -2
@@ -260,9 +260,9 @@ do_ftrace_mod_code(unsigned long ip, void *new_code)return mod_code_status; } -static unsigned char *ftrace_nop_replace (void ) +static const unsigned char *ftrace_nop_replace (void ) { -return ideal_nop5; +return ideal_nops[NOP_ATOMIC5 ]; } static int
arch/x86/kernel/jump_label.c +3 -2
@@ -34,7 +34,7 @@ void arch_jump_label_transform(struct jump_entry *entry, code.offset = entry->target - (entry->code +JUMP_LABEL_NOP_SIZE ); }else -memcpy (&code, ideal_nop5,JUMP_LABEL_NOP_SIZE ); +memcpy (&code, ideal_nops[NOP_ATOMIC5 ],JUMP_LABEL_NOP_SIZE );get_online_cpus ();mutex_lock (&text_mutex);text_poke_smp ((void *)entry->code, &code,JUMP_LABEL_NOP_SIZE );
@@ -44,7 +44,8 @@ void arch_jump_label_transform(struct jump_entry *entry,void arch_jump_label_text_poke_early (jump_label_t addr) { -text_poke_early ((void *)addr, ideal_nop5,JUMP_LABEL_NOP_SIZE ); +text_poke_early ((void *)addr, ideal_nops[NOP_ATOMIC5 ], +JUMP_LABEL_NOP_SIZE ); }#endif
arch/x86/kernel/setup.c +1 -5
@@ -691,8 +691,6 @@ early_param("reservelow", parse_reservelow);void __init setup_arch (char **cmdline_p) { -unsigned long flags; -#ifdef CONFIG_X86_32 memcpy (&boot_cpu_data, &new_cpu_data,sizeof (new_cpu_data));visws_early_detect ();
@@ -1036,9 +1034,7 @@ void __init setup_arch(char **cmdline_p)mcheck_init (); -local_irq_save (flags); -arch_init_ideal_nop5 (); -local_irq_restore (flags); +arch_init_ideal_nops (); }#ifdef CONFIG_X86_32