perf_events: update extra shared registers management

Peter,

The following revised patch seems to work for me on top of my series (well, the modified one with irqsave):

$ syst_count -c 0 -p  -e offcore_response_0:dmnd_data_rd:k,\
		    offcore_response_0:dmnd_rfo:u,\
		    offcore_response_0:dmnd_rfo:k,\
		    offcore_response_0:dmnd_data_rd:u

CPU0   G0  478  offcore_response_0:dmnd_data_rd:k (scaling 0.00%, ena=997285681, run=997285681) 
CPU0   G0  163  offcore_response_0:dmnd_rfo (scaling 0.00%, ena=997285681, run=997285681) 
CPU0   G0  163  offcore_response_0:dmnd_rfo (scaling 0.00%, ena=997285681, run=997285681) 
CPU0   G0  0    offcore_response_0:dmnd_data_rd:u (scaling 0.00%, ena=997285681, run=997285681) 

Subject: perf, intel: Try alternative OFFCORE encoding
From: Peter Zijlstra <[email protected]>
Date: Mon May 23 11:08:15 CEST 2011

Since the OFFCORE registers are fully symmetric, try the other when the speficied one is already taken.

---

index d6ad9c2..59e7004 100644
@@ -326,9 +326,12 @@ struct x86_pmu {
 	 * Extra registers for events
 	 */
 	struct extra_reg *extra_regs;
-	bool regs_no_ht_sharing;
+	unsigned int er_flags;
 };
 
+#define ERF_NO_HT_SHARING	1
+#define ERF_HAS_RSP_1		2
+
 static struct x86_pmu x86_pmu __read_mostly;
 
 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {

index 941f40d..1671cd8 100644
@@ -544,6 +544,7 @@ struct hw_perf_event_extra {
 	unsigned int	reg;	/* register address or index */
 	int		alloc;	/* extra register already allocated */
 	int		idx;	/* index in shared_regs->regs[] */
+	int		alt_cnt;/* number of alternate indexes tried */
 };
 
 /**