perf, x86: P4 PMU - Introduce event alias feature v2
Subsystems (2)
PATCH 1/1 perf, x86: P4 PMU - Introduce event alias feature v2
Instead of hw_nmi_watchdog_set_attr() weak function and appropriate x86_pmu::hw_watchdog_set_attr() call we introduce an event alias mechanism.
This allow us to drop this routines completely and isolate quirks of Netburst architecture inside P4 PMU code only.
The main idea remains the same though -- to allow nmi-watchdog and perf top run simultaneously.
v2: A number of typo fixes pointed out by Ingo Molnar.
Signed-off-by Cyrill Gorcunov <[email protected]>
Acked-by Don Zickus <[email protected]>
CC Steven Rostedt <[email protected]>
CC Ingo Molnar <[email protected]>
CC Peter Zijlstra <[email protected]>
CC Stephane Eranian <[email protected]>
CC Lin Ming <[email protected]>
CC Arnaldo Carvalho de Melo <[email protected]>
CC Frederic Weisbecker <[email protected]>
---
I hope this one will fit better
arch/x86/include/asm/perf_event_p4.h | 33 ++++++++ arch/x86/kernel/cpu/perf_event.c | 7 - arch/x86/kernel/cpu/perf_event_p4.c | 129 +++++++++++++++++++++++++++-------- kernel/watchdog.c | 2 4 files changed, 133 insertions(+), 38 deletions(-)
arch/x86/include/asm/perf_event_p4.h +33 -0
@@ -102,6 +102,14 @@#define P4_CONFIG_HT (1ULL << P4_CONFIG_HT_SHIFT)/* +* If an event has alias it should be marked +* with a special bit. (Don't forget to check +* P4_PEBS_CONFIG_MASK and related bits on +* modification.) +*/ +#define P4_CONFIG_ALIASABLE (1 << 9) + +/* * The bits we allow to pass for RAW events */ #define P4_CONFIG_MASK_ESCR \
@@ -123,6 +131,31 @@ (p4_config_pack_escr (P4_CONFIG_MASK_ESCR )) | \ (p4_config_pack_cccr (P4_CONFIG_MASK_CCCR )) +/* +* In case of event aliasing we need to preserve some +* caller bits, otherwise the mapping won't be complete. + */ +#define P4_CONFIG_EVENT_ALIAS_MASK \ + (p4_config_pack_escr(P4_CONFIG_MASK_ESCR) | \ + p4_config_pack_cccr(P4_CCCR_EDGE | \ + P4_CCCR_THRESHOLD_MASK | \ + P4_CCCR_COMPLEMENT | \ + P4_CCCR_COMPARE)) + +#define P4_CONFIG_EVENT_ALIAS_IMMUTABLE_BITS \ + ((P4_CONFIG_HT) | \ + p4_config_pack_escr(P4_ESCR_T0_OS | \ + P4_ESCR_T0_USR | \ + P4_ESCR_T1_OS | \ + P4_ESCR_T1_USR) | \ + p4_config_pack_cccr(P4_CCCR_OVF | \ + P4_CCCR_CASCADE | \ + P4_CCCR_FORCE_OVF | \ + P4_CCCR_THREAD_ANY | \ + P4_CCCR_OVF_PMI_T0 | \ + P4_CCCR_OVF_PMI_T1 | \ + P4_CONFIG_ALIASABLE)) +static inline bool p4_is_event_cascaded (u64 config) {u32 cccr =p4_config_unpack_cccr (config);
arch/x86/kernel/cpu/perf_event.c +0 -7
@@ -274,7 +274,6 @@ struct x86_pmu {void (*enable_all)(int added);void (*enable)(struct perf_event *);void (*disable)(struct perf_event *); -void (*hw_watchdog_set_attr)(struct perf_event_attr *attr);int (*hw_config)(struct perf_event *event);int (*schedule_events)(struct cpu_hw_events *cpuc,int n,int *assign);unsigned eventsel;
@@ -360,12 +359,6 @@ static u64 __read_mostly hw_cache_extra_ [PERF_COUNT_HW_CACHE_OP_MAX ] [PERF_COUNT_HW_CACHE_RESULT_MAX ]; -void hw_nmi_watchdog_set_attr (struct perf_event_attr *wd_attr) -{ -if (x86_pmu.hw_watchdog_set_attr) - x86_pmu.hw_watchdog_set_attr (wd_attr); -} -/* * Propagate event elapsed time into the generic event. * Can only be executed on the CPU where the event is active.
arch/x86/kernel/cpu/perf_event_p4.c +100 -29
169 lines not on this page · raw message
kernel/watchdog.c +0 -2
@@ -200,7 +200,6 @@ static int is_softlockup(unsigned long t }#ifdef CONFIG_HARDLOCKUP_DETECTOR -void __weak hw_nmi_watchdog_set_attr (struct perf_event_attr *wd_attr) { }static struct perf_event_attr wd_hw_attr = { .type = PERF_TYPE_HARDWARE,
@@ -372,7 +371,6 @@ static int watchdog_nmi_enable(int cpu) wd_attr = &wd_hw_attr; wd_attr->sample_period =hw_nmi_get_sample_period (watchdog_thresh); -hw_nmi_watchdog_set_attr (wd_attr);/* Try to register using hardware perf events */ event =perf_event_create_kernel_counter (wd_attr, cpu,NULL , watchdog_overflow_callback,NULL );