ARM: pxa: remove redundant macro on GPIO
Subsystems (6)
A message that is not in the archive (sent off-list or not yet received): 2011092901
PATCH 1/5 ARM: pxa: remove redundant macro on GPIO
Both GPLRx and GPLR(x) are provided. GPLRx means register GPLR0/1/... GPLR(x) means register GPLR0/1/... and x ranges from 0 to the maximum bit number.
Remove GPLRx since it's redundant.
Signed-off-by Haojian Zhuang <[email protected]>
--- arch/arm/mach-pxa/corgi_pm.c | 5 ++- arch/arm/mach-pxa/include/mach/gpio.h | 60 ++++---------------------------- arch/arm/mach-pxa/irq.c | 17 +++++---- arch/arm/mach-pxa/spitz_pm.c | 3 +- 4 files changed, 22 insertions(+), 63 deletions(-)
arch/arm/mach-pxa/corgi_pm.c +3 -2
@@ -90,7 +90,7 @@ static int corgi_should_wakeup(unsigned int resume_on_alarm) {int is_resume =0 ; -dev_dbg (sharpsl_pm.dev,"GPLR0 = %x,%x\n" ,GPLR0 ,PEDR ); +dev_dbg (sharpsl_pm.dev,"GPLR0 = %x,%x\n" ,GPLR (0 ),PEDR );if ((PEDR &GPIO_bit (CORGI_GPIO_AC_IN ))) {if (sharpsl_pm.machinfo->read_devdata (SHARPSL_STATUS_ACIN )) {
@@ -124,7 +124,8 @@ static int corgi_should_wakeup(unsigned int resume_on_alarm)static unsigned long corgi_charger_wakeup (void ) { -return ~GPLR0 & (GPIO_bit (CORGI_GPIO_AC_IN ) |GPIO_bit (CORGI_GPIO_KEY_INT ) |GPIO_bit (CORGI_GPIO_WAKEUP ) ); +return ~GPLR (CORGI_GPIO_AC_IN ) & (GPIO_bit (CORGI_GPIO_AC_IN ) + |GPIO_bit (CORGI_GPIO_KEY_INT ) |GPIO_bit (CORGI_GPIO_WAKEUP ) ); }unsigned long corgipm_read_devdata (int type)
arch/arm/mach-pxa/include/mach/gpio.h +8 -52
77 lines not on this page · raw message
arch/arm/mach-pxa/irq.c +9 -8
@@ -103,21 +103,22 @@ static int pxa_set_low_gpio_type(struct irq_data *d, unsigned int type) }if (type &IRQ_TYPE_EDGE_RISING ) -GRER0 |=GPIO_bit (gpio); +GRER (gpio) |=GPIO_bit (gpio);else -GRER0 &= ~GPIO_bit (gpio); +GRER (gpio) &= ~GPIO_bit (gpio);if (type &IRQ_TYPE_EDGE_FALLING ) -GFER0 |=GPIO_bit (gpio); +GFER (gpio) |=GPIO_bit (gpio);else -GFER0 &= ~GPIO_bit (gpio); +GFER (gpio) &= ~GPIO_bit (gpio);return 0 ; }static void pxa_ack_low_gpio (struct irq_data *d) { -GEDR0 = (1 << (d->irq -IRQ_GPIO0 )); +int gpio = d->irq -IRQ_GPIO0 ; +GEDR (gpio) =1 << gpio; }static struct irq_chip pxa_low_gpio_chip = {
@@ -163,9 +164,9 @@ static void __init pxa_init_low_gpio_irq(set_wake_t fn)int irq;/* clear edge detection on GPIO 0 and 1 */ -GFER0 &= ~0x3 ; -GRER0 &= ~0x3 ; -GEDR0 =0x3 ; +GFER (0 ) &= ~0x3 ; +GRER (0 ) &= ~0x3 ; +GEDR (0 ) =0x3 ;for (irq =IRQ_GPIO0 ; irq <=IRQ_GPIO1 ; irq++) { irq_set_chip_and_handler(irq, &pxa_low_gpio_chip,
arch/arm/mach-pxa/spitz_pm.c +2 -1
@@ -169,7 +169,8 @@ static int spitz_should_wakeup(unsigned int resume_on_alarm)static unsigned long spitz_charger_wakeup (void ) { -return (~GPLR0 &GPIO_bit (SPITZ_GPIO_KEY_INT )) | (GPLR0 &GPIO_bit (SPITZ_GPIO_SYNC )); +return (~GPLR (SPITZ_GPIO_KEY_INT ) &GPIO_bit (SPITZ_GPIO_KEY_INT )) + | (GPLR (SPITZ_GPIO_SYNC ) &GPIO_bit (SPITZ_GPIO_SYNC )); }unsigned long spitzpm_read_devdata (int type)
Signature · 1 line
1.7.2.5
PATCH 1/5 ARM: pxa: remove redundant macro on GPIO
2011/9/29 Haojian Zhuang <[email protected]>:
[...]
Quoted 3 lines
? ? ? ?if (type &
IRQ_TYPE_EDGE_RISING)
- ? ? ? ? ? ? ? GRER0 |=GPIO_bit(gpio);
+ ? ? ? ? ? ? ? GRER(gpio) |=GPIO_bit(gpio);
[...]
This looks wrong. There are more occurrences like this. Can you explain if this is correct?
Best Regards,
Micha? Miros?aw
PATCH 1/5 ARM: pxa: remove redundant macro on GPIO
2011/9/30 Micha? Miros?aw <[email protected]>:
Quoted 9 lines
2011/9/29 Haojian Zhuang <[email protected]>:
[...]Quoted 3 lines
? ? ? ?if (type &
IRQ_TYPE_EDGE_RISING)
- ? ? ? ? ? ? ? GRER0 |=GPIO_bit(gpio);
+ ? ? ? ? ? ? ? GRER(gpio) |=GPIO_bit(gpio);[...]
This looks wrong. There are more occurrences like this. Can you explain if this is correct?
This is actually correct. In GRER(x) - x designates the GPIO instead of the subindex n in GRERn.
The rest of the direct references GPxRn have been mostly removed during the last several rounds of cleanup.
Haojian,
Please use
'git grep GP.R[0-9]'
and
'git grep GR.R[0-9]'
to rule out the rest references. I'm good with the patch, just to make sure there is no more such reference.
Quoted 4 lines
Best Regards,
Micha? Miros?aw
Haojian Zhuang
maintainerPATCH 1/5 ARM: pxa: remove redundant macro on GPIO
2011/9/30 Eric Miao <[email protected]>:
Quoted 21 lines
2011/9/30 Micha? Miros?aw <[email protected]>:
Quoted 9 lines
2011/9/29 Haojian Zhuang <[email protected]>:
[...]Quoted 3 lines
? ? ? ?if (type &
IRQ_TYPE_EDGE_RISING)
- ? ? ? ? ? ? ? GRER0 |=GPIO_bit(gpio);
+ ? ? ? ? ? ? ? GRER(gpio) |=GPIO_bit(gpio);[...]
This looks wrong. There are more occurrences like this. Can you explain if this is correct?
This is actually correct. In GRER(x) - x designates the GPIO instead of the subindex n in GRERn.
The rest of the direct references GPxRn have been mostly removed during the last several rounds of cleanup.
Haojian,
Please use
Quoted 9 lines
'git grep GP.R[0-9]'
and
'git grep GR.R[0-9]'
to rule out the rest references. I'm good with the patch, just to make sure there is no more such reference.
There's no reference to GP.R and GR.R registers except for comment.
PATCH 1/5 ARM: pxa: remove redundant macro on GPIO
In reply to Haojian ZhuangHey, these patches are mor thorough than what I did, making deeper changes in the driver.
Notify me when you have put the patches into Russells patch tracker so I can remove my similar patches from the tracker.
Acked-by Linus Walleij <[email protected]>
For all.
Thanks!
Linus Walleij
PATCH 1/5 ARM: pxa: remove redundant macro on GPIO
In reply to Haojian ZhuangQuoted 7 lines · Haojian Zhuang
Both GPLRx and GPLR(x) are provided. GPLRx means register GPLR0/1/... GPLR(x) means register GPLR0/1/... and x ranges from 0 to the maximum bit number.
Remove GPLRx since it's redundant.
Signed-off-by Haojian Zhuang <[email protected]>
Acked-by Grant Likely <[email protected]>
Quoted 174 lines
--- arch/arm/mach-pxa/corgi_pm.c | 5 ++- arch/arm/mach-pxa/include/mach/gpio.h | 60 ++++---------------------------- arch/arm/mach-pxa/irq.c | 17 +++++---- arch/arm/mach-pxa/spitz_pm.c | 3 +- 4 files changed, 22 insertions(+), 63 deletions(-)arch/arm/mach-pxa/corgi_pm.c +3
-2@@ -90,7 +90,7 @@ static int corgi_should_wakeup(unsigned int resume_on_alarm) {int is_resume =0 ; -dev_dbg (sharpsl_pm.dev,"GPLR0 = %x,%x\n" ,GPLR0 ,PEDR ); +dev_dbg (sharpsl_pm.dev,"GPLR0 = %x,%x\n" ,GPLR (0 ),PEDR );if ((PEDR &GPIO_bit (CORGI_GPIO_AC_IN ))) {if (sharpsl_pm.machinfo->read_devdata (SHARPSL_STATUS_ACIN )) {@@ -124,7 +124,8 @@ static int corgi_should_wakeup(unsigned int resume_on_alarm)static unsigned long corgi_charger_wakeup (void ) { -return ~GPLR0 & (GPIO_bit (CORGI_GPIO_AC_IN ) |GPIO_bit (CORGI_GPIO_KEY_INT ) |GPIO_bit (CORGI_GPIO_WAKEUP ) ); +return ~GPLR (CORGI_GPIO_AC_IN ) & (GPIO_bit (CORGI_GPIO_AC_IN ) + |GPIO_bit (CORGI_GPIO_KEY_INT ) |GPIO_bit (CORGI_GPIO_WAKEUP ) ); }unsigned long corgipm_read_devdata (int type)arch/arm/mach-pxa/include/mach/gpio.h +8
-52@@ -33,69 +33,25 @@#define BANK_OFF (n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))#define GPIO_REG (x) (*(volatile u32 *)(GPIO_REGS_VIRT + (x))) -/* GPIO Pin Level Registers */ -#define GPLR0 GPIO_REG(BANK_OFF(0) + 0x00) -#define GPLR1 GPIO_REG(BANK_OFF(1) + 0x00) -#define GPLR2 GPIO_REG(BANK_OFF(2) + 0x00) -#define GPLR3 GPIO_REG(BANK_OFF(3) + 0x00) - -/* GPIO Pin Direction Registers */ -#define GPDR0 GPIO_REG(BANK_OFF(0) + 0x0c) -#define GPDR1 GPIO_REG(BANK_OFF(1) + 0x0c) -#define GPDR2 GPIO_REG(BANK_OFF(2) + 0x0c) -#define GPDR3 GPIO_REG(BANK_OFF(3) + 0x0c) - -/* GPIO Pin Output Set Registers */ -#define GPSR0 GPIO_REG(BANK_OFF(0) + 0x18) -#define GPSR1 GPIO_REG(BANK_OFF(1) + 0x18) -#define GPSR2 GPIO_REG(BANK_OFF(2) + 0x18) -#define GPSR3 GPIO_REG(BANK_OFF(3) + 0x18) - -/* GPIO Pin Output Clear Registers */ -#define GPCR0 GPIO_REG(BANK_OFF(0) + 0x24) -#define GPCR1 GPIO_REG(BANK_OFF(1) + 0x24) -#define GPCR2 GPIO_REG(BANK_OFF(2) + 0x24) -#define GPCR3 GPIO_REG(BANK_OFF(3) + 0x24) - -/* GPIO Rising Edge Detect Registers */ -#define GRER0 GPIO_REG(BANK_OFF(0) + 0x30) -#define GRER1 GPIO_REG(BANK_OFF(1) + 0x30) -#define GRER2 GPIO_REG(BANK_OFF(2) + 0x30) -#define GRER3 GPIO_REG(BANK_OFF(3) + 0x30) - -/* GPIO Falling Edge Detect Registers */ -#define GFER0 GPIO_REG(BANK_OFF(0) + 0x3c) -#define GFER1 GPIO_REG(BANK_OFF(1) + 0x3c) -#define GFER2 GPIO_REG(BANK_OFF(2) + 0x3c) -#define GFER3 GPIO_REG(BANK_OFF(3) + 0x3c) - -/* GPIO Edge Detect Status Registers */ -#define GEDR0 GPIO_REG(BANK_OFF(0) + 0x48) -#define GEDR1 GPIO_REG(BANK_OFF(1) + 0x48) -#define GEDR2 GPIO_REG(BANK_OFF(2) + 0x48) -#define GEDR3 GPIO_REG(BANK_OFF(3) + 0x48) - -/* GPIO Alternate Function Select Registers */ -#define GAFR0_L GPIO_REG(0x0054) -#define GAFR0_U GPIO_REG(0x0058) -#define GAFR1_L GPIO_REG(0x005C) -#define GAFR1_U GPIO_REG(0x0060) -#define GAFR2_L GPIO_REG(0x0064) -#define GAFR2_U GPIO_REG(0x0068) -#define GAFR3_L GPIO_REG(0x006C) -#define GAFR3_U GPIO_REG(0x0070) -/* More handy macros. The argument is a literal GPIO number. */ #define GPIO_bit (x) (1 << ((x) & 0x1f)) +/* GPIO Pin Level Registers */ #define GPLR (x) GPIO_REG(BANK_OFF((x) >> 5) + 0x00) +/* GPIO Pin Direction Registers */ #define GPDR (x) GPIO_REG(BANK_OFF((x) >> 5) + 0x0c) +/* GPIO Pin Output Set Registers */ #define GPSR (x) GPIO_REG(BANK_OFF((x) >> 5) + 0x18) +/* GPIO Pin Output Clear Registers */ #define GPCR (x) GPIO_REG(BANK_OFF((x) >> 5) + 0x24) +/* GPIO Rising Edge Detect Registers */ #define GRER (x) GPIO_REG(BANK_OFF((x) >> 5) + 0x30) +/* GPIO Falling Edge Detect Registers */ #define GFER (x) GPIO_REG(BANK_OFF((x) >> 5) + 0x3c) +/* GPIO Edge Detect Status Registers */ #define GEDR (x) GPIO_REG(BANK_OFF((x) >> 5) + 0x48) +/* GPIO Alternate Function Select Registers */ #define GAFR (x) GPIO_REG(0x54 + (((x) & 0x70) >> 2))arch/arm/mach-pxa/irq.c +9
-8@@ -103,21 +103,22 @@ static int pxa_set_low_gpio_type(struct irq_data *d, unsigned int type) }if (type &IRQ_TYPE_EDGE_RISING ) -GRER0 |=GPIO_bit (gpio); +GRER (gpio) |=GPIO_bit (gpio);else -GRER0 &= ~GPIO_bit (gpio); +GRER (gpio) &= ~GPIO_bit (gpio);if (type &IRQ_TYPE_EDGE_FALLING ) -GFER0 |=GPIO_bit (gpio); +GFER (gpio) |=GPIO_bit (gpio);else -GFER0 &= ~GPIO_bit (gpio); +GFER (gpio) &= ~GPIO_bit (gpio);return 0 ; }static void pxa_ack_low_gpio (struct irq_data *d) { -GEDR0 = (1 << (d->irq -IRQ_GPIO0 )); +int gpio = d->irq -IRQ_GPIO0 ; +GEDR (gpio) =1 << gpio; }static struct irq_chip pxa_low_gpio_chip = {@@ -163,9 +164,9 @@ static void __init pxa_init_low_gpio_irq(set_wake_t fn)int irq;/* clear edge detection on GPIO 0 and 1 */ -GFER0 &= ~0x3 ; -GRER0 &= ~0x3 ; -GEDR0 =0x3 ; +GFER (0 ) &= ~0x3 ; +GRER (0 ) &= ~0x3 ; +GEDR (0 ) =0x3 ;for (irq =IRQ_GPIO0 ; irq <=IRQ_GPIO1 ; irq++) { irq_set_chip_and_handler(irq, &pxa_low_gpio_chip,arch/arm/mach-pxa/spitz_pm.c +2
-1@@ -169,7 +169,8 @@ static int spitz_should_wakeup(unsigned int resume_on_alarm)static unsigned long spitz_charger_wakeup (void ) { -return (~GPLR0 &GPIO_bit (SPITZ_GPIO_KEY_INT )) | (GPLR0 &GPIO_bit (SPITZ_GPIO_SYNC )); +return (~GPLR (SPITZ_GPIO_KEY_INT ) &GPIO_bit (SPITZ_GPIO_KEY_INT )) + | (GPLR (SPITZ_GPIO_SYNC ) &GPIO_bit (SPITZ_GPIO_SYNC )); }unsigned long spitzpm_read_devdata (int type)Signature · 1 line
1.7.2.5
PATCH 2/5 ARM: pxa: remove set_wake_t
In reply to a message not in the archiveSince set_wake_t is used for irq chip, it shouldn't be defined in gpio.h. Just remove it from gpio.h.
Signed-off-by Haojian Zhuang <[email protected]>
--- arch/arm/mach-pxa/irq.c | 5 +++-- arch/arm/mach-pxa/pxa3xx.c | 3 ++- arch/arm/plat-pxa/gpio.c | 3 ++- arch/arm/plat-pxa/include/plat/gpio.h | 5 ++--- 4 files changed, 9 insertions(+), 7 deletions(-)
arch/arm/mach-pxa/irq.c +3 -2
@@ -159,7 +159,8 @@ asmlinkage void __exception_irq_entry ichp_handle_irq(struct pt_regs *regs) }while (1 ); } -static void __init pxa_init_low_gpio_irq (set_wake_t fn) +static void __init pxa_init_low_gpio_irq (int (*fn)(struct irq_data *, +unsigned int )) {int irq;
@@ -178,7 +179,7 @@ static void __init pxa_init_low_gpio_irq(set_wake_t fn) pxa_low_gpio_chip.irq_set_wake = fn; } -void __init pxa_init_irq (int irq_nr,set_wake_t fn) +void __init pxa_init_irq (int irq_nr,int (*fn)(struct irq_data *,unsigned int )) {int irq, i, n;
arch/arm/mach-pxa/pxa3xx.c +2 -1
@@ -365,7 +365,8 @@ static struct irq_chip pxa_ext_wakeup_chip = { .irq_set_type = pxa_set_ext_wakeup_type, }; -static void __init pxa_init_ext_wakeup_irq (set_wake_t fn) +static void __init pxa_init_ext_wakeup_irq (int (*fn)(struct irq_data *, +unsigned int )) {int irq;
arch/arm/plat-pxa/gpio.c +2 -1
@@ -264,7 +264,8 @@ static struct irq_chip pxa_muxed_gpio_chip = { .irq_set_type = pxa_gpio_irq_type, }; -void __init pxa_init_gpio (int mux_irq,int start,int end,set_wake_t fn) +void __init pxa_init_gpio (int mux_irq,int start,int end, +int (*fn)(struct irq_data *,unsigned int )) {struct pxa_gpio_chip *c;int gpio, irq;
arch/arm/plat-pxa/include/plat/gpio.h +2 -3
@@ -60,7 +60,6 @@ static inline void gpio_set_value(unsigned gpio, int value)*/ extern int pxa_last_gpio; -typedef int (*set_wake_t )(struct irq_data *d,unsigned int on); - -extern void pxa_init_gpio (int mux_irq,int start,int end,set_wake_t fn); +extern void pxa_init_gpio (int mux_irq,int start,int end, +int (*fn)(struct irq_data *,unsigned int ));#endif /* __PLAT_GPIO_H */
Signature · 1 line
1.7.2.5
PATCH 3/5 ARM: pxa: rename gpio_to_irq and irq_to_gpio
In reply to a message not in the archiveRename gpio_to_irq() to pxa_gpio_to_irq(), and rename irq_to_gpio() to pxa_irq_to_gpio(). This rename operations is used to avoid naming confliction while gpio driver is moved into drivers/gpio/ directory.
Signed-off-by Haojian Zhuang <[email protected]>
--- arch/arm/mach-mmp/aspenite.c | 4 +- arch/arm/mach-mmp/flint.c | 4 +- arch/arm/mach-mmp/include/mach/gpio.h | 4 +- arch/arm/mach-mmp/tavorevb.c | 4 +- arch/arm/mach-mmp/teton_bga.c | 2 +- arch/arm/mach-pxa/capc7117.c | 12 ++++---- arch/arm/mach-pxa/cm-x270.c | 2 +- arch/arm/mach-pxa/cm-x2xx-pci.c | 4 +- arch/arm/mach-pxa/colibri-pxa270.c | 6 ++-- arch/arm/mach-pxa/colibri-pxa300.c | 4 +- arch/arm/mach-pxa/colibri-pxa320.c | 4 +- arch/arm/mach-pxa/corgi.c | 2 +- arch/arm/mach-pxa/em-x270.c | 6 ++-- arch/arm/mach-pxa/hx4700.c | 18 +++++++------- arch/arm/mach-pxa/icontrol.c | 8 +++--- arch/arm/mach-pxa/include/mach/csb726.h | 4 +- arch/arm/mach-pxa/include/mach/gpio.h | 4 +- arch/arm/mach-pxa/littleton.c | 2 +- arch/arm/mach-pxa/magician.c | 8 +++--- arch/arm/mach-pxa/mioa701.c | 12 ++++---- arch/arm/mach-pxa/mxm8x10.c | 4 +- arch/arm/mach-pxa/poodle.c | 2 +- arch/arm/mach-pxa/pxa25x.c | 2 +- arch/arm/mach-pxa/pxa27x.c | 2 +- arch/arm/mach-pxa/raumfeld.c | 14 +++++----- arch/arm/mach-pxa/saar.c | 6 ++-- arch/arm/mach-pxa/saarb.c | 2 +- arch/arm/mach-pxa/spitz.c | 2 +- arch/arm/mach-pxa/stargate2.c | 4 +- arch/arm/mach-pxa/tavorevb.c | 4 +- arch/arm/mach-pxa/tavorevb3.c | 2 +- arch/arm/mach-pxa/tosa.c | 4 +- arch/arm/mach-pxa/viper.c | 16 ++++++------ arch/arm/mach-pxa/vpac270.c | 4 +- arch/arm/mach-pxa/z2.c | 2 +- arch/arm/mach-pxa/zeus.c | 40 +++++++++++++++++------------- arch/arm/mach-pxa/zylonite.c | 4 +- arch/arm/plat-pxa/gpio.c | 13 +++++---- 38 files changed, 124 insertions(+), 117 deletions(-)
arch/arm/mach-mmp/aspenite.c +2 -2
@@ -119,8 +119,8 @@ static struct resource smc91x_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gpio_to_irq(27), - .end = gpio_to_irq(27), + .start = pxa_gpio_to_irq(27), + .end = pxa_gpio_to_irq(27), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, } };
arch/arm/mach-mmp/flint.c +2 -2
@@ -87,8 +87,8 @@ static struct resource smc91x_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gpio_to_irq(155), - .end = gpio_to_irq(155), + .start = pxa_gpio_to_irq(155), + .end = pxa_gpio_to_irq(155), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, } };
arch/arm/mach-mmp/include/mach/gpio.h +2 -2
@@ -13,8 +13,8 @@#define NR_BUILTIN_GPIO IRQ_GPIO_NUM#define gpio_to_bank (gpio) ((gpio) >> 5) -#define gpio_to_irq (gpio) (IRQ_GPIO_START + (gpio)) -#define irq_to_gpio (irq) ((irq) - IRQ_GPIO_START) +#define pxa_gpio_to_irq (gpio) (IRQ_GPIO_START + (gpio)) +#define pxa_irq_to_gpio (irq) ((irq) - IRQ_GPIO_START)#define __gpio_is_inverted (gpio) (0)
arch/arm/mach-mmp/tavorevb.c +2 -2
@@ -70,8 +70,8 @@ static struct resource smc91x_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gpio_to_irq(80), - .end = gpio_to_irq(80), + .start = pxa_gpio_to_irq(80), + .end = pxa_gpio_to_irq(80), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, } };
arch/arm/mach-mmp/teton_bga.c +1 -1
@@ -66,7 +66,7 @@ static struct pxa27x_keypad_platform_data teton_bga_keypad_info __initdata = {static struct i2c_board_info teton_bga_i2c_info[]__initdata = { {I2C_BOARD_INFO ("ds1337" ,0x68 ), - .irq =gpio_to_irq (RTC_INT_GPIO ) + .irq =pxa_gpio_to_irq (RTC_INT_GPIO ) }, };
arch/arm/mach-pxa/capc7117.c +6 -6
@@ -50,8 +50,8 @@ static struct resource capc7117_ide_resources[] = { .flags = IORESOURCE_MEM }, [2] = { - .start = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO76)), - .end = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO76)), + .start = pxa_gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO76)), + .end = pxa_gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO76)), .flags = IORESOURCE_IRQ | IRQF_TRIGGER_RISING } };
@@ -80,7 +80,7 @@ static void __init capc7117_ide_init(void)static struct plat_serial8250_port ti16c752_platform_data[] = { [0 ] = { .mapbase =0x14000000 , - .irq =gpio_to_irq (mfp_to_gpio (MFP_PIN_GPIO78 )), + .irq =pxa_gpio_to_irq (mfp_to_gpio (MFP_PIN_GPIO78 )), .irqflags =IRQF_TRIGGER_RISING , .flags =TI16C752_FLAGS , .iotype =UPIO_MEM ,
@@ -89,7 +89,7 @@ static struct plat_serial8250_port ti16c752_platform_data[] = { }, [1] = { .mapbase = 0x14000040, - .irq = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO79)), + .irq = pxa_gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO79)), .irqflags = IRQF_TRIGGER_RISING, .flags = TI16C752_FLAGS, .iotype = UPIO_MEM,
@@ -98,7 +98,7 @@ static struct plat_serial8250_port ti16c752_platform_data[] = { }, [2] = { .mapbase = 0x14000080, - .irq = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO80)), + .irq = pxa_gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO80)), .irqflags = IRQF_TRIGGER_RISING, .flags = TI16C752_FLAGS, .iotype = UPIO_MEM,
@@ -107,7 +107,7 @@ static struct plat_serial8250_port ti16c752_platform_data[] = { }, [3] = { .mapbase = 0x140000c0, - .irq = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO81)), + .irq = pxa_gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO81)), .irqflags = IRQF_TRIGGER_RISING, .flags = TI16C752_FLAGS, .iotype = UPIO_MEM,
arch/arm/mach-pxa/cm-x270.c +1 -1
@@ -380,7 +380,7 @@ static struct spi_board_info cm_x270_spi_devices[] __initdata = { .modalias = "libertas_spi", .max_speed_hz = 13000000, .bus_num = 2, - .irq = gpio_to_irq(95), + .irq = pxa_gpio_to_irq(95), .chip_select = 0, .controller_data = &cm_x270_libertas_chip, .platform_data = &cm_x270_libertas_pdata,
arch/arm/mach-pxa/cm-x2xx-pci.c +2 -2
@@ -43,9 +43,9 @@ void __cmx2xx_pci_init_irq(int irq_gpio) cmx2xx_it8152_irq_gpio = irq_gpio; -irq_set_irq_type (gpio_to_irq (irq_gpio),IRQ_TYPE_EDGE_RISING ); +irq_set_irq_type (pxa_gpio_to_irq (irq_gpio),IRQ_TYPE_EDGE_RISING ); -irq_set_chained_handler (gpio_to_irq (irq_gpio), +irq_set_chained_handler (pxa_gpio_to_irq (irq_gpio), cmx2xx_it8152_irq_demux); }
arch/arm/mach-pxa/colibri-pxa270.c +3 -3
@@ -217,8 +217,8 @@ static struct resource colibri_pxa270_dm9000_resources[] = { .flags = IORESOURCE_MEM, }, { - .start = gpio_to_irq(GPIO114_COLIBRI_PXA270_ETH_IRQ), - .end = gpio_to_irq(GPIO114_COLIBRI_PXA270_ETH_IRQ), + .start = pxa_gpio_to_irq(GPIO114_COLIBRI_PXA270_ETH_IRQ), + .end = pxa_gpio_to_irq(GPIO114_COLIBRI_PXA270_ETH_IRQ), .flags = IORESOURCE_IRQ | IRQF_TRIGGER_RISING, }, };
@@ -248,7 +248,7 @@ static pxa2xx_audio_ops_t colibri_pxa270_ac97_pdata = { };static struct ucb1400_pdata colibri_pxa270_ucb1400_pdata = { - .irq =gpio_to_irq (GPIO113_COLIBRI_PXA270_TS_IRQ ), + .irq =pxa_gpio_to_irq (GPIO113_COLIBRI_PXA270_TS_IRQ ), };static struct platform_device colibri_pxa270_ucb1400_device = {
arch/arm/mach-pxa/colibri-pxa300.c +2 -2
@@ -78,8 +78,8 @@ static struct resource colibri_asix_resource[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gpio_to_irq(COLIBRI_ETH_IRQ_GPIO), - .end = gpio_to_irq(COLIBRI_ETH_IRQ_GPIO), + .start = pxa_gpio_to_irq(COLIBRI_ETH_IRQ_GPIO), + .end = pxa_gpio_to_irq(COLIBRI_ETH_IRQ_GPIO), .flags = IORESOURCE_IRQ | IRQF_TRIGGER_FALLING, } };
arch/arm/mach-pxa/colibri-pxa320.c +2 -2
@@ -115,8 +115,8 @@ static struct resource colibri_asix_resource[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gpio_to_irq(COLIBRI_ETH_IRQ_GPIO), - .end = gpio_to_irq(COLIBRI_ETH_IRQ_GPIO), + .start = pxa_gpio_to_irq(COLIBRI_ETH_IRQ_GPIO), + .end = pxa_gpio_to_irq(COLIBRI_ETH_IRQ_GPIO), .flags = IORESOURCE_IRQ | IRQF_TRIGGER_FALLING, } };
arch/arm/mach-pxa/corgi.c +1 -1
@@ -531,7 +531,7 @@ static struct spi_board_info corgi_spi_devices[] = { .chip_select = 0, .platform_data = &corgi_ads7846_info, .controller_data= &corgi_ads7846_chip, - .irq = gpio_to_irq(CORGI_GPIO_TP_INT), + .irq = pxa_gpio_to_irq(CORGI_GPIO_TP_INT), }, { .modalias = "corgi-lcd", .max_speed_hz = 50000,
arch/arm/mach-pxa/em-x270.c +3 -3
@@ -558,7 +558,7 @@ static int em_x270_mci_init(struct device *dev,return PTR_ERR (em_x270_sdio_ldo); } - err =request_irq (gpio_to_irq (mmc_cd), em_x270_detect_int, + err =request_irq (pxa_gpio_to_irq (mmc_cd), em_x270_detect_int,IRQF_DISABLED |IRQF_TRIGGER_RISING |IRQF_TRIGGER_FALLING ,"MMC card detect" , data);
@@ -588,7 +588,7 @@ static int em_x270_mci_init(struct device *dev,return 0 ; err_gpio_wp: -free_irq (gpio_to_irq (mmc_cd), data); +free_irq (pxa_gpio_to_irq (mmc_cd), data); err_irq:regulator_put (em_x270_sdio_ldo);
@@ -611,7 +611,7 @@ static void em_x270_mci_setpower(struct device *dev, unsigned int vdd)static void em_x270_mci_exit (struct device *dev,void *data) { -free_irq (gpio_to_irq (mmc_cd), data); +free_irq (pxa_gpio_to_irq (mmc_cd), data);regulator_put (em_x270_sdio_ldo);if (machine_is_em_x270 ())
arch/arm/mach-pxa/hx4700.c +9 -9
@@ -252,8 +252,8 @@ static struct resource asic3_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gpio_to_irq(GPIO12_HX4700_ASIC3_IRQ), - .end = gpio_to_irq(GPIO12_HX4700_ASIC3_IRQ), + .start = pxa_gpio_to_irq(GPIO12_HX4700_ASIC3_IRQ), + .end = pxa_gpio_to_irq(GPIO12_HX4700_ASIC3_IRQ), .flags = IORESOURCE_IRQ, },/* SD part */
@@ -263,8 +263,8 @@ static struct resource asic3_resources[] = { .flags = IORESOURCE_MEM, }, [3] = { - .start = gpio_to_irq(GPIO66_HX4700_ASIC3_nSDIO_IRQ), - .end = gpio_to_irq(GPIO66_HX4700_ASIC3_nSDIO_IRQ), + .start = pxa_gpio_to_irq(GPIO66_HX4700_ASIC3_nSDIO_IRQ), + .end = pxa_gpio_to_irq(GPIO66_HX4700_ASIC3_nSDIO_IRQ), .flags = IORESOURCE_IRQ, }, };
@@ -587,7 +587,7 @@ static struct spi_board_info tsc2046_board_info[] __initdata = { .modalias = "ads7846", .bus_num = 2, .max_speed_hz = 2600000, /* 100 kHz sample rate */ - .irq = gpio_to_irq(GPIO58_HX4700_TSC2046_nPENIRQ), + .irq = pxa_gpio_to_irq(GPIO58_HX4700_TSC2046_nPENIRQ), .platform_data = &tsc2046_info, .controller_data = &tsc2046_chip, },
@@ -635,15 +635,15 @@ static struct resource power_supply_resources[] = { .name = "ac", .flags =IORESOURCE_IRQ |IORESOURCE_IRQ_HIGHEDGE | IORESOURCE_IRQ_LOWEDGE, - .start = gpio_to_irq(GPIOD9_nAC_IN), - .end = gpio_to_irq(GPIOD9_nAC_IN), + .start = pxa_gpio_to_irq(GPIOD9_nAC_IN), + .end = pxa_gpio_to_irq(GPIOD9_nAC_IN), }, [1] = { .name = "usb", .flags =IORESOURCE_IRQ |IORESOURCE_IRQ_HIGHEDGE | IORESOURCE_IRQ_LOWEDGE, - .start = gpio_to_irq(GPIOD14_nUSBC_DETECT), - .end = gpio_to_irq(GPIOD14_nUSBC_DETECT), + .start = pxa_gpio_to_irq(GPIOD14_nUSBC_DETECT), + .end = pxa_gpio_to_irq(GPIOD14_nUSBC_DETECT), }, };
arch/arm/mach-pxa/icontrol.c +4 -4
@@ -86,7 +86,7 @@ static struct spi_board_info mcp251x_board_info[] = { .chip_select = 0, .platform_data = &mcp251x_info, .controller_data = &mcp251x_chip_info1, - .irq =gpio_to_irq (ICONTROL_MCP251x_nIRQ1) + .irq =pxa_gpio_to_irq (ICONTROL_MCP251x_nIRQ1) }, { .modalias = "mcp2515",
@@ -95,7 +95,7 @@ static struct spi_board_info mcp251x_board_info[] = { .chip_select = 1, .platform_data = &mcp251x_info, .controller_data = &mcp251x_chip_info2, - .irq =gpio_to_irq (ICONTROL_MCP251x_nIRQ2) + .irq =pxa_gpio_to_irq (ICONTROL_MCP251x_nIRQ2) }, { .modalias = "mcp2515",
@@ -104,7 +104,7 @@ static struct spi_board_info mcp251x_board_info[] = { .chip_select = 0, .platform_data = &mcp251x_info, .controller_data = &mcp251x_chip_info3, - .irq =gpio_to_irq (ICONTROL_MCP251x_nIRQ3) + .irq =pxa_gpio_to_irq (ICONTROL_MCP251x_nIRQ3) }, { .modalias = "mcp2515",
@@ -113,7 +113,7 @@ static struct spi_board_info mcp251x_board_info[] = { .chip_select = 1, .platform_data = &mcp251x_info, .controller_data = &mcp251x_chip_info4, - .irq = gpio_to_irq(ICONTROL_MCP251x_nIRQ4) + .irq = pxa_gpio_to_irq(ICONTROL_MCP251x_nIRQ4) } };
arch/arm/mach-pxa/include/mach/csb726.h +2 -2
@@ -19,8 +19,8 @@#define CSB726_FLASH_SIZE (64 * 1024 * 1024)#define CSB726_FLASH_uMON (8 * 1024 * 1024) -#define CSB726_IRQ_LAN gpio_to_irq(CSB726_GPIO_IRQ_LAN) -#define CSB726_IRQ_SM501 gpio_to_irq(CSB726_GPIO_IRQ_SM501) +#define CSB726_IRQ_LAN pxa_gpio_to_irq(CSB726_GPIO_IRQ_LAN) +#define CSB726_IRQ_SM501 pxa_gpio_to_irq(CSB726_GPIO_IRQ_SM501)#endif
arch/arm/mach-pxa/include/mach/gpio.h +2 -2
@@ -58,9 +58,9 @@#define NR_BUILTIN_GPIO PXA_GPIO_IRQ_NUM#define gpio_to_bank (gpio) ((gpio) >> 5) -#define gpio_to_irq (gpio) IRQ_GPIO(gpio) +#define pxa_gpio_to_irq (gpio) IRQ_GPIO(gpio) -static inline int irq_to_gpio (unsigned int irq) +static inline int pxa_irq_to_gpio (unsigned int irq) {int gpio;
arch/arm/mach-pxa/littleton.c +1 -1
@@ -396,7 +396,7 @@ static struct i2c_board_info littleton_i2c_info[] = { .type = "da9034", .addr = 0x34, .platform_data = &littleton_da9034_info, - .irq = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO18)), + .irq = pxa_gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO18)), }, [1] = { .type = "max7320",
arch/arm/mach-pxa/magician.c +4 -4
@@ -184,8 +184,8 @@ static struct resource egpio_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gpio_to_irq(GPIO13_MAGICIAN_CPLD_IRQ), - .end = gpio_to_irq(GPIO13_MAGICIAN_CPLD_IRQ), + .start = pxa_gpio_to_irq(GPIO13_MAGICIAN_CPLD_IRQ), + .end = pxa_gpio_to_irq(GPIO13_MAGICIAN_CPLD_IRQ), .flags = IORESOURCE_IRQ, }, };
@@ -468,8 +468,8 @@ static struct resource pasic3_resources[] = { },/* No IRQ handler in the PASIC3, DS1WM needs an external IRQ */ [1 ] = { - .start =gpio_to_irq (GPIO107_MAGICIAN_DS1WM_IRQ ), - .end =gpio_to_irq (GPIO107_MAGICIAN_DS1WM_IRQ ), + .start =pxa_gpio_to_irq (GPIO107_MAGICIAN_DS1WM_IRQ ), + .end =pxa_gpio_to_irq (GPIO107_MAGICIAN_DS1WM_IRQ ), .flags =IORESOURCE_IRQ |IORESOURCE_IRQ_HIGHEDGE , } };
arch/arm/mach-pxa/mioa701.c +6 -6
@@ -314,7 +314,7 @@ static int __init gsm_init(void) rc =gpio_request_array (ARRAY_AND_SIZE (gsm_gpios));if (rc) goto err_gpio; - rc =request_irq (gpio_to_irq (GPIO25_GSM_MOD_ON_STATE ), gsm_on_irq, + rc =request_irq (pxa_gpio_to_irq (GPIO25_GSM_MOD_ON_STATE ), gsm_on_irq,IRQF_TRIGGER_RISING |IRQF_TRIGGER_FALLING ,"GSM XS200 Power Irq" ,NULL );if (rc)
@@ -333,7 +333,7 @@ err_gpio:static void gsm_exit (void ) { -free_irq (gpio_to_irq (GPIO25_GSM_MOD_ON_STATE ),NULL ); +free_irq (pxa_gpio_to_irq (GPIO25_GSM_MOD_ON_STATE ),NULL );gpio_free_array (ARRAY_AND_SIZE (gsm_gpios)); }
@@ -541,15 +541,15 @@ static struct pda_power_pdata power_pdata = {static struct resource power_resources[] = { [0 ] = { .name ="ac" , - .start =gpio_to_irq (GPIO96_AC_DETECT ), - .end =gpio_to_irq (GPIO96_AC_DETECT ), + .start =pxa_gpio_to_irq (GPIO96_AC_DETECT ), + .end =pxa_gpio_to_irq (GPIO96_AC_DETECT ), .flags =IORESOURCE_IRQ |IORESOURCE_IRQ_HIGHEDGE |IORESOURCE_IRQ_LOWEDGE , }, [1 ] = { .name ="usb" , - .start =gpio_to_irq (GPIO13_nUSB_DETECT), - .end =gpio_to_irq (GPIO13_nUSB_DETECT), + .start =pxa_gpio_to_irq (GPIO13_nUSB_DETECT), + .end =pxa_gpio_to_irq (GPIO13_nUSB_DETECT), .flags =IORESOURCE_IRQ |IORESOURCE_IRQ_HIGHEDGE |IORESOURCE_IRQ_LOWEDGE , },
arch/arm/mach-pxa/mxm8x10.c +2 -2
@@ -417,8 +417,8 @@ static struct resource dm9k_resources[] = { .flags = IORESOURCE_MEM }, [2] = { - .start = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO9)), - .end = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO9)), + .start = pxa_gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO9)), + .end = pxa_gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO9)), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE } };
arch/arm/mach-pxa/poodle.c +1 -1
@@ -212,7 +212,7 @@ static struct spi_board_info poodle_spi_devices[] = { .bus_num = 1, .platform_data = &poodle_ads7846_info, .controller_data= &poodle_ads7846_chip, - .irq = gpio_to_irq(POODLE_GPIO_TP_INT), + .irq = pxa_gpio_to_irq(POODLE_GPIO_TP_INT), }, };
arch/arm/mach-pxa/pxa25x.c +1 -1
@@ -286,7 +286,7 @@ static inline void pxa25x_init_pm(void) {}static int pxa25x_set_wake (struct irq_data *d,unsigned int on) { -int gpio =irq_to_gpio (d->irq); +int gpio =pxa_irq_to_gpio (d->irq);uint32_t mask =0 ;if (gpio >=0 && gpio <85 )
arch/arm/mach-pxa/pxa27x.c +1 -1
@@ -354,7 +354,7 @@ static inline void pxa27x_init_pm(void) {}*/ static int pxa27x_set_wake (struct irq_data *d,unsigned int on) { -int gpio =irq_to_gpio (d->irq); +int gpio =pxa_irq_to_gpio (d->irq);uint32_t mask;if (gpio >=0 && gpio <128 )
arch/arm/mach-pxa/raumfeld.c +7 -7
@@ -292,8 +292,8 @@ static struct resource smc91x_resources[] = { .flags = IORESOURCE_MEM, }, { - .start = gpio_to_irq(GPIO_ETH_IRQ), - .end = gpio_to_irq(GPIO_ETH_IRQ), + .start = pxa_gpio_to_irq(GPIO_ETH_IRQ), + .end = pxa_gpio_to_irq(GPIO_ETH_IRQ), .flags = IORESOURCE_IRQ | IRQF_TRIGGER_FALLING, } };
@@ -672,7 +672,7 @@ static struct lis3lv02d_platform_data lis3_pdata = { .chip_select = 1, \ .controller_data = (void *) GPIO_ACCEL_CS, \ .platform_data = &lis3_pdata, \ - .irq = gpio_to_irq(GPIO_ACCEL_IRQ), \ + .irq = pxa_gpio_to_irq(GPIO_ACCEL_IRQ), \ }#define SPI_DAC7512 \
@@ -824,10 +824,10 @@ static void __init raumfeld_power_init(void)else gpio_direction_output (GPIO_CHARGE_USB_SUSP ,0 ); - power_supply_resources[0 ].start =gpio_to_irq (GPIO_CHARGE_DC_OK ); - power_supply_resources[0 ].end =gpio_to_irq (GPIO_CHARGE_DC_OK ); + power_supply_resources[0 ].start =pxa_gpio_to_irq (GPIO_CHARGE_DC_OK ); + power_supply_resources[0 ].end =pxa_gpio_to_irq (GPIO_CHARGE_DC_OK ); - ret =request_irq (gpio_to_irq (GPIO_CHARGE_DONE ), + ret =request_irq (pxa_gpio_to_irq (GPIO_CHARGE_DONE ), &charge_done_irq,IORESOURCE_IRQ_LOWEDGE ,"charge_done" ,NULL );
@@ -956,7 +956,7 @@ static struct eeti_ts_platform_data eeti_ts_pdata = {static struct i2c_board_info raumfeld_controller_i2c_board_info__initdata = { .type ="eeti_ts" , .addr =0x0a , - .irq =gpio_to_irq (GPIO_TOUCH_IRQ ), + .irq =pxa_gpio_to_irq (GPIO_TOUCH_IRQ ), .platform_data = &eeti_ts_pdata, };
arch/arm/mach-pxa/saar.c +3 -3
@@ -96,8 +96,8 @@ static struct resource smc91x_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO97)), - .end = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO97)), + .start = pxa_gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO97)), + .end = pxa_gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO97)), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, } };
@@ -502,7 +502,7 @@ static struct i2c_board_info saar_i2c_info[] = { .type = "da9034", .addr = 0x34, .platform_data = &saar_da9034_info, - .irq = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO83)), + .irq = pxa_gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO83)), }, };
arch/arm/mach-pxa/saarb.c +1 -1
@@ -90,7 +90,7 @@ static struct i2c_board_info saarb_i2c_info[] = { .type = "88PM860x", .addr = 0x34, .platform_data = &saarb_pm8607_info, - .irq = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO83)), + .irq = pxa_gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO83)), }, };
arch/arm/mach-pxa/spitz.c +1 -1
@@ -552,7 +552,7 @@ static struct spi_board_info spitz_spi_devices[] = { .chip_select = 0, .platform_data = &spitz_ads7846_info, .controller_data = &spitz_ads7846_chip, - .irq = gpio_to_irq(SPITZ_GPIO_TP_INT), + .irq = pxa_gpio_to_irq(SPITZ_GPIO_TP_INT), }, { .modalias = "corgi-lcd", .max_speed_hz = 50000,
arch/arm/mach-pxa/stargate2.c +2 -2
@@ -546,7 +546,7 @@ static struct i2c_board_info __initdata imote2_pwr_i2c_board_info[] = { .type = "da9030", .addr = 0x49, .platform_data = &imote2_da9030_pdata, - .irq = gpio_to_irq(1), + .irq = pxa_gpio_to_irq(1), }, };
@@ -913,7 +913,7 @@ static struct i2c_board_info __initdata stargate2_pwr_i2c_board_info[] = { .type = "da9030", .addr = 0x49, .platform_data = &stargate2_da9030_pdata, - .irq = gpio_to_irq(1), + .irq = pxa_gpio_to_irq(1), }, };
arch/arm/mach-pxa/tavorevb.c +2 -2
@@ -85,8 +85,8 @@ static struct resource smc91x_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO47)), - .end = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO47)), + .start = pxa_gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO47)), + .end = pxa_gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO47)), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, } };
arch/arm/mach-pxa/tavorevb3.c +1 -1
@@ -101,7 +101,7 @@ static struct i2c_board_info evb3_i2c_info[] = { .type = "88PM860x", .addr = 0x34, .platform_data = &evb3_pm8607_info, - .irq = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO83)), + .irq = pxa_gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO83)), }, };
arch/arm/mach-pxa/tosa.c +2 -2
@@ -404,8 +404,8 @@ static struct pda_power_pdata tosa_power_data = {static struct resource tosa_power_resource[] = { { .name ="ac" , - .start =gpio_to_irq (TOSA_GPIO_AC_IN ), - .end =gpio_to_irq (TOSA_GPIO_AC_IN ), + .start =pxa_gpio_to_irq (TOSA_GPIO_AC_IN ), + .end =pxa_gpio_to_irq (TOSA_GPIO_AC_IN ), .flags =IORESOURCE_IRQ |IORESOURCE_IRQ_HIGHEDGE |IORESOURCE_IRQ_LOWEDGE ,
arch/arm/mach-pxa/viper.c +8 -8
@@ -315,9 +315,9 @@ static void __init viper_init_irq(void)set_irq_flags (isa_irq,IRQF_VALID |IRQF_PROBE ); } -irq_set_chained_handler (gpio_to_irq (VIPER_CPLD_GPIO ), +irq_set_chained_handler (pxa_gpio_to_irq (VIPER_CPLD_GPIO ), viper_irq_handler); -irq_set_irq_type (gpio_to_irq (VIPER_CPLD_GPIO ),IRQ_TYPE_EDGE_BOTH ); +irq_set_irq_type (pxa_gpio_to_irq (VIPER_CPLD_GPIO ),IRQ_TYPE_EDGE_BOTH ); }/* Flat Panel */
@@ -422,8 +422,8 @@ static struct resource smc91x_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gpio_to_irq(VIPER_ETH_GPIO), - .end = gpio_to_irq(VIPER_ETH_GPIO), + .start = pxa_gpio_to_irq(VIPER_ETH_GPIO), + .end = pxa_gpio_to_irq(VIPER_ETH_GPIO), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, }, [2] = {
@@ -546,7 +546,7 @@ static struct plat_serial8250_port serial_platform_data[] = {/* External UARTs */ { .mapbase = VIPER_UARTA_PHYS, - .irq = gpio_to_irq(VIPER_UARTA_GPIO), + .irq = pxa_gpio_to_irq(VIPER_UARTA_GPIO), .irqflags = IRQF_TRIGGER_RISING, .uartclk = 1843200, .regshift = 1,
@@ -556,7 +556,7 @@ static struct plat_serial8250_port serial_platform_data[] = { }, { .mapbase = VIPER_UARTB_PHYS, - .irq = gpio_to_irq(VIPER_UARTB_GPIO), + .irq = pxa_gpio_to_irq(VIPER_UARTB_GPIO), .irqflags = IRQF_TRIGGER_RISING, .uartclk = 1843200, .regshift = 1,
@@ -596,8 +596,8 @@ static struct resource isp116x_resources[] = { .flags = IORESOURCE_MEM, }, [2] = { - .start = gpio_to_irq(VIPER_USB_GPIO), - .end = gpio_to_irq(VIPER_USB_GPIO), + .start = pxa_gpio_to_irq(VIPER_USB_GPIO), + .end = pxa_gpio_to_irq(VIPER_USB_GPIO), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, }, };
arch/arm/mach-pxa/vpac270.c +2 -2
@@ -610,8 +610,8 @@ static struct resource vpac270_ide_resources[] = { .flags = IORESOURCE_DMA }, [3] = { /* IDE IRQ pin */ - .start = gpio_to_irq(GPIO36_VPAC270_IDE_IRQ), - .end = gpio_to_irq(GPIO36_VPAC270_IDE_IRQ), + .start = pxa_gpio_to_irq(GPIO36_VPAC270_IDE_IRQ), + .end = pxa_gpio_to_irq(GPIO36_VPAC270_IDE_IRQ), .flags = IORESOURCE_IRQ } };
arch/arm/mach-pxa/z2.c +1 -1
@@ -573,7 +573,7 @@ static struct spi_board_info spi_board_info[] __initdata = { .modalias = "libertas_spi", .platform_data = &z2_lbs_pdata, .controller_data = &z2_lbs_chip_info, - .irq = gpio_to_irq(GPIO36_ZIPITZ2_WIFI_IRQ), + .irq = pxa_gpio_to_irq(GPIO36_ZIPITZ2_WIFI_IRQ), .max_speed_hz = 13000000, .bus_num = 1, .chip_select = 0,
arch/arm/mach-pxa/zeus.c +23 -17
@@ -136,12 +136,16 @@ static void __init zeus_init_irq(void)/* Peripheral IRQs. It would be nice to move those inside driver configuration, but it is not supported@the moment. */ -irq_set_irq_type (gpio_to_irq (ZEUS_AC97_GPIO ),IRQ_TYPE_EDGE_RISING ); -irq_set_irq_type (gpio_to_irq (ZEUS_WAKEUP_GPIO ),IRQ_TYPE_EDGE_RISING ); -irq_set_irq_type (gpio_to_irq (ZEUS_PTT_GPIO ),IRQ_TYPE_EDGE_RISING ); -irq_set_irq_type (gpio_to_irq (ZEUS_EXTGPIO_GPIO ), +irq_set_irq_type (pxa_gpio_to_irq (ZEUS_AC97_GPIO ), +IRQ_TYPE_EDGE_RISING ); +irq_set_irq_type (pxa_gpio_to_irq (ZEUS_WAKEUP_GPIO ), +IRQ_TYPE_EDGE_RISING ); +irq_set_irq_type (pxa_gpio_to_irq (ZEUS_PTT_GPIO ), +IRQ_TYPE_EDGE_RISING ); +irq_set_irq_type (pxa_gpio_to_irq (ZEUS_EXTGPIO_GPIO ), +IRQ_TYPE_EDGE_FALLING ); +irq_set_irq_type (pxa_gpio_to_irq (ZEUS_CAN_GPIO ),IRQ_TYPE_EDGE_FALLING ); -irq_set_irq_type (gpio_to_irq (ZEUS_CAN_GPIO ),IRQ_TYPE_EDGE_FALLING );/* Setup ISA IRQs */ for (level =0 ; level <ARRAY_SIZE (zeus_isa_irqs); level++) {
@@ -151,8 +155,10 @@ static void __init zeus_init_irq(void)set_irq_flags (isa_irq,IRQF_VALID |IRQF_PROBE ); } -irq_set_irq_type (gpio_to_irq (ZEUS_ISA_GPIO ),IRQ_TYPE_EDGE_RISING ); -irq_set_chained_handler (gpio_to_irq (ZEUS_ISA_GPIO ), zeus_irq_handler); +irq_set_irq_type (pxa_gpio_to_irq (ZEUS_ISA_GPIO ), +IRQ_TYPE_EDGE_RISING ); +irq_set_chained_handler (pxa_gpio_to_irq (ZEUS_ISA_GPIO ), + zeus_irq_handler); }
@@ -233,7 +239,7 @@ static struct plat_serial8250_port serial_platform_data[] = {/* FIXME: Shared IRQs on COM1-COM4 will not work properly on v1i1 hardware. */ {/* COM1 */ .mapbase = 0x10000000, - .irq = gpio_to_irq(ZEUS_UARTA_GPIO), + .irq = pxa_gpio_to_irq(ZEUS_UARTA_GPIO), .irqflags = IRQF_TRIGGER_RISING, .uartclk = 14745600, .regshift = 1,
@@ -242,7 +248,7 @@ static struct plat_serial8250_port serial_platform_data[] = { }, {/* COM2 */ .mapbase = 0x10800000, - .irq = gpio_to_irq(ZEUS_UARTB_GPIO), + .irq = pxa_gpio_to_irq(ZEUS_UARTB_GPIO), .irqflags = IRQF_TRIGGER_RISING, .uartclk = 14745600, .regshift = 1,
@@ -251,7 +257,7 @@ static struct plat_serial8250_port serial_platform_data[] = { }, {/* COM3 */ .mapbase = 0x11000000, - .irq = gpio_to_irq(ZEUS_UARTC_GPIO), + .irq = pxa_gpio_to_irq(ZEUS_UARTC_GPIO), .irqflags = IRQF_TRIGGER_RISING, .uartclk = 14745600, .regshift = 1,
@@ -260,7 +266,7 @@ static struct plat_serial8250_port serial_platform_data[] = { }, {/* COM4 */ .mapbase = 0x11800000, - .irq = gpio_to_irq(ZEUS_UARTD_GPIO), + .irq = pxa_gpio_to_irq(ZEUS_UARTD_GPIO), .irqflags = IRQF_TRIGGER_RISING, .uartclk = 14745600, .regshift = 1,
@@ -321,8 +327,8 @@ static struct resource zeus_dm9k0_resource[] = { .flags = IORESOURCE_MEM }, [2] = { - .start = gpio_to_irq(ZEUS_ETH0_GPIO), - .end = gpio_to_irq(ZEUS_ETH0_GPIO), + .start = pxa_gpio_to_irq(ZEUS_ETH0_GPIO), + .end = pxa_gpio_to_irq(ZEUS_ETH0_GPIO), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, }, };
@@ -339,8 +345,8 @@ static struct resource zeus_dm9k1_resource[] = { .flags = IORESOURCE_MEM, }, [2] = { - .start = gpio_to_irq(ZEUS_ETH1_GPIO), - .end = gpio_to_irq(ZEUS_ETH1_GPIO), + .start = pxa_gpio_to_irq(ZEUS_ETH1_GPIO), + .end = pxa_gpio_to_irq(ZEUS_ETH1_GPIO), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, }, };
@@ -423,7 +429,7 @@ static struct spi_board_info zeus_spi_board_info[] = { [0] = { .modalias = "mcp2515", .platform_data = &zeus_mcp2515_pdata, - .irq = gpio_to_irq(ZEUS_CAN_GPIO), + .irq = pxa_gpio_to_irq(ZEUS_CAN_GPIO), .max_speed_hz = 1*1000*1000, .bus_num = 3, .mode = SPI_MODE_0,
@@ -753,7 +759,7 @@ static struct i2c_board_info __initdata zeus_i2c_devices[] = { { I2C_BOARD_INFO("pca9535", 0x20), .platform_data = &zeus_pca953x_pdata[2], - .irq =gpio_to_irq (ZEUS_EXTGPIO_GPIO ), + .irq =pxa_gpio_to_irq (ZEUS_EXTGPIO_GPIO ), }, { I2C_BOARD_INFO("lm75a", 0x48) }, { I2C_BOARD_INFO("24c01", 0x50) },
arch/arm/mach-pxa/zylonite.c +2 -2
@@ -408,8 +408,8 @@ static void __init zylonite_init(void)* Note: We depend that the bootloader set * the correct value to MSC register for SMC91x. */ - smc91x_resources[1 ].start =gpio_to_irq (gpio_eth_irq); - smc91x_resources[1 ].end =gpio_to_irq (gpio_eth_irq); + smc91x_resources[1 ].start =pxa_gpio_to_irq (gpio_eth_irq); + smc91x_resources[1 ].end =pxa_gpio_to_irq (gpio_eth_irq);platform_device_register (&smc91x_device);pxa_set_ac97_info (NULL );
arch/arm/plat-pxa/gpio.c +7 -6
@@ -156,7 +156,7 @@ static inline void update_edge_detect(struct pxa_gpio_chip *c)static int pxa_gpio_irq_type (struct irq_data *d,unsigned int type) {struct pxa_gpio_chip *c; -int gpio =irq_to_gpio (d->irq); +int gpio =pxa_irq_to_gpio (d->irq);unsigned long gpdr, mask =GPIO_bit (gpio); c =gpio_to_pxachip (gpio);
@@ -218,7 +218,7 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)while (n <BITS_PER_LONG ) { loop =1 ; -generic_handle_irq (gpio_to_irq (gpio_base + n)); +generic_handle_irq (pxa_gpio_to_irq (gpio_base + n)); n =find_next_bit (&gedr,BITS_PER_LONG , n +1 ); } }
@@ -227,7 +227,7 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)static void pxa_ack_muxed_gpio (struct irq_data *d) { -int gpio =irq_to_gpio (d->irq); +int gpio =pxa_irq_to_gpio (d->irq);struct pxa_gpio_chip *c =gpio_to_pxachip (gpio);__raw_writel (GPIO_bit (gpio), c->regbase +GEDR_OFFSET );
@@ -235,7 +235,7 @@ static void pxa_ack_muxed_gpio(struct irq_data *d)static void pxa_mask_muxed_gpio (struct irq_data *d) { -int gpio =irq_to_gpio (d->irq); +int gpio =pxa_irq_to_gpio (d->irq);struct pxa_gpio_chip *c =gpio_to_pxachip (gpio);uint32_t grer, gfer;
@@ -249,7 +249,7 @@ static void pxa_mask_muxed_gpio(struct irq_data *d)static void pxa_unmask_muxed_gpio (struct irq_data *d) { -int gpio =irq_to_gpio (d->irq); +int gpio =pxa_irq_to_gpio (d->irq);struct pxa_gpio_chip *c =gpio_to_pxachip (gpio); c->irq_mask |=GPIO_bit (gpio);
@@ -282,7 +282,8 @@ void __init pxa_init_gpio(int mux_irq, int start, int end,__raw_writel (~0 ,c->regbase +GEDR_OFFSET ); } -for (irq =gpio_to_irq (start); irq <=gpio_to_irq (end); irq++) { +for (irq =pxa_gpio_to_irq (start); irq <=pxa_gpio_to_irq (end); + irq++) {irq_set_chip_and_handler (irq, &pxa_muxed_gpio_chip, handle_edge_irq);set_irq_flags (irq,IRQF_VALID |IRQF_PROBE );
Signature · 1 line
1.7.2.5
PATCH 3/5 ARM: pxa: rename gpio_to_irq and irq_to_gpio
Quoted 5 lines · Haojian Zhuang
Rename
gpio_to_irq()topxa_gpio_to_irq(), and renameirq_to_gpio()topxa_irq_to_gpio(). This rename operations is used to avoid naming confliction while gpio driver is moved intodrivers/gpio/directory.Signed-off-by Haojian Zhuang <[email protected]>
Acked-by Grant Likely <[email protected]>
Quoted 991 lines
--- arch/arm/mach-mmp/aspenite.c | 4 +- arch/arm/mach-mmp/flint.c | 4 +- arch/arm/mach-mmp/include/mach/gpio.h | 4 +- arch/arm/mach-mmp/tavorevb.c | 4 +- arch/arm/mach-mmp/teton_bga.c | 2 +- arch/arm/mach-pxa/capc7117.c | 12 ++++---- arch/arm/mach-pxa/cm-x270.c | 2 +- arch/arm/mach-pxa/cm-x2xx-pci.c | 4 +- arch/arm/mach-pxa/colibri-pxa270.c | 6 ++-- arch/arm/mach-pxa/colibri-pxa300.c | 4 +- arch/arm/mach-pxa/colibri-pxa320.c | 4 +- arch/arm/mach-pxa/corgi.c | 2 +- arch/arm/mach-pxa/em-x270.c | 6 ++-- arch/arm/mach-pxa/hx4700.c | 18 +++++++------- arch/arm/mach-pxa/icontrol.c | 8 +++--- arch/arm/mach-pxa/include/mach/csb726.h | 4 +- arch/arm/mach-pxa/include/mach/gpio.h | 4 +- arch/arm/mach-pxa/littleton.c | 2 +- arch/arm/mach-pxa/magician.c | 8 +++--- arch/arm/mach-pxa/mioa701.c | 12 ++++---- arch/arm/mach-pxa/mxm8x10.c | 4 +- arch/arm/mach-pxa/poodle.c | 2 +- arch/arm/mach-pxa/pxa25x.c | 2 +- arch/arm/mach-pxa/pxa27x.c | 2 +- arch/arm/mach-pxa/raumfeld.c | 14 +++++----- arch/arm/mach-pxa/saar.c | 6 ++-- arch/arm/mach-pxa/saarb.c | 2 +- arch/arm/mach-pxa/spitz.c | 2 +- arch/arm/mach-pxa/stargate2.c | 4 +- arch/arm/mach-pxa/tavorevb.c | 4 +- arch/arm/mach-pxa/tavorevb3.c | 2 +- arch/arm/mach-pxa/tosa.c | 4 +- arch/arm/mach-pxa/viper.c | 16 ++++++------ arch/arm/mach-pxa/vpac270.c | 4 +- arch/arm/mach-pxa/z2.c | 2 +- arch/arm/mach-pxa/zeus.c | 40 +++++++++++++++++------------- arch/arm/mach-pxa/zylonite.c | 4 +- arch/arm/plat-pxa/gpio.c | 13 +++++---- 38 files changed, 124 insertions(+), 117 deletions(-)arch/arm/mach-mmp/aspenite.c +2
-2@@ -119,8 +119,8 @@ static struct resource smc91x_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gpio_to_irq(27), - .end = gpio_to_irq(27), + .start = pxa_gpio_to_irq(27), + .end = pxa_gpio_to_irq(27), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, } };arch/arm/mach-mmp/flint.c +2
-2@@ -87,8 +87,8 @@ static struct resource smc91x_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gpio_to_irq(155), - .end = gpio_to_irq(155), + .start = pxa_gpio_to_irq(155), + .end = pxa_gpio_to_irq(155), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, } };arch/arm/mach-mmp/include/mach/gpio.h +2
-2@@ -13,8 +13,8 @@#define NR_BUILTIN_GPIO IRQ_GPIO_NUM#define gpio_to_bank (gpio) ((gpio) >> 5) -#define gpio_to_irq (gpio) (IRQ_GPIO_START + (gpio)) -#define irq_to_gpio (irq) ((irq) - IRQ_GPIO_START) +#define pxa_gpio_to_irq (gpio) (IRQ_GPIO_START + (gpio)) +#define pxa_irq_to_gpio (irq) ((irq) - IRQ_GPIO_START)#define __gpio_is_inverted (gpio) (0)arch/arm/mach-mmp/tavorevb.c +2
-2@@ -70,8 +70,8 @@ static struct resource smc91x_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gpio_to_irq(80), - .end = gpio_to_irq(80), + .start = pxa_gpio_to_irq(80), + .end = pxa_gpio_to_irq(80), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, } };arch/arm/mach-mmp/teton_bga.c +1
-1@@ -66,7 +66,7 @@ static struct pxa27x_keypad_platform_data teton_bga_keypad_info __initdata = {static struct i2c_board_info teton_bga_i2c_info[]__initdata = { {I2C_BOARD_INFO ("ds1337" ,0x68 ), - .irq =gpio_to_irq (RTC_INT_GPIO ) + .irq =pxa_gpio_to_irq (RTC_INT_GPIO ) }, };arch/arm/mach-pxa/capc7117.c +6
-6@@ -50,8 +50,8 @@ static struct resource capc7117_ide_resources[] = { .flags = IORESOURCE_MEM }, [2] = { - .start = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO76)), - .end = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO76)), + .start = pxa_gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO76)), + .end = pxa_gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO76)), .flags = IORESOURCE_IRQ | IRQF_TRIGGER_RISING } };@@ -80,7 +80,7 @@ static void __init capc7117_ide_init(void)static struct plat_serial8250_port ti16c752_platform_data[] = { [0 ] = { .mapbase =0x14000000 , - .irq =gpio_to_irq (mfp_to_gpio (MFP_PIN_GPIO78 )), + .irq =pxa_gpio_to_irq (mfp_to_gpio (MFP_PIN_GPIO78 )), .irqflags =IRQF_TRIGGER_RISING , .flags =TI16C752_FLAGS , .iotype =UPIO_MEM ,@@ -89,7 +89,7 @@ static struct plat_serial8250_port ti16c752_platform_data[] = { }, [1] = { .mapbase = 0x14000040, - .irq = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO79)), + .irq = pxa_gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO79)), .irqflags = IRQF_TRIGGER_RISING, .flags = TI16C752_FLAGS, .iotype = UPIO_MEM,@@ -98,7 +98,7 @@ static struct plat_serial8250_port ti16c752_platform_data[] = { }, [2] = { .mapbase = 0x14000080, - .irq = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO80)), + .irq = pxa_gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO80)), .irqflags = IRQF_TRIGGER_RISING, .flags = TI16C752_FLAGS, .iotype = UPIO_MEM,@@ -107,7 +107,7 @@ static struct plat_serial8250_port ti16c752_platform_data[] = { }, [3] = { .mapbase = 0x140000c0, - .irq = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO81)), + .irq = pxa_gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO81)), .irqflags = IRQF_TRIGGER_RISING, .flags = TI16C752_FLAGS, .iotype = UPIO_MEM,arch/arm/mach-pxa/cm-x270.c +1
-1@@ -380,7 +380,7 @@ static struct spi_board_info cm_x270_spi_devices[] __initdata = { .modalias = "libertas_spi", .max_speed_hz = 13000000, .bus_num = 2, - .irq = gpio_to_irq(95), + .irq = pxa_gpio_to_irq(95), .chip_select = 0, .controller_data = &cm_x270_libertas_chip, .platform_data = &cm_x270_libertas_pdata,arch/arm/mach-pxa/cm-x2xx-pci.c +2
-2@@ -43,9 +43,9 @@ void __cmx2xx_pci_init_irq(int irq_gpio) cmx2xx_it8152_irq_gpio = irq_gpio; -irq_set_irq_type (gpio_to_irq (irq_gpio),IRQ_TYPE_EDGE_RISING ); +irq_set_irq_type (pxa_gpio_to_irq (irq_gpio),IRQ_TYPE_EDGE_RISING ); -irq_set_chained_handler (gpio_to_irq (irq_gpio), +irq_set_chained_handler (pxa_gpio_to_irq (irq_gpio), cmx2xx_it8152_irq_demux); }arch/arm/mach-pxa/colibri-pxa270.c +3
-3@@ -217,8 +217,8 @@ static struct resource colibri_pxa270_dm9000_resources[] = { .flags = IORESOURCE_MEM, }, { - .start = gpio_to_irq(GPIO114_COLIBRI_PXA270_ETH_IRQ), - .end = gpio_to_irq(GPIO114_COLIBRI_PXA270_ETH_IRQ), + .start = pxa_gpio_to_irq(GPIO114_COLIBRI_PXA270_ETH_IRQ), + .end = pxa_gpio_to_irq(GPIO114_COLIBRI_PXA270_ETH_IRQ), .flags = IORESOURCE_IRQ | IRQF_TRIGGER_RISING, }, };@@ -248,7 +248,7 @@ static pxa2xx_audio_ops_t colibri_pxa270_ac97_pdata = { };static struct ucb1400_pdata colibri_pxa270_ucb1400_pdata = { - .irq =gpio_to_irq (GPIO113_COLIBRI_PXA270_TS_IRQ ), + .irq =pxa_gpio_to_irq (GPIO113_COLIBRI_PXA270_TS_IRQ ), };static struct platform_device colibri_pxa270_ucb1400_device = {arch/arm/mach-pxa/colibri-pxa300.c +2
-2@@ -78,8 +78,8 @@ static struct resource colibri_asix_resource[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gpio_to_irq(COLIBRI_ETH_IRQ_GPIO), - .end = gpio_to_irq(COLIBRI_ETH_IRQ_GPIO), + .start = pxa_gpio_to_irq(COLIBRI_ETH_IRQ_GPIO), + .end = pxa_gpio_to_irq(COLIBRI_ETH_IRQ_GPIO), .flags = IORESOURCE_IRQ | IRQF_TRIGGER_FALLING, } };arch/arm/mach-pxa/colibri-pxa320.c +2
-2@@ -115,8 +115,8 @@ static struct resource colibri_asix_resource[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gpio_to_irq(COLIBRI_ETH_IRQ_GPIO), - .end = gpio_to_irq(COLIBRI_ETH_IRQ_GPIO), + .start = pxa_gpio_to_irq(COLIBRI_ETH_IRQ_GPIO), + .end = pxa_gpio_to_irq(COLIBRI_ETH_IRQ_GPIO), .flags = IORESOURCE_IRQ | IRQF_TRIGGER_FALLING, } };arch/arm/mach-pxa/corgi.c +1
-1@@ -531,7 +531,7 @@ static struct spi_board_info corgi_spi_devices[] = { .chip_select = 0, .platform_data = &corgi_ads7846_info, .controller_data= &corgi_ads7846_chip, - .irq = gpio_to_irq(CORGI_GPIO_TP_INT), + .irq = pxa_gpio_to_irq(CORGI_GPIO_TP_INT), }, { .modalias = "corgi-lcd", .max_speed_hz = 50000,arch/arm/mach-pxa/em-x270.c +3
-3@@ -558,7 +558,7 @@ static int em_x270_mci_init(struct device *dev,return PTR_ERR (em_x270_sdio_ldo); } - err =request_irq (gpio_to_irq (mmc_cd), em_x270_detect_int, + err =request_irq (pxa_gpio_to_irq (mmc_cd), em_x270_detect_int,IRQF_DISABLED |IRQF_TRIGGER_RISING |IRQF_TRIGGER_FALLING ,"MMC card detect" , data);@@ -588,7 +588,7 @@ static int em_x270_mci_init(struct device *dev,return 0 ; err_gpio_wp: -free_irq (gpio_to_irq (mmc_cd), data); +free_irq (pxa_gpio_to_irq (mmc_cd), data); err_irq:regulator_put (em_x270_sdio_ldo);@@ -611,7 +611,7 @@ static void em_x270_mci_setpower(struct device *dev, unsigned int vdd)static void em_x270_mci_exit (struct device *dev,void *data) { -free_irq (gpio_to_irq (mmc_cd), data); +free_irq (pxa_gpio_to_irq (mmc_cd), data);regulator_put (em_x270_sdio_ldo);if (machine_is_em_x270 ())arch/arm/mach-pxa/hx4700.c +9
-9@@ -252,8 +252,8 @@ static struct resource asic3_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gpio_to_irq(GPIO12_HX4700_ASIC3_IRQ), - .end = gpio_to_irq(GPIO12_HX4700_ASIC3_IRQ), + .start = pxa_gpio_to_irq(GPIO12_HX4700_ASIC3_IRQ), + .end = pxa_gpio_to_irq(GPIO12_HX4700_ASIC3_IRQ), .flags = IORESOURCE_IRQ, },/* SD part */ @@ -263,8 +263,8 @@ static struct resource asic3_resources[] = { .flags = IORESOURCE_MEM, }, [3] = { - .start = gpio_to_irq(GPIO66_HX4700_ASIC3_nSDIO_IRQ), - .end = gpio_to_irq(GPIO66_HX4700_ASIC3_nSDIO_IRQ), + .start = pxa_gpio_to_irq(GPIO66_HX4700_ASIC3_nSDIO_IRQ), + .end = pxa_gpio_to_irq(GPIO66_HX4700_ASIC3_nSDIO_IRQ), .flags = IORESOURCE_IRQ, }, };@@ -587,7 +587,7 @@ static struct spi_board_info tsc2046_board_info[] __initdata = { .modalias = "ads7846", .bus_num = 2, .max_speed_hz = 2600000, /* 100 kHz sample rate */ - .irq = gpio_to_irq(GPIO58_HX4700_TSC2046_nPENIRQ), + .irq = pxa_gpio_to_irq(GPIO58_HX4700_TSC2046_nPENIRQ), .platform_data = &tsc2046_info, .controller_data = &tsc2046_chip, },@@ -635,15 +635,15 @@ static struct resource power_supply_resources[] = { .name = "ac", .flags =IORESOURCE_IRQ |IORESOURCE_IRQ_HIGHEDGE | IORESOURCE_IRQ_LOWEDGE, - .start = gpio_to_irq(GPIOD9_nAC_IN), - .end = gpio_to_irq(GPIOD9_nAC_IN), + .start = pxa_gpio_to_irq(GPIOD9_nAC_IN), + .end = pxa_gpio_to_irq(GPIOD9_nAC_IN), }, [1] = { .name = "usb", .flags =IORESOURCE_IRQ |IORESOURCE_IRQ_HIGHEDGE | IORESOURCE_IRQ_LOWEDGE, - .start = gpio_to_irq(GPIOD14_nUSBC_DETECT), - .end = gpio_to_irq(GPIOD14_nUSBC_DETECT), + .start = pxa_gpio_to_irq(GPIOD14_nUSBC_DETECT), + .end = pxa_gpio_to_irq(GPIOD14_nUSBC_DETECT), }, };arch/arm/mach-pxa/icontrol.c +4
-4@@ -86,7 +86,7 @@ static struct spi_board_info mcp251x_board_info[] = { .chip_select = 0, .platform_data = &mcp251x_info, .controller_data = &mcp251x_chip_info1, - .irq =gpio_to_irq (ICONTROL_MCP251x_nIRQ1) + .irq =pxa_gpio_to_irq (ICONTROL_MCP251x_nIRQ1) }, { .modalias = "mcp2515",@@ -95,7 +95,7 @@ static struct spi_board_info mcp251x_board_info[] = { .chip_select = 1, .platform_data = &mcp251x_info, .controller_data = &mcp251x_chip_info2, - .irq =gpio_to_irq (ICONTROL_MCP251x_nIRQ2) + .irq =pxa_gpio_to_irq (ICONTROL_MCP251x_nIRQ2) }, { .modalias = "mcp2515",@@ -104,7 +104,7 @@ static struct spi_board_info mcp251x_board_info[] = { .chip_select = 0, .platform_data = &mcp251x_info, .controller_data = &mcp251x_chip_info3, - .irq =gpio_to_irq (ICONTROL_MCP251x_nIRQ3) + .irq =pxa_gpio_to_irq (ICONTROL_MCP251x_nIRQ3) }, { .modalias = "mcp2515",@@ -113,7 +113,7 @@ static struct spi_board_info mcp251x_board_info[] = { .chip_select = 1, .platform_data = &mcp251x_info, .controller_data = &mcp251x_chip_info4, - .irq = gpio_to_irq(ICONTROL_MCP251x_nIRQ4) + .irq = pxa_gpio_to_irq(ICONTROL_MCP251x_nIRQ4) } };arch/arm/mach-pxa/include/mach/csb726.h +2
-2@@ -19,8 +19,8 @@#define CSB726_FLASH_SIZE (64 * 1024 * 1024)#define CSB726_FLASH_uMON (8 * 1024 * 1024) -#define CSB726_IRQ_LAN gpio_to_irq(CSB726_GPIO_IRQ_LAN) -#define CSB726_IRQ_SM501 gpio_to_irq(CSB726_GPIO_IRQ_SM501) +#define CSB726_IRQ_LAN pxa_gpio_to_irq(CSB726_GPIO_IRQ_LAN) +#define CSB726_IRQ_SM501 pxa_gpio_to_irq(CSB726_GPIO_IRQ_SM501)#endif arch/arm/mach-pxa/include/mach/gpio.h +2
-2@@ -58,9 +58,9 @@#define NR_BUILTIN_GPIO PXA_GPIO_IRQ_NUM#define gpio_to_bank (gpio) ((gpio) >> 5) -#define gpio_to_irq (gpio) IRQ_GPIO(gpio) +#define pxa_gpio_to_irq (gpio) IRQ_GPIO(gpio) -static inline int irq_to_gpio (unsigned int irq) +static inline int pxa_irq_to_gpio (unsigned int irq) {int gpio;arch/arm/mach-pxa/littleton.c +1
-1@@ -396,7 +396,7 @@ static struct i2c_board_info littleton_i2c_info[] = { .type = "da9034", .addr = 0x34, .platform_data = &littleton_da9034_info, - .irq = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO18)), + .irq = pxa_gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO18)), }, [1] = { .type = "max7320",arch/arm/mach-pxa/magician.c +4
-4@@ -184,8 +184,8 @@ static struct resource egpio_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gpio_to_irq(GPIO13_MAGICIAN_CPLD_IRQ), - .end = gpio_to_irq(GPIO13_MAGICIAN_CPLD_IRQ), + .start = pxa_gpio_to_irq(GPIO13_MAGICIAN_CPLD_IRQ), + .end = pxa_gpio_to_irq(GPIO13_MAGICIAN_CPLD_IRQ), .flags = IORESOURCE_IRQ, }, };@@ -468,8 +468,8 @@ static struct resource pasic3_resources[] = { },/* No IRQ handler in the PASIC3, DS1WM needs an external IRQ */ [1 ] = { - .start =gpio_to_irq (GPIO107_MAGICIAN_DS1WM_IRQ ), - .end =gpio_to_irq (GPIO107_MAGICIAN_DS1WM_IRQ ), + .start =pxa_gpio_to_irq (GPIO107_MAGICIAN_DS1WM_IRQ ), + .end =pxa_gpio_to_irq (GPIO107_MAGICIAN_DS1WM_IRQ ), .flags =IORESOURCE_IRQ |IORESOURCE_IRQ_HIGHEDGE , } };arch/arm/mach-pxa/mioa701.c +6
-6@@ -314,7 +314,7 @@ static int __init gsm_init(void) rc =gpio_request_array (ARRAY_AND_SIZE (gsm_gpios));if (rc) goto err_gpio; - rc =request_irq (gpio_to_irq (GPIO25_GSM_MOD_ON_STATE ), gsm_on_irq, + rc =request_irq (pxa_gpio_to_irq (GPIO25_GSM_MOD_ON_STATE ), gsm_on_irq,IRQF_TRIGGER_RISING |IRQF_TRIGGER_FALLING ,"GSM XS200 Power Irq" ,NULL );if (rc)@@ -333,7 +333,7 @@ err_gpio:static void gsm_exit (void ) { -free_irq (gpio_to_irq (GPIO25_GSM_MOD_ON_STATE ),NULL ); +free_irq (pxa_gpio_to_irq (GPIO25_GSM_MOD_ON_STATE ),NULL );gpio_free_array (ARRAY_AND_SIZE (gsm_gpios)); }@@ -541,15 +541,15 @@ static struct pda_power_pdata power_pdata = {static struct resource power_resources[] = { [0 ] = { .name ="ac" , - .start =gpio_to_irq (GPIO96_AC_DETECT ), - .end =gpio_to_irq (GPIO96_AC_DETECT ), + .start =pxa_gpio_to_irq (GPIO96_AC_DETECT ), + .end =pxa_gpio_to_irq (GPIO96_AC_DETECT ), .flags =IORESOURCE_IRQ |IORESOURCE_IRQ_HIGHEDGE |IORESOURCE_IRQ_LOWEDGE , }, [1 ] = { .name ="usb" , - .start =gpio_to_irq (GPIO13_nUSB_DETECT), - .end =gpio_to_irq (GPIO13_nUSB_DETECT), + .start =pxa_gpio_to_irq (GPIO13_nUSB_DETECT), + .end =pxa_gpio_to_irq (GPIO13_nUSB_DETECT), .flags =IORESOURCE_IRQ |IORESOURCE_IRQ_HIGHEDGE |IORESOURCE_IRQ_LOWEDGE , },arch/arm/mach-pxa/mxm8x10.c +2
-2@@ -417,8 +417,8 @@ static struct resource dm9k_resources[] = { .flags = IORESOURCE_MEM }, [2] = { - .start = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO9)), - .end = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO9)), + .start = pxa_gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO9)), + .end = pxa_gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO9)), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE } };arch/arm/mach-pxa/poodle.c +1
-1@@ -212,7 +212,7 @@ static struct spi_board_info poodle_spi_devices[] = { .bus_num = 1, .platform_data = &poodle_ads7846_info, .controller_data= &poodle_ads7846_chip, - .irq = gpio_to_irq(POODLE_GPIO_TP_INT), + .irq = pxa_gpio_to_irq(POODLE_GPIO_TP_INT), }, };arch/arm/mach-pxa/pxa25x.c +1
-1@@ -286,7 +286,7 @@ static inline void pxa25x_init_pm(void) {}static int pxa25x_set_wake (struct irq_data *d,unsigned int on) { -int gpio =irq_to_gpio (d->irq); +int gpio =pxa_irq_to_gpio (d->irq);uint32_t mask =0 ;if (gpio >=0 && gpio <85 )arch/arm/mach-pxa/pxa27x.c +1
-1@@ -354,7 +354,7 @@ static inline void pxa27x_init_pm(void) {}*/ static int pxa27x_set_wake (struct irq_data *d,unsigned int on) { -int gpio =irq_to_gpio (d->irq); +int gpio =pxa_irq_to_gpio (d->irq);uint32_t mask;if (gpio >=0 && gpio <128 )arch/arm/mach-pxa/raumfeld.c +7
-7@@ -292,8 +292,8 @@ static struct resource smc91x_resources[] = { .flags = IORESOURCE_MEM, }, { - .start = gpio_to_irq(GPIO_ETH_IRQ), - .end = gpio_to_irq(GPIO_ETH_IRQ), + .start = pxa_gpio_to_irq(GPIO_ETH_IRQ), + .end = pxa_gpio_to_irq(GPIO_ETH_IRQ), .flags = IORESOURCE_IRQ | IRQF_TRIGGER_FALLING, } };@@ -672,7 +672,7 @@ static struct lis3lv02d_platform_data lis3_pdata = { .chip_select = 1, \ .controller_data = (void *) GPIO_ACCEL_CS, \ .platform_data = &lis3_pdata, \ - .irq = gpio_to_irq(GPIO_ACCEL_IRQ), \ + .irq = pxa_gpio_to_irq(GPIO_ACCEL_IRQ), \ }#define SPI_DAC7512 \@@ -824,10 +824,10 @@ static void __init raumfeld_power_init(void)else gpio_direction_output (GPIO_CHARGE_USB_SUSP ,0 ); - power_supply_resources[0 ].start =gpio_to_irq (GPIO_CHARGE_DC_OK ); - power_supply_resources[0 ].end =gpio_to_irq (GPIO_CHARGE_DC_OK ); + power_supply_resources[0 ].start =pxa_gpio_to_irq (GPIO_CHARGE_DC_OK ); + power_supply_resources[0 ].end =pxa_gpio_to_irq (GPIO_CHARGE_DC_OK ); - ret =request_irq (gpio_to_irq (GPIO_CHARGE_DONE ), + ret =request_irq (pxa_gpio_to_irq (GPIO_CHARGE_DONE ), &charge_done_irq,IORESOURCE_IRQ_LOWEDGE ,"charge_done" ,NULL );@@ -956,7 +956,7 @@ static struct eeti_ts_platform_data eeti_ts_pdata = {static struct i2c_board_info raumfeld_controller_i2c_board_info__initdata = { .type ="eeti_ts" , .addr =0x0a , - .irq =gpio_to_irq (GPIO_TOUCH_IRQ ), + .irq =pxa_gpio_to_irq (GPIO_TOUCH_IRQ ), .platform_data = &eeti_ts_pdata, };arch/arm/mach-pxa/saar.c +3
-3@@ -96,8 +96,8 @@ static struct resource smc91x_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO97)), - .end = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO97)), + .start = pxa_gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO97)), + .end = pxa_gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO97)), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, } };@@ -502,7 +502,7 @@ static struct i2c_board_info saar_i2c_info[] = { .type = "da9034", .addr = 0x34, .platform_data = &saar_da9034_info, - .irq = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO83)), + .irq = pxa_gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO83)), }, };arch/arm/mach-pxa/saarb.c +1
-1@@ -90,7 +90,7 @@ static struct i2c_board_info saarb_i2c_info[] = { .type = "88PM860x", .addr = 0x34, .platform_data = &saarb_pm8607_info, - .irq = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO83)), + .irq = pxa_gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO83)), }, };arch/arm/mach-pxa/spitz.c +1
-1@@ -552,7 +552,7 @@ static struct spi_board_info spitz_spi_devices[] = { .chip_select = 0, .platform_data = &spitz_ads7846_info, .controller_data = &spitz_ads7846_chip, - .irq = gpio_to_irq(SPITZ_GPIO_TP_INT), + .irq = pxa_gpio_to_irq(SPITZ_GPIO_TP_INT), }, { .modalias = "corgi-lcd", .max_speed_hz = 50000,arch/arm/mach-pxa/stargate2.c +2
-2@@ -546,7 +546,7 @@ static struct i2c_board_info __initdata imote2_pwr_i2c_board_info[] = { .type = "da9030", .addr = 0x49, .platform_data = &imote2_da9030_pdata, - .irq = gpio_to_irq(1), + .irq = pxa_gpio_to_irq(1), }, };@@ -913,7 +913,7 @@ static struct i2c_board_info __initdata stargate2_pwr_i2c_board_info[] = { .type = "da9030", .addr = 0x49, .platform_data = &stargate2_da9030_pdata, - .irq = gpio_to_irq(1), + .irq = pxa_gpio_to_irq(1), }, };arch/arm/mach-pxa/tavorevb.c +2
-2@@ -85,8 +85,8 @@ static struct resource smc91x_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO47)), - .end = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO47)), + .start = pxa_gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO47)), + .end = pxa_gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO47)), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, } };arch/arm/mach-pxa/tavorevb3.c +1
-1@@ -101,7 +101,7 @@ static struct i2c_board_info evb3_i2c_info[] = { .type = "88PM860x", .addr = 0x34, .platform_data = &evb3_pm8607_info, - .irq = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO83)), + .irq = pxa_gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO83)), }, };arch/arm/mach-pxa/tosa.c +2
-2@@ -404,8 +404,8 @@ static struct pda_power_pdata tosa_power_data = {static struct resource tosa_power_resource[] = { { .name ="ac" , - .start =gpio_to_irq (TOSA_GPIO_AC_IN ), - .end =gpio_to_irq (TOSA_GPIO_AC_IN ), + .start =pxa_gpio_to_irq (TOSA_GPIO_AC_IN ), + .end =pxa_gpio_to_irq (TOSA_GPIO_AC_IN ), .flags =IORESOURCE_IRQ |IORESOURCE_IRQ_HIGHEDGE |IORESOURCE_IRQ_LOWEDGE ,arch/arm/mach-pxa/viper.c +8
-8@@ -315,9 +315,9 @@ static void __init viper_init_irq(void)set_irq_flags (isa_irq,IRQF_VALID |IRQF_PROBE ); } -irq_set_chained_handler (gpio_to_irq (VIPER_CPLD_GPIO ), +irq_set_chained_handler (pxa_gpio_to_irq (VIPER_CPLD_GPIO ), viper_irq_handler); -irq_set_irq_type (gpio_to_irq (VIPER_CPLD_GPIO ),IRQ_TYPE_EDGE_BOTH ); +irq_set_irq_type (pxa_gpio_to_irq (VIPER_CPLD_GPIO ),IRQ_TYPE_EDGE_BOTH ); }/* Flat Panel */ @@ -422,8 +422,8 @@ static struct resource smc91x_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = gpio_to_irq(VIPER_ETH_GPIO), - .end = gpio_to_irq(VIPER_ETH_GPIO), + .start = pxa_gpio_to_irq(VIPER_ETH_GPIO), + .end = pxa_gpio_to_irq(VIPER_ETH_GPIO), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, }, [2] = {@@ -546,7 +546,7 @@ static struct plat_serial8250_port serial_platform_data[] = {/* External UARTs */ { .mapbase = VIPER_UARTA_PHYS, - .irq = gpio_to_irq(VIPER_UARTA_GPIO), + .irq = pxa_gpio_to_irq(VIPER_UARTA_GPIO), .irqflags = IRQF_TRIGGER_RISING, .uartclk = 1843200, .regshift = 1,@@ -556,7 +556,7 @@ static struct plat_serial8250_port serial_platform_data[] = { }, { .mapbase = VIPER_UARTB_PHYS, - .irq = gpio_to_irq(VIPER_UARTB_GPIO), + .irq = pxa_gpio_to_irq(VIPER_UARTB_GPIO), .irqflags = IRQF_TRIGGER_RISING, .uartclk = 1843200, .regshift = 1,@@ -596,8 +596,8 @@ static struct resource isp116x_resources[] = { .flags = IORESOURCE_MEM, }, [2] = { - .start = gpio_to_irq(VIPER_USB_GPIO), - .end = gpio_to_irq(VIPER_USB_GPIO), + .start = pxa_gpio_to_irq(VIPER_USB_GPIO), + .end = pxa_gpio_to_irq(VIPER_USB_GPIO), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, }, };arch/arm/mach-pxa/vpac270.c +2
-2@@ -610,8 +610,8 @@ static struct resource vpac270_ide_resources[] = { .flags = IORESOURCE_DMA }, [3] = { /* IDE IRQ pin */ - .start = gpio_to_irq(GPIO36_VPAC270_IDE_IRQ), - .end = gpio_to_irq(GPIO36_VPAC270_IDE_IRQ), + .start = pxa_gpio_to_irq(GPIO36_VPAC270_IDE_IRQ), + .end = pxa_gpio_to_irq(GPIO36_VPAC270_IDE_IRQ), .flags = IORESOURCE_IRQ } };arch/arm/mach-pxa/z2.c +1
-1@@ -573,7 +573,7 @@ static struct spi_board_info spi_board_info[] __initdata = { .modalias = "libertas_spi", .platform_data = &z2_lbs_pdata, .controller_data = &z2_lbs_chip_info, - .irq = gpio_to_irq(GPIO36_ZIPITZ2_WIFI_IRQ), + .irq = pxa_gpio_to_irq(GPIO36_ZIPITZ2_WIFI_IRQ), .max_speed_hz = 13000000, .bus_num = 1, .chip_select = 0,arch/arm/mach-pxa/zeus.c +23
-17@@ -136,12 +136,16 @@ static void __init zeus_init_irq(void)/* Peripheral IRQs. It would be nice to move those inside driver configuration, but it is not supported at the moment. */ -irq_set_irq_type (gpio_to_irq (ZEUS_AC97_GPIO ),IRQ_TYPE_EDGE_RISING ); -irq_set_irq_type (gpio_to_irq (ZEUS_WAKEUP_GPIO ),IRQ_TYPE_EDGE_RISING ); -irq_set_irq_type (gpio_to_irq (ZEUS_PTT_GPIO ),IRQ_TYPE_EDGE_RISING ); -irq_set_irq_type (gpio_to_irq (ZEUS_EXTGPIO_GPIO ), +irq_set_irq_type (pxa_gpio_to_irq (ZEUS_AC97_GPIO ), +IRQ_TYPE_EDGE_RISING ); +irq_set_irq_type (pxa_gpio_to_irq (ZEUS_WAKEUP_GPIO ), +IRQ_TYPE_EDGE_RISING ); +irq_set_irq_type (pxa_gpio_to_irq (ZEUS_PTT_GPIO ), +IRQ_TYPE_EDGE_RISING ); +irq_set_irq_type (pxa_gpio_to_irq (ZEUS_EXTGPIO_GPIO ), +IRQ_TYPE_EDGE_FALLING ); +irq_set_irq_type (pxa_gpio_to_irq (ZEUS_CAN_GPIO ),IRQ_TYPE_EDGE_FALLING ); -irq_set_irq_type (gpio_to_irq (ZEUS_CAN_GPIO ),IRQ_TYPE_EDGE_FALLING );/* Setup ISA IRQs */ for (level =0 ; level <ARRAY_SIZE (zeus_isa_irqs); level++) {@@ -151,8 +155,10 @@ static void __init zeus_init_irq(void)set_irq_flags (isa_irq,IRQF_VALID |IRQF_PROBE ); } -irq_set_irq_type (gpio_to_irq (ZEUS_ISA_GPIO ),IRQ_TYPE_EDGE_RISING ); -irq_set_chained_handler (gpio_to_irq (ZEUS_ISA_GPIO ), zeus_irq_handler); +irq_set_irq_type (pxa_gpio_to_irq (ZEUS_ISA_GPIO ), +IRQ_TYPE_EDGE_RISING ); +irq_set_chained_handler (pxa_gpio_to_irq (ZEUS_ISA_GPIO ), + zeus_irq_handler); }@@ -233,7 +239,7 @@ static struct plat_serial8250_port serial_platform_data[] = {/* FIXME: Shared IRQs on COM1-COM4 will not work properly on v1i1 hardware. */ {/* COM1 */ .mapbase = 0x10000000, - .irq = gpio_to_irq(ZEUS_UARTA_GPIO), + .irq = pxa_gpio_to_irq(ZEUS_UARTA_GPIO), .irqflags = IRQF_TRIGGER_RISING, .uartclk = 14745600, .regshift = 1,@@ -242,7 +248,7 @@ static struct plat_serial8250_port serial_platform_data[] = { }, {/* COM2 */ .mapbase = 0x10800000, - .irq = gpio_to_irq(ZEUS_UARTB_GPIO), + .irq = pxa_gpio_to_irq(ZEUS_UARTB_GPIO), .irqflags = IRQF_TRIGGER_RISING, .uartclk = 14745600, .regshift = 1,@@ -251,7 +257,7 @@ static struct plat_serial8250_port serial_platform_data[] = { }, {/* COM3 */ .mapbase = 0x11000000, - .irq = gpio_to_irq(ZEUS_UARTC_GPIO), + .irq = pxa_gpio_to_irq(ZEUS_UARTC_GPIO), .irqflags = IRQF_TRIGGER_RISING, .uartclk = 14745600, .regshift = 1,@@ -260,7 +266,7 @@ static struct plat_serial8250_port serial_platform_data[] = { }, {/* COM4 */ .mapbase = 0x11800000, - .irq = gpio_to_irq(ZEUS_UARTD_GPIO), + .irq = pxa_gpio_to_irq(ZEUS_UARTD_GPIO), .irqflags = IRQF_TRIGGER_RISING, .uartclk = 14745600, .regshift = 1,@@ -321,8 +327,8 @@ static struct resource zeus_dm9k0_resource[] = { .flags = IORESOURCE_MEM }, [2] = { - .start = gpio_to_irq(ZEUS_ETH0_GPIO), - .end = gpio_to_irq(ZEUS_ETH0_GPIO), + .start = pxa_gpio_to_irq(ZEUS_ETH0_GPIO), + .end = pxa_gpio_to_irq(ZEUS_ETH0_GPIO), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, }, };@@ -339,8 +345,8 @@ static struct resource zeus_dm9k1_resource[] = { .flags = IORESOURCE_MEM, }, [2] = { - .start = gpio_to_irq(ZEUS_ETH1_GPIO), - .end = gpio_to_irq(ZEUS_ETH1_GPIO), + .start = pxa_gpio_to_irq(ZEUS_ETH1_GPIO), + .end = pxa_gpio_to_irq(ZEUS_ETH1_GPIO), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, }, };@@ -423,7 +429,7 @@ static struct spi_board_info zeus_spi_board_info[] = { [0] = { .modalias = "mcp2515", .platform_data = &zeus_mcp2515_pdata, - .irq = gpio_to_irq(ZEUS_CAN_GPIO), + .irq = pxa_gpio_to_irq(ZEUS_CAN_GPIO), .max_speed_hz = 1*1000*1000, .bus_num = 3, .mode = SPI_MODE_0,@@ -753,7 +759,7 @@ static struct i2c_board_info __initdata zeus_i2c_devices[] = { { I2C_BOARD_INFO("pca9535", 0x20), .platform_data = &zeus_pca953x_pdata[2], - .irq =gpio_to_irq (ZEUS_EXTGPIO_GPIO ), + .irq =pxa_gpio_to_irq (ZEUS_EXTGPIO_GPIO ), }, { I2C_BOARD_INFO("lm75a", 0x48) }, { I2C_BOARD_INFO("24c01", 0x50) },arch/arm/mach-pxa/zylonite.c +2
-2@@ -408,8 +408,8 @@ static void __init zylonite_init(void)* Note: We depend that the bootloader set * the correct value to MSC register for SMC91x. */ - smc91x_resources[1 ].start =gpio_to_irq (gpio_eth_irq); - smc91x_resources[1 ].end =gpio_to_irq (gpio_eth_irq); + smc91x_resources[1 ].start =pxa_gpio_to_irq (gpio_eth_irq); + smc91x_resources[1 ].end =pxa_gpio_to_irq (gpio_eth_irq);platform_device_register (&smc91x_device);pxa_set_ac97_info (NULL );arch/arm/plat-pxa/gpio.c +7
-6@@ -156,7 +156,7 @@ static inline void update_edge_detect(struct pxa_gpio_chip *c)static int pxa_gpio_irq_type (struct irq_data *d,unsigned int type) {struct pxa_gpio_chip *c; -int gpio =irq_to_gpio (d->irq); +int gpio =pxa_irq_to_gpio (d->irq);unsigned long gpdr, mask =GPIO_bit (gpio); c =gpio_to_pxachip (gpio);@@ -218,7 +218,7 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)while (n <BITS_PER_LONG ) { loop =1 ; -generic_handle_irq (gpio_to_irq (gpio_base + n)); +generic_handle_irq (pxa_gpio_to_irq (gpio_base + n)); n =find_next_bit (&gedr,BITS_PER_LONG , n +1 ); } }@@ -227,7 +227,7 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)static void pxa_ack_muxed_gpio (struct irq_data *d) { -int gpio =irq_to_gpio (d->irq); +int gpio =pxa_irq_to_gpio (d->irq);struct pxa_gpio_chip *c =gpio_to_pxachip (gpio);__raw_writel (GPIO_bit (gpio), c->regbase +GEDR_OFFSET );@@ -235,7 +235,7 @@ static void pxa_ack_muxed_gpio(struct irq_data *d)static void pxa_mask_muxed_gpio (struct irq_data *d) { -int gpio =irq_to_gpio (d->irq); +int gpio =pxa_irq_to_gpio (d->irq);struct pxa_gpio_chip *c =gpio_to_pxachip (gpio);uint32_t grer, gfer;@@ -249,7 +249,7 @@ static void pxa_mask_muxed_gpio(struct irq_data *d)static void pxa_unmask_muxed_gpio (struct irq_data *d) { -int gpio =irq_to_gpio (d->irq); +int gpio =pxa_irq_to_gpio (d->irq);struct pxa_gpio_chip *c =gpio_to_pxachip (gpio); c->irq_mask |=GPIO_bit (gpio);@@ -282,7 +282,8 @@ void __init pxa_init_gpio(int mux_irq, int start, int end,__raw_writel (~0 ,c->regbase +GEDR_OFFSET ); } -for (irq =gpio_to_irq (start); irq <=gpio_to_irq (end); irq++) { +for (irq =pxa_gpio_to_irq (start); irq <=pxa_gpio_to_irq (end); + irq++) {irq_set_chip_and_handler (irq, &pxa_muxed_gpio_chip, handle_edge_irq);set_irq_flags (irq,IRQF_VALID |IRQF_PROBE );Signature · 1 line
1.7.2.5
PATCH 4/5 ARM: pxa: use chained irq for GPIO0 and GPIO1
In reply to a message not in the archiveChange interrupt of GPIO0 and GPIO1 to chained interrupt. So irq chip of gpio could be removed from irq.c. So pxa_gpio_to_irq() could be simplified.
Since IRQ_GPIO() is similar to pxa_gpio_to_irq(), remove IRQ_GPIO().
Signed-off-by Haojian Zhuang <[email protected]>
--- arch/arm/mach-mmp/include/mach/gpio.h | 3 - arch/arm/mach-mmp/include/mach/irqs.h | 3 +- arch/arm/mach-mmp/ttc_dkb.c | 2 +- arch/arm/mach-pxa/am200epd.c | 4 +- arch/arm/mach-pxa/am300epd.c | 4 +- arch/arm/mach-pxa/balloon3.c | 2 +- arch/arm/mach-pxa/cm-x270.c | 2 +- arch/arm/mach-pxa/cm-x2xx.c | 4 +- arch/arm/mach-pxa/cm-x300.c | 6 +- arch/arm/mach-pxa/em-x270.c | 6 +- arch/arm/mach-pxa/eseries.c | 4 +- arch/arm/mach-pxa/idp.c | 4 +- arch/arm/mach-pxa/include/mach/balloon3.h | 6 +- arch/arm/mach-pxa/include/mach/corgi.h | 24 ++++---- arch/arm/mach-pxa/include/mach/gpio.h | 15 ----- arch/arm/mach-pxa/include/mach/gumstix.h | 20 ++++---- arch/arm/mach-pxa/include/mach/idp.h | 14 +++--- arch/arm/mach-pxa/include/mach/irqs.h | 4 +- arch/arm/mach-pxa/include/mach/palmld.h | 8 ++-- arch/arm/mach-pxa/include/mach/palmt5.h | 8 ++-- arch/arm/mach-pxa/include/mach/palmtc.h | 4 +- arch/arm/mach-pxa/include/mach/palmtx.h | 8 ++-- arch/arm/mach-pxa/include/mach/pcm027.h | 8 ++-- arch/arm/mach-pxa/include/mach/pcm990_baseboard.h | 14 +++--- arch/arm/mach-pxa/include/mach/poodle.h | 24 ++++---- arch/arm/mach-pxa/include/mach/spitz.h | 34 ++++++------ arch/arm/mach-pxa/include/mach/tosa.h | 46 ++++++++-------- arch/arm/mach-pxa/include/mach/trizeps4.h | 16 +++--- arch/arm/mach-pxa/irq.c | 61 --------------------- arch/arm/mach-pxa/littleton.c | 4 +- arch/arm/mach-pxa/lpd270.c | 4 +- arch/arm/mach-pxa/lubbock.c | 4 +- arch/arm/mach-pxa/mainstone.c | 4 +- arch/arm/mach-pxa/poodle.c | 4 +- arch/arm/mach-pxa/sharpsl_pm.c | 24 ++++---- arch/arm/mach-pxa/stargate2.c | 22 ++++---- arch/arm/mach-pxa/vpac270.c | 6 +- arch/arm/mach-pxa/zylonite_pxa300.c | 4 +- arch/arm/plat-pxa/gpio.c | 14 +++++ 39 files changed, 192 insertions(+), 256 deletions(-)
arch/arm/mach-mmp/include/mach/gpio.h +0 -3
@@ -13,9 +13,6 @@#define NR_BUILTIN_GPIO IRQ_GPIO_NUM#define gpio_to_bank (gpio) ((gpio) >> 5) -#define pxa_gpio_to_irq (gpio) (IRQ_GPIO_START + (gpio)) -#define pxa_irq_to_gpio (irq) ((irq) - IRQ_GPIO_START) -#define __gpio_is_inverted (gpio) (0)#define __gpio_is_occupied (gpio) (0)
arch/arm/mach-mmp/include/mach/irqs.h +2 -1
@@ -220,7 +220,8 @@#define IRQ_GPIO_START 128#define IRQ_GPIO_NUM 192 -#define IRQ_GPIO (x) (IRQ_GPIO_START + (x)) +#define pxa_gpio_to_irq (gpio) (IRQ_GPIO_START + (gpio)) +#define pxa_irq_to_gpio (irq) ((irq) - IRQ_GPIO_START)#define IRQ_BOARD_START (IRQ_GPIO_START + IRQ_GPIO_NUM)
arch/arm/mach-mmp/ttc_dkb.c +1 -1
@@ -136,7 +136,7 @@ static struct i2c_board_info ttc_dkb_i2c_info[] = { { .type = "max7312", .addr = 0x23, - .irq = IRQ_GPIO(80), + .irq = pxa_gpio_to_irq(80), .platform_data = &max7312_data, }, };
arch/arm/mach-pxa/am200epd.c +2 -2
@@ -138,7 +138,7 @@ static void am200_cleanup(struct metronomefb_par *par) {int i; -free_irq (IRQ_GPIO (RDY_GPIO_PIN ), par); +free_irq (pxa_gpio_to_irq (RDY_GPIO_PIN ), par);for (i =0 ; i <ARRAY_SIZE (gpios); i++)gpio_free (gpios[i]);
@@ -292,7 +292,7 @@ static int am200_setup_irq(struct fb_info *info) {int ret; - ret =request_irq (IRQ_GPIO (RDY_GPIO_PIN ), am200_handle_irq, + ret =request_irq (pxa_gpio_to_irq (RDY_GPIO_PIN ), am200_handle_irq,IRQF_DISABLED |IRQF_TRIGGER_FALLING ,"AM200" , info->par);if (ret)
arch/arm/mach-pxa/am300epd.c +2 -2
@@ -176,7 +176,7 @@ static void am300_cleanup(struct broadsheetfb_par *par) {int i; -free_irq (IRQ_GPIO (RDY_GPIO_PIN ), par); +free_irq (pxa_gpio_to_irq (RDY_GPIO_PIN ), par);for (i =0 ; i <ARRAY_SIZE (gpios); i++)gpio_free (gpios[i]);
@@ -240,7 +240,7 @@ static int am300_setup_irq(struct fb_info *info)int ret;struct broadsheetfb_par *par = info->par; - ret =request_irq (IRQ_GPIO (RDY_GPIO_PIN ), am300_handle_irq, + ret =request_irq (pxa_gpio_to_irq (RDY_GPIO_PIN ), am300_handle_irq,IRQF_DISABLED |IRQF_TRIGGER_RISING ,"AM300" , par);if (ret)
arch/arm/mach-pxa/balloon3.c +1 -1
@@ -179,7 +179,7 @@ static unsigned long balloon3_ac97_pin_config[] __initdata = { };static struct ucb1400_pdata vpac270_ucb1400_pdata = { - .irq =IRQ_GPIO (BALLOON3_GPIO_CODEC_IRQ ), + .irq =pxa_gpio_to_irq (BALLOON3_GPIO_CODEC_IRQ ), };
arch/arm/mach-pxa/cm-x270.c +1 -1
@@ -33,7 +33,7 @@/* GPIO IRQ usage */ #define GPIO83_MMC_IRQ (83) -#define CMX270_MMC_IRQ IRQ_GPIO(GPIO83_MMC_IRQ) +#define CMX270_MMC_IRQ pxa_gpio_to_irq(GPIO83_MMC_IRQ)/* MMC power enable */ #define GPIO105_MMC_POWER (105)
arch/arm/mach-pxa/cm-x2xx.c +2 -2
@@ -58,8 +58,8 @@ extern void cmx270_init(void);#define CMX255_GPIO_IT8152_IRQ (0)#define CMX270_GPIO_IT8152_IRQ (22) -#define CMX255_ETHIRQ IRQ_GPIO(GPIO22_ETHIRQ) -#define CMX270_ETHIRQ IRQ_GPIO(GPIO10_ETHIRQ) +#define CMX255_ETHIRQ pxa_gpio_to_irq(GPIO22_ETHIRQ) +#define CMX270_ETHIRQ pxa_gpio_to_irq(GPIO10_ETHIRQ)#if defined(CONFIG_DM9000 ) || defined(CONFIG_DM9000_MODULE ) static struct resource cmx255_dm9000_resource[] = {
arch/arm/mach-pxa/cm-x300.c +3 -3
@@ -64,7 +64,7 @@#define GPIO82_MMC_IRQ (82)#define GPIO85_MMC_WP (85) -#define CM_X300_MMC_IRQ IRQ_GPIO(GPIO82_MMC_IRQ) +#define CM_X300_MMC_IRQ pxa_gpio_to_irq(GPIO82_MMC_IRQ)#define GPIO95_RTC_CS (95)#define GPIO96_RTC_WR (96)
@@ -229,8 +229,8 @@ static struct resource dm9000_resources[] = { .flags = IORESOURCE_MEM, }, [2] = { - .start = IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO99)), - .end = IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO99)), + .start = pxa_gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO99)), + .end = pxa_gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO99)), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, } };
arch/arm/mach-pxa/em-x270.c +3 -3
@@ -70,7 +70,7 @@/* common GPIOs */ #define GPIO11_NAND_CS (11)#define GPIO41_ETHIRQ (41) -#define EM_X270_ETHIRQ IRQ_GPIO(GPIO41_ETHIRQ) +#define EM_X270_ETHIRQ pxa_gpio_to_irq(GPIO41_ETHIRQ)#define GPIO115_WLAN_PWEN (115)#define GPIO19_WLAN_STRAP (19)#define GPIO9_USB_VBUS_EN (9)
@@ -805,7 +805,7 @@ static struct spi_board_info em_x270_spi_devices[] __initdata = { .modalias = "libertas_spi", .max_speed_hz = 13000000, .bus_num = 2, - .irq = IRQ_GPIO(116), + .irq = pxa_gpio_to_irq(116), .chip_select = 0, .controller_data = &em_x270_libertas_chip, .platform_data = &em_x270_libertas_pdata,
@@ -1203,7 +1203,7 @@ static struct da903x_platform_data em_x270_da9030_info = {static struct i2c_board_info em_x270_i2c_pmic_info = {I2C_BOARD_INFO ("da9030" ,0x49 ), - .irq =IRQ_GPIO (0 ), + .irq =pxa_gpio_to_irq (0 ), .platform_data = &em_x270_da9030_info, };
arch/arm/mach-pxa/eseries.c +2 -2
@@ -120,8 +120,8 @@ struct resource eseries_tmio_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = IRQ_GPIO(GPIO_ESERIES_TMIO_IRQ), - .end = IRQ_GPIO(GPIO_ESERIES_TMIO_IRQ), + .start = pxa_gpio_to_irq(GPIO_ESERIES_TMIO_IRQ), + .end = pxa_gpio_to_irq(GPIO_ESERIES_TMIO_IRQ), .flags = IORESOURCE_IRQ, }, };
arch/arm/mach-pxa/idp.c +2 -2
@@ -75,8 +75,8 @@ static struct resource smc91x_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = IRQ_GPIO(4), - .end = IRQ_GPIO(4), + .start = pxa_gpio_to_irq(4), + .end = pxa_gpio_to_irq(4), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, } };
arch/arm/mach-pxa/include/mach/balloon3.h +3 -3
@@ -172,9 +172,9 @@ enum balloon3_features {/* Balloon3 Interrupts */ #define BALLOON3_IRQ (x) (IRQ_BOARD_START + (x)) -#define BALLOON3_AUX_NIRQ IRQ_GPIO(BALLOON3_GPIO_AUX_NIRQ) -#define BALLOON3_CODEC_IRQ IRQ_GPIO(BALLOON3_GPIO_CODEC_IRQ) -#define BALLOON3_S0_CD_IRQ IRQ_GPIO(BALLOON3_GPIO_S0_CD) +#define BALLOON3_AUX_NIRQ pxa_gpio_to_irq(BALLOON3_GPIO_AUX_NIRQ) +#define BALLOON3_CODEC_IRQ pxa_gpio_to_irq(BALLOON3_GPIO_CODEC_IRQ) +#define BALLOON3_S0_CD_IRQ pxa_gpio_to_irq(BALLOON3_GPIO_S0_CD)#define BALLOON3_NR_IRQS (IRQ_BOARD_START + 16)
arch/arm/mach-pxa/include/mach/corgi.h +12 -12
@@ -66,18 +66,18 @@/* * Corgi Interrupts */ -#define CORGI_IRQ_GPIO_KEY_INT IRQ_GPIO(0) -#define CORGI_IRQ_GPIO_AC_IN IRQ_GPIO(1) -#define CORGI_IRQ_GPIO_WAKEUP IRQ_GPIO(3) -#define CORGI_IRQ_GPIO_AK_INT IRQ_GPIO(4) -#define CORGI_IRQ_GPIO_TP_INT IRQ_GPIO(5) -#define CORGI_IRQ_GPIO_nSD_DETECT IRQ_GPIO(9) -#define CORGI_IRQ_GPIO_nSD_INT IRQ_GPIO(10) -#define CORGI_IRQ_GPIO_MAIN_BAT_LOW IRQ_GPIO(11) -#define CORGI_IRQ_GPIO_CF_CD IRQ_GPIO(14) -#define CORGI_IRQ_GPIO_CHRG_FULL IRQ_GPIO(16)/* Battery fully charged */ -#define CORGI_IRQ_GPIO_CF_IRQ IRQ_GPIO(17) -#define CORGI_IRQ_GPIO_KEY_SENSE (a) IRQ_GPIO(58+(a))/* Keyboard Sense lines */ +#define CORGI_IRQ_GPIO_KEY_INT pxa_gpio_to_irq(0) +#define CORGI_IRQ_GPIO_AC_IN pxa_gpio_to_irq(1) +#define CORGI_IRQ_GPIO_WAKEUP pxa_gpio_to_irq(3) +#define CORGI_IRQ_GPIO_AK_INT pxa_gpio_to_irq(4) +#define CORGI_IRQ_GPIO_TP_INT pxa_gpio_to_irq(5) +#define CORGI_IRQ_GPIO_nSD_DETECT pxa_gpio_to_irq(9) +#define CORGI_IRQ_GPIO_nSD_INT pxa_gpio_to_irq(10) +#define CORGI_IRQ_GPIO_MAIN_BAT_LOW pxa_gpio_to_irq(11) +#define CORGI_IRQ_GPIO_CF_CD pxa_gpio_to_irq(14) +#define CORGI_IRQ_GPIO_CHRG_FULL pxa_gpio_to_irq(16)/* Battery fully charged */ +#define CORGI_IRQ_GPIO_CF_IRQ pxa_gpio_to_irq(17) +#define CORGI_IRQ_GPIO_KEY_SENSE (a) pxa_gpio_to_irq(58+(a))/* Keyboard Sense lines */ /*
arch/arm/mach-pxa/include/mach/gpio.h +0 -15
@@ -58,21 +58,6 @@#define NR_BUILTIN_GPIO PXA_GPIO_IRQ_NUM#define gpio_to_bank (gpio) ((gpio) >> 5) -#define pxa_gpio_to_irq (gpio) IRQ_GPIO(gpio) - -static inline int pxa_irq_to_gpio (unsigned int irq) -{ -int gpio; - -if (irq ==IRQ_GPIO0 || irq ==IRQ_GPIO1 ) -return irq -IRQ_GPIO0 ; - - gpio = irq -PXA_GPIO_IRQ_BASE ; -if (gpio >=2 && gpio <NR_BUILTIN_GPIO ) -return gpio; - -return -1 ; -}#ifdef CONFIG_CPU_PXA26x/* GPIO86/87/88/89 on PXA26x have their direction bits in GPDR2 inverted,
arch/arm/mach-pxa/include/mach/gumstix.h +10 -10
@@ -24,7 +24,7 @@ has detected a cable insertion; driven low otherwise. */#define GPIO_GUMSTIX_USB_GPIOx 41/* usb state change */ -#define GUMSTIX_USB_INTR_IRQ IRQ_GPIO(GPIO_GUMSTIX_USB_GPIOn) +#define GUMSTIX_USB_INTR_IRQ pxa_gpio_to_irq(GPIO_GUMSTIX_USB_GPIOn)#define GPIO_GUMSTIX_USB_GPIOn_MD (GPIO_GUMSTIX_USB_GPIOn | GPIO_IN)#define GPIO_GUMSTIX_USB_GPIOx_CON_MD (GPIO_GUMSTIX_USB_GPIOx | GPIO_OUT)
@@ -35,7 +35,7 @@ has detected a cable insertion; driven low otherwise. */*/ #define GUMSTIX_GPIO_nSD_WP 22/* SD Write Protect */ #define GUMSTIX_GPIO_nSD_DETECT 11/* MMC/SD Card Detect */ -#define GUMSTIX_IRQ_GPIO_nSD_DETECT IRQ_GPIO(GUMSTIX_GPIO_nSD_DETECT) +#define GUMSTIX_IRQ_GPIO_nSD_DETECT pxa_gpio_to_irq(GUMSTIX_GPIO_nSD_DETECT)/* * SMC Ethernet definitions
@@ -49,10 +49,10 @@ has detected a cable insertion; driven low otherwise. */#define GPIO_GUMSTIX_ETH0 36#define GPIO_GUMSTIX_ETH0_MD (GPIO_GUMSTIX_ETH0 | GPIO_IN) -#define GUMSTIX_ETH0_IRQ IRQ_GPIO(GPIO_GUMSTIX_ETH0) +#define GUMSTIX_ETH0_IRQ pxa_gpio_to_irq(GPIO_GUMSTIX_ETH0)#define GPIO_GUMSTIX_ETH1 27#define GPIO_GUMSTIX_ETH1_MD (GPIO_GUMSTIX_ETH1 | GPIO_IN) -#define GUMSTIX_ETH1_IRQ IRQ_GPIO(GPIO_GUMSTIX_ETH1) +#define GUMSTIX_ETH1_IRQ pxa_gpio_to_irq(GPIO_GUMSTIX_ETH1)/* CF reset line */
@@ -63,18 +63,18 @@ has detected a cable insertion; driven low otherwise. */#define GPIO4_nSTSCHG GPIO4_nBVD1#define GPIO11_nCD 11#define GPIO26_PRDY_nBSY 26 -#define GUMSTIX_S0_nSTSCHG_IRQ IRQ_GPIO(GPIO4_nSTSCHG) -#define GUMSTIX_S0_nCD_IRQ IRQ_GPIO(GPIO11_nCD) -#define GUMSTIX_S0_PRDY_nBSY_IRQ IRQ_GPIO(GPIO26_PRDY_nBSY) +#define GUMSTIX_S0_nSTSCHG_IRQ pxa_gpio_to_irq(GPIO4_nSTSCHG) +#define GUMSTIX_S0_nCD_IRQ pxa_gpio_to_irq(GPIO11_nCD) +#define GUMSTIX_S0_PRDY_nBSY_IRQ pxa_gpio_to_irq(GPIO26_PRDY_nBSY)/* CF slot 1 */ #define GPIO18_nBVD1 18#define GPIO18_nSTSCHG GPIO18_nBVD1#define GPIO36_nCD 36#define GPIO27_PRDY_nBSY 27 -#define GUMSTIX_S1_nSTSCHG_IRQ IRQ_GPIO(GPIO18_nSTSCHG) -#define GUMSTIX_S1_nCD_IRQ IRQ_GPIO(GPIO36_nCD) -#define GUMSTIX_S1_PRDY_nBSY_IRQ IRQ_GPIO(GPIO27_PRDY_nBSY) +#define GUMSTIX_S1_nSTSCHG_IRQ pxa_gpio_to_irq(GPIO18_nSTSCHG) +#define GUMSTIX_S1_nCD_IRQ pxa_gpio_to_irq(GPIO36_nCD) +#define GUMSTIX_S1_PRDY_nBSY_IRQ pxa_gpio_to_irq(GPIO27_PRDY_nBSY)/* CF GPIO line modes */ #define GPIO4_nSTSCHG_MD (GPIO4_nSTSCHG | GPIO_IN)
arch/arm/mach-pxa/include/mach/idp.h +7 -7
@@ -135,24 +135,24 @@/* A listing of interrupts used by external hardware devices */ -#define TOUCH_PANEL_IRQ IRQ_GPIO(5) -#define IDE_IRQ IRQ_GPIO(21) +#define TOUCH_PANEL_IRQ pxa_gpio_to_irq(5) +#define IDE_IRQ pxa_gpio_to_irq(21)#define TOUCH_PANEL_IRQ_EDGE IRQ_TYPE_EDGE_FALLING -#define ETHERNET_IRQ IRQ_GPIO(4) +#define ETHERNET_IRQ pxa_gpio_to_irq(4)#define ETHERNET_IRQ_EDGE IRQ_TYPE_EDGE_RISING#define IDE_IRQ_EDGE IRQ_TYPE_EDGE_RISING -#define PCMCIA_S0_CD_VALID IRQ_GPIO(7) +#define PCMCIA_S0_CD_VALID pxa_gpio_to_irq(7)#define PCMCIA_S0_CD_VALID_EDGE IRQ_TYPE_EDGE_BOTH -#define PCMCIA_S1_CD_VALID IRQ_GPIO(8) +#define PCMCIA_S1_CD_VALID pxa_gpio_to_irq(8)#define PCMCIA_S1_CD_VALID_EDGE IRQ_TYPE_EDGE_BOTH -#define PCMCIA_S0_RDYINT IRQ_GPIO(19) -#define PCMCIA_S1_RDYINT IRQ_GPIO(22) +#define PCMCIA_S0_RDYINT pxa_gpio_to_irq(19) +#define PCMCIA_S1_RDYINT pxa_gpio_to_irq(22)/*
arch/arm/mach-pxa/include/mach/irqs.h +2 -2
@@ -90,8 +90,8 @@#define PXA_GPIO_IRQ_BASE PXA_IRQ(96)#define PXA_GPIO_IRQ_NUM (192) -#define GPIO_2_x_TO_IRQ (x) (PXA_GPIO_IRQ_BASE + (x)) -#define IRQ_GPIO (x) (((x) < 2) ? (IRQ_GPIO0 + (x)) : GPIO_2_x_TO_IRQ(x)) +#define pxa_gpio_to_irq (gpio) (PXA_GPIO_IRQ_BASE + (gpio)) +#define pxa_irq_to_gpio (irq) ((irq) - PXA_GPIO_IRQ_BASE)/* * The following interrupts are for board specific purposes. Since
arch/arm/mach-pxa/include/mach/palmld.h +4 -4
@@ -68,10 +68,10 @@/* 20, 53 and 86 are usb related too */ /* INTERRUPTS */ -#define IRQ_GPIO_PALMLD_GPIO_RESET IRQ_GPIO(GPIO_NR_PALMLD_GPIO_RESET) -#define IRQ_GPIO_PALMLD_SD_DETECT_N IRQ_GPIO(GPIO_NR_PALMLD_SD_DETECT_N) -#define IRQ_GPIO_PALMLD_WM9712_IRQ IRQ_GPIO(GPIO_NR_PALMLD_WM9712_IRQ) -#define IRQ_GPIO_PALMLD_IDE_IRQ IRQ_GPIO(GPIO_NR_PALMLD_IDE_IRQ) +#define IRQ_GPIO_PALMLD_GPIO_RESET pxa_gpio_to_irq(GPIO_NR_PALMLD_GPIO_RESET) +#define IRQ_GPIO_PALMLD_SD_DETECT_N pxa_gpio_to_irq(GPIO_NR_PALMLD_SD_DETECT_N) +#define IRQ_GPIO_PALMLD_WM9712_IRQ pxa_gpio_to_irq(GPIO_NR_PALMLD_WM9712_IRQ) +#define IRQ_GPIO_PALMLD_IDE_IRQ pxa_gpio_to_irq(GPIO_NR_PALMLD_IDE_IRQ)/** HERE ARE INIT VALUES **/
arch/arm/mach-pxa/include/mach/palmt5.h +4 -4
@@ -48,10 +48,10 @@#define GPIO_NR_PALMT5_BT_RESET 83/* INTERRUPTS */ -#define IRQ_GPIO_PALMT5_SD_DETECT_N IRQ_GPIO(GPIO_NR_PALMT5_SD_DETECT_N) -#define IRQ_GPIO_PALMT5_WM9712_IRQ IRQ_GPIO(GPIO_NR_PALMT5_WM9712_IRQ) -#define IRQ_GPIO_PALMT5_USB_DETECT IRQ_GPIO(GPIO_NR_PALMT5_USB_DETECT) -#define IRQ_GPIO_PALMT5_GPIO_RESET IRQ_GPIO(GPIO_NR_PALMT5_GPIO_RESET) +#define IRQ_GPIO_PALMT5_SD_DETECT_N pxa_gpio_to_irq(GPIO_NR_PALMT5_SD_DETECT_N) +#define IRQ_GPIO_PALMT5_WM9712_IRQ pxa_gpio_to_irq(GPIO_NR_PALMT5_WM9712_IRQ) +#define IRQ_GPIO_PALMT5_USB_DETECT pxa_gpio_to_irq(GPIO_NR_PALMT5_USB_DETECT) +#define IRQ_GPIO_PALMT5_GPIO_RESET pxa_gpio_to_irq(GPIO_NR_PALMT5_GPIO_RESET)/** HERE ARE INIT VALUES **/
arch/arm/mach-pxa/include/mach/palmtc.h +2 -2
@@ -52,8 +52,8 @@#define GPIO_NR_PALMTC_IR_DISABLE 45/* IRQs */ -#define IRQ_GPIO_PALMTC_SD_DETECT_N IRQ_GPIO(GPIO_NR_PALMTC_SD_DETECT_N) -#define IRQ_GPIO_PALMTC_WLAN_READY IRQ_GPIO(GPIO_NR_PALMTC_WLAN_READY) +#define IRQ_GPIO_PALMTC_SD_DETECT_N pxa_gpio_to_irq(GPIO_NR_PALMTC_SD_DETECT_N) +#define IRQ_GPIO_PALMTC_WLAN_READY pxa_gpio_to_irq(GPIO_NR_PALMTC_WLAN_READY)/* UCB1400 GPIOs */ #define GPIO_NR_PALMTC_POWER_DETECT (0x80 | 0x00)
arch/arm/mach-pxa/include/mach/palmtx.h +4 -4
@@ -62,10 +62,10 @@#define GPIO_NR_PALMTX_NAND_BUFFER_DIR 79/* INTERRUPTS */ -#define IRQ_GPIO_PALMTX_SD_DETECT_N IRQ_GPIO(GPIO_NR_PALMTX_SD_DETECT_N) -#define IRQ_GPIO_PALMTX_WM9712_IRQ IRQ_GPIO(GPIO_NR_PALMTX_WM9712_IRQ) -#define IRQ_GPIO_PALMTX_USB_DETECT IRQ_GPIO(GPIO_NR_PALMTX_USB_DETECT) -#define IRQ_GPIO_PALMTX_GPIO_RESET IRQ_GPIO(GPIO_NR_PALMTX_GPIO_RESET) +#define IRQ_GPIO_PALMTX_SD_DETECT_N pxa_gpio_to_irq(GPIO_NR_PALMTX_SD_DETECT_N) +#define IRQ_GPIO_PALMTX_WM9712_IRQ pxa_gpio_to_irq(GPIO_NR_PALMTX_WM9712_IRQ) +#define IRQ_GPIO_PALMTX_USB_DETECT pxa_gpio_to_irq(GPIO_NR_PALMTX_USB_DETECT) +#define IRQ_GPIO_PALMTX_GPIO_RESET pxa_gpio_to_irq(GPIO_NR_PALMTX_GPIO_RESET)/** HERE ARE INIT VALUES **/
arch/arm/mach-pxa/include/mach/pcm027.h +4 -4
@@ -34,7 +34,7 @@/* I2C RTC */ #define PCM027_RTC_IRQ_GPIO 0 -#define PCM027_RTC_IRQ IRQ_GPIO(PCM027_RTC_IRQ_GPIO) +#define PCM027_RTC_IRQ pxa_gpio_to_irq(PCM027_RTC_IRQ_GPIO)#define PCM027_RTC_IRQ_EDGE IRQ_TYPE_EDGE_FALLING#define ADR_PCM027_RTC 0x51/* I2C address */
@@ -43,21 +43,21 @@/* Ethernet chip (SMSC91C111) */ #define PCM027_ETH_IRQ_GPIO 52 -#define PCM027_ETH_IRQ IRQ_GPIO(PCM027_ETH_IRQ_GPIO) +#define PCM027_ETH_IRQ pxa_gpio_to_irq(PCM027_ETH_IRQ_GPIO)#define PCM027_ETH_IRQ_EDGE IRQ_TYPE_EDGE_RISING#define PCM027_ETH_PHYS PXA_CS5_PHYS#define PCM027_ETH_SIZE (1*1024*1024)/* CAN controller SJA1000 (unsupported yet) */ #define PCM027_CAN_IRQ_GPIO 114 -#define PCM027_CAN_IRQ IRQ_GPIO(PCM027_CAN_IRQ_GPIO) +#define PCM027_CAN_IRQ pxa_gpio_to_irq(PCM027_CAN_IRQ_GPIO)#define PCM027_CAN_IRQ_EDGE IRQ_TYPE_EDGE_FALLING#define PCM027_CAN_PHYS 0x22000000#define PCM027_CAN_SIZE 0x100/* SPI GPIO expander (unsupported yet) */ #define PCM027_EGPIO_IRQ_GPIO 27 -#define PCM027_EGPIO_IRQ IRQ_GPIO(PCM027_EGPIO_IRQ_GPIO) +#define PCM027_EGPIO_IRQ pxa_gpio_to_irq(PCM027_EGPIO_IRQ_GPIO)#define PCM027_EGPIO_IRQ_EDGE IRQ_TYPE_EDGE_FALLING#define PCM027_EGPIO_CS 24/*
arch/arm/mach-pxa/include/mach/pcm990_baseboard.h +7 -7
@@ -28,14 +28,14 @@/* CPLD's interrupt controller is connected to PCM-027 GPIO 9 */ #define PCM990_CTRL_INT_IRQ_GPIO 9 -#define PCM990_CTRL_INT_IRQ IRQ_GPIO(PCM990_CTRL_INT_IRQ_GPIO) +#define PCM990_CTRL_INT_IRQ pxa_gpio_to_irq(PCM990_CTRL_INT_IRQ_GPIO)#define PCM990_CTRL_INT_IRQ_EDGE IRQ_TYPE_EDGE_RISING#define PCM990_CTRL_PHYS PXA_CS1_PHYS/* 16-Bit */ #define PCM990_CTRL_BASE 0xea000000#define PCM990_CTRL_SIZE (1*1024*1024)#define PCM990_CTRL_PWR_IRQ_GPIO 14 -#define PCM990_CTRL_PWR_IRQ IRQ_GPIO(PCM990_CTRL_PWR_IRQ_GPIO) +#define PCM990_CTRL_PWR_IRQ pxa_gpio_to_irq(PCM990_CTRL_PWR_IRQ_GPIO)#define PCM990_CTRL_PWR_IRQ_EDGE IRQ_TYPE_EDGE_RISING/* visible CPLD (U7) registers */
@@ -132,7 +132,7 @@* IDE */ #define PCM990_IDE_IRQ_GPIO 13 -#define PCM990_IDE_IRQ IRQ_GPIO(PCM990_IDE_IRQ_GPIO) +#define PCM990_IDE_IRQ pxa_gpio_to_irq(PCM990_IDE_IRQ_GPIO)#define PCM990_IDE_IRQ_EDGE IRQ_TYPE_EDGE_RISING#define PCM990_IDE_PLD_PHYS 0x20000000/* 16 bit wide */ #define PCM990_IDE_PLD_BASE 0xee000000
@@ -188,11 +188,11 @@* Compact Flash */ #define PCM990_CF_IRQ_GPIO 11 -#define PCM990_CF_IRQ IRQ_GPIO(PCM990_CF_IRQ_GPIO) +#define PCM990_CF_IRQ pxa_gpio_to_irq(PCM990_CF_IRQ_GPIO)#define PCM990_CF_IRQ_EDGE IRQ_TYPE_EDGE_RISING#define PCM990_CF_CD_GPIO 12 -#define PCM990_CF_CD IRQ_GPIO(PCM990_CF_CD_GPIO) +#define PCM990_CF_CD pxa_gpio_to_irq(PCM990_CF_CD_GPIO)#define PCM990_CF_CD_EDGE IRQ_TYPE_EDGE_RISING#define PCM990_CF_PLD_PHYS 0x30000000/* 16 bit wide */
@@ -258,14 +258,14 @@* Wolfson AC97 Touch */ #define PCM990_AC97_IRQ_GPIO 10 -#define PCM990_AC97_IRQ IRQ_GPIO(PCM990_AC97_IRQ_GPIO) +#define PCM990_AC97_IRQ pxa_gpio_to_irq(PCM990_AC97_IRQ_GPIO)#define PCM990_AC97_IRQ_EDGE IRQ_TYPE_EDGE_RISING/* * MMC phyCORE */ #define PCM990_MMC0_IRQ_GPIO 9 -#define PCM990_MMC0_IRQ IRQ_GPIO(PCM990_MMC0_IRQ_GPIO) +#define PCM990_MMC0_IRQ pxa_gpio_to_irq(PCM990_MMC0_IRQ_GPIO)#define PCM990_MMC0_IRQ_EDGE IRQ_TYPE_EDGE_FALLING/*
arch/arm/mach-pxa/include/mach/poodle.h +12 -12
@@ -47,18 +47,18 @@#define POODLE_GPIO_DISCHARGE_ON (42)/* Enable battery discharge */ /* PXA GPIOs */ -#define POODLE_IRQ_GPIO_ON_KEY IRQ_GPIO(0) -#define POODLE_IRQ_GPIO_AC_IN IRQ_GPIO(1) -#define POODLE_IRQ_GPIO_HP_IN IRQ_GPIO(4) -#define POODLE_IRQ_GPIO_CO IRQ_GPIO(16) -#define POODLE_IRQ_GPIO_TP_INT IRQ_GPIO(5) -#define POODLE_IRQ_GPIO_WAKEUP IRQ_GPIO(11) -#define POODLE_IRQ_GPIO_GA_INT IRQ_GPIO(10) -#define POODLE_IRQ_GPIO_CF_IRQ IRQ_GPIO(17) -#define POODLE_IRQ_GPIO_CF_CD IRQ_GPIO(14) -#define POODLE_IRQ_GPIO_nSD_INT IRQ_GPIO(8) -#define POODLE_IRQ_GPIO_nSD_DETECT IRQ_GPIO(9) -#define POODLE_IRQ_GPIO_MAIN_BAT_LOW IRQ_GPIO(13) +#define POODLE_IRQ_GPIO_ON_KEY pxa_gpio_to_irq(0) +#define POODLE_IRQ_GPIO_AC_IN pxa_gpio_to_irq(1) +#define POODLE_IRQ_GPIO_HP_IN pxa_gpio_to_irq(4) +#define POODLE_IRQ_GPIO_CO pxa_gpio_to_irq(16) +#define POODLE_IRQ_GPIO_TP_INT pxa_gpio_to_irq(5) +#define POODLE_IRQ_GPIO_WAKEUP pxa_gpio_to_irq(11) +#define POODLE_IRQ_GPIO_GA_INT pxa_gpio_to_irq(10) +#define POODLE_IRQ_GPIO_CF_IRQ pxa_gpio_to_irq(17) +#define POODLE_IRQ_GPIO_CF_CD pxa_gpio_to_irq(14) +#define POODLE_IRQ_GPIO_nSD_INT pxa_gpio_to_irq(8) +#define POODLE_IRQ_GPIO_nSD_DETECT pxa_gpio_to_irq(9) +#define POODLE_IRQ_GPIO_MAIN_BAT_LOW pxa_gpio_to_irq(13)/* SCOOP GPIOs */ #define POODLE_SCOOP_CHARGE_ON SCOOP_GPCR_PA11
arch/arm/mach-pxa/include/mach/spitz.h +17 -17
@@ -164,23 +164,23 @@/* Spitz IRQ Definitions */ -#define SPITZ_IRQ_GPIO_KEY_INT IRQ_GPIO(SPITZ_GPIO_KEY_INT) -#define SPITZ_IRQ_GPIO_AC_IN IRQ_GPIO(SPITZ_GPIO_AC_IN) -#define SPITZ_IRQ_GPIO_AK_INT IRQ_GPIO(SPITZ_GPIO_AK_INT) -#define SPITZ_IRQ_GPIO_HP_IN IRQ_GPIO(SPITZ_GPIO_HP_IN) -#define SPITZ_IRQ_GPIO_TP_INT IRQ_GPIO(SPITZ_GPIO_TP_INT) -#define SPITZ_IRQ_GPIO_SYNC IRQ_GPIO(SPITZ_GPIO_SYNC) -#define SPITZ_IRQ_GPIO_ON_KEY IRQ_GPIO(SPITZ_GPIO_ON_KEY) -#define SPITZ_IRQ_GPIO_SWA IRQ_GPIO(SPITZ_GPIO_SWA) -#define SPITZ_IRQ_GPIO_SWB IRQ_GPIO(SPITZ_GPIO_SWB) -#define SPITZ_IRQ_GPIO_BAT_COVER IRQ_GPIO(SPITZ_GPIO_BAT_COVER) -#define SPITZ_IRQ_GPIO_FATAL_BAT IRQ_GPIO(SPITZ_GPIO_FATAL_BAT) -#define SPITZ_IRQ_GPIO_CO IRQ_GPIO(SPITZ_GPIO_CO) -#define SPITZ_IRQ_GPIO_CF_IRQ IRQ_GPIO(SPITZ_GPIO_CF_IRQ) -#define SPITZ_IRQ_GPIO_CF_CD IRQ_GPIO(SPITZ_GPIO_CF_CD) -#define SPITZ_IRQ_GPIO_CF2_IRQ IRQ_GPIO(SPITZ_GPIO_CF2_IRQ) -#define SPITZ_IRQ_GPIO_nSD_INT IRQ_GPIO(SPITZ_GPIO_nSD_INT) -#define SPITZ_IRQ_GPIO_nSD_DETECT IRQ_GPIO(SPITZ_GPIO_nSD_DETECT) +#define SPITZ_IRQ_GPIO_KEY_INT pxa_gpio_to_irq(SPITZ_GPIO_KEY_INT) +#define SPITZ_IRQ_GPIO_AC_IN pxa_gpio_to_irq(SPITZ_GPIO_AC_IN) +#define SPITZ_IRQ_GPIO_AK_INT pxa_gpio_to_irq(SPITZ_GPIO_AK_INT) +#define SPITZ_IRQ_GPIO_HP_IN pxa_gpio_to_irq(SPITZ_GPIO_HP_IN) +#define SPITZ_IRQ_GPIO_TP_INT pxa_gpio_to_irq(SPITZ_GPIO_TP_INT) +#define SPITZ_IRQ_GPIO_SYNC pxa_gpio_to_irq(SPITZ_GPIO_SYNC) +#define SPITZ_IRQ_GPIO_ON_KEY pxa_gpio_to_irq(SPITZ_GPIO_ON_KEY) +#define SPITZ_IRQ_GPIO_SWA pxa_gpio_to_irq(SPITZ_GPIO_SWA) +#define SPITZ_IRQ_GPIO_SWB pxa_gpio_to_irq(SPITZ_GPIO_SWB) +#define SPITZ_IRQ_GPIO_BAT_COVER pxa_gpio_to_irq(SPITZ_GPIO_BAT_COVER) +#define SPITZ_IRQ_GPIO_FATAL_BAT pxa_gpio_to_irq(SPITZ_GPIO_FATAL_BAT) +#define SPITZ_IRQ_GPIO_CO pxa_gpio_to_irq(SPITZ_GPIO_CO) +#define SPITZ_IRQ_GPIO_CF_IRQ pxa_gpio_to_irq(SPITZ_GPIO_CF_IRQ) +#define SPITZ_IRQ_GPIO_CF_CD pxa_gpio_to_irq(SPITZ_GPIO_CF_CD) +#define SPITZ_IRQ_GPIO_CF2_IRQ pxa_gpio_to_irq(SPITZ_GPIO_CF2_IRQ) +#define SPITZ_IRQ_GPIO_nSD_INT pxa_gpio_to_irq(SPITZ_GPIO_nSD_INT) +#define SPITZ_IRQ_GPIO_nSD_DETECT pxa_gpio_to_irq(SPITZ_GPIO_nSD_DETECT)/* * Shared data structures
arch/arm/mach-pxa/include/mach/tosa.h +24 -24
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arch/arm/mach-pxa/include/mach/trizeps4.h +8 -8
@@ -43,30 +43,30 @@/* Ethernet Controller Davicom DM9000 */ #define GPIO_DM9000 101 -#define TRIZEPS4_ETH_IRQ IRQ_GPIO(GPIO_DM9000) +#define TRIZEPS4_ETH_IRQ pxa_gpio_to_irq(GPIO_DM9000)/* UCB1400 audio / TS-controller */ #define GPIO_UCB1400 1 -#define TRIZEPS4_UCB1400_IRQ IRQ_GPIO(GPIO_UCB1400) +#define TRIZEPS4_UCB1400_IRQ pxa_gpio_to_irq(GPIO_UCB1400)/* PCMCIA socket Compact Flash */ #define GPIO_PCD 11/* PCMCIA Card Detect */ -#define TRIZEPS4_CD_IRQ IRQ_GPIO(GPIO_PCD) +#define TRIZEPS4_CD_IRQ pxa_gpio_to_irq(GPIO_PCD)#define GPIO_PRDY 13/* READY / nINT */ -#define TRIZEPS4_READY_NINT IRQ_GPIO(GPIO_PRDY) +#define TRIZEPS4_READY_NINT pxa_gpio_to_irq(GPIO_PRDY)/* MMC socket */ #define GPIO_MMC_DET 12 -#define TRIZEPS4_MMC_IRQ IRQ_GPIO(GPIO_MMC_DET) +#define TRIZEPS4_MMC_IRQ pxa_gpio_to_irq(GPIO_MMC_DET)/* DOC NAND chip */ #define GPIO_DOC_LOCK 94#define GPIO_DOC_IRQ 93 -#define TRIZEPS4_DOC_IRQ IRQ_GPIO(GPIO_DOC_IRQ) +#define TRIZEPS4_DOC_IRQ pxa_gpio_to_irq(GPIO_DOC_IRQ)/* SPI interface */ #define GPIO_SPI 53 -#define TRIZEPS4_SPI_IRQ IRQ_GPIO(GPIO_SPI) +#define TRIZEPS4_SPI_IRQ pxa_gpio_to_irq(GPIO_SPI)/* LEDS using tx2 / rx2 */ #define GPIO_SYS_BUSY_LED 46
@@ -74,7 +74,7 @@/* Off-module PIC on ConXS board */ #define GPIO_PIC 0 -#define TRIZEPS4_PIC_IRQ IRQ_GPIO(GPIO_PIC) +#define TRIZEPS4_PIC_IRQ pxa_gpio_to_irq(GPIO_PIC)#ifdef CONFIG_MACH_TRIZEPS_CONXS /* for CONXS base board define these registers */
arch/arm/mach-pxa/irq.c +0 -61
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arch/arm/mach-pxa/littleton.c +2 -2
@@ -124,8 +124,8 @@ static struct resource smc91x_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO90)), - .end = IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO90)), + .start = pxa_gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO90)), + .end = pxa_gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO90)), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, } };
arch/arm/mach-pxa/lpd270.c +2 -2
@@ -152,8 +152,8 @@ static void __init lpd270_init_irq(void) handle_level_irq);set_irq_flags (irq,IRQF_VALID |IRQF_PROBE ); } -irq_set_chained_handler (IRQ_GPIO (0 ), lpd270_irq_handler); -irq_set_irq_type (IRQ_GPIO (0 ),IRQ_TYPE_EDGE_FALLING ); +irq_set_chained_handler (pxa_gpio_to_irq (0 ), lpd270_irq_handler); +irq_set_irq_type (pxa_gpio_to_irq (0 ),IRQ_TYPE_EDGE_FALLING ); }
arch/arm/mach-pxa/lubbock.c +2 -2
@@ -170,8 +170,8 @@ static void __init lubbock_init_irq(void)set_irq_flags (irq,IRQF_VALID |IRQF_PROBE ); } -irq_set_chained_handler (IRQ_GPIO (0 ), lubbock_irq_handler); -irq_set_irq_type (IRQ_GPIO (0 ),IRQ_TYPE_EDGE_FALLING ); +irq_set_chained_handler (pxa_gpio_to_irq (0 ), lubbock_irq_handler); +irq_set_irq_type (pxa_gpio_to_irq (0 ),IRQ_TYPE_EDGE_FALLING ); }#ifdef CONFIG_PM
arch/arm/mach-pxa/mainstone.c +2 -2
@@ -178,8 +178,8 @@ static void __init mainstone_init_irq(void)MST_INTMSKENA =0 ;MST_INTSETCLR =0 ; -irq_set_chained_handler (IRQ_GPIO (0 ), mainstone_irq_handler); -irq_set_irq_type (IRQ_GPIO (0 ),IRQ_TYPE_EDGE_FALLING ); +irq_set_chained_handler (pxa_gpio_to_irq (0 ), mainstone_irq_handler); +irq_set_irq_type (pxa_gpio_to_irq (0 ),IRQ_TYPE_EDGE_FALLING ); }#ifdef CONFIG_PM
arch/arm/mach-pxa/poodle.c +2 -2
@@ -166,8 +166,8 @@ static struct resource locomo_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = IRQ_GPIO(10), - .end = IRQ_GPIO(10), + .start = pxa_gpio_to_irq(10), + .end = pxa_gpio_to_irq(10), .flags = IORESOURCE_IRQ, }, };
arch/arm/mach-pxa/sharpsl_pm.c +12 -12
@@ -907,24 +907,24 @@ static int __devinit sharpsl_pm_probe(struct platform_device *pdev)gpio_direction_input (sharpsl_pm.machinfo->gpio_batlock);/* Register interrupt handlers */ -if (request_irq (IRQ_GPIO (sharpsl_pm.machinfo->gpio_acin), sharpsl_ac_isr,IRQF_DISABLED |IRQF_TRIGGER_RISING |IRQF_TRIGGER_FALLING ,"AC Input Detect" , sharpsl_ac_isr)) { -dev_err (sharpsl_pm.dev,"Could not get irq %d.\n" ,IRQ_GPIO (sharpsl_pm.machinfo->gpio_acin)); +if (request_irq (pxa_gpio_to_irq (sharpsl_pm.machinfo->gpio_acin), sharpsl_ac_isr,IRQF_DISABLED |IRQF_TRIGGER_RISING |IRQF_TRIGGER_FALLING ,"AC Input Detect" , sharpsl_ac_isr)) { +dev_err (sharpsl_pm.dev,"Could not get irq %d.\n" ,pxa_gpio_to_irq (sharpsl_pm.machinfo->gpio_acin)); } -if (request_irq (IRQ_GPIO (sharpsl_pm.machinfo->gpio_batlock), sharpsl_fatal_isr,IRQF_DISABLED |IRQF_TRIGGER_FALLING ,"Battery Cover" , sharpsl_fatal_isr)) { -dev_err (sharpsl_pm.dev,"Could not get irq %d.\n" ,IRQ_GPIO (sharpsl_pm.machinfo->gpio_batlock)); +if (request_irq (pxa_gpio_to_irq (sharpsl_pm.machinfo->gpio_batlock), sharpsl_fatal_isr,IRQF_DISABLED |IRQF_TRIGGER_FALLING ,"Battery Cover" , sharpsl_fatal_isr)) { +dev_err (sharpsl_pm.dev,"Could not get irq %d.\n" ,pxa_gpio_to_irq (sharpsl_pm.machinfo->gpio_batlock)); }if (sharpsl_pm.machinfo->gpio_fatal) { -if (request_irq (IRQ_GPIO (sharpsl_pm.machinfo->gpio_fatal), sharpsl_fatal_isr,IRQF_DISABLED |IRQF_TRIGGER_FALLING ,"Fatal Battery" , sharpsl_fatal_isr)) { -dev_err (sharpsl_pm.dev,"Could not get irq %d.\n" ,IRQ_GPIO (sharpsl_pm.machinfo->gpio_fatal)); +if (request_irq (pxa_gpio_to_irq (sharpsl_pm.machinfo->gpio_fatal), sharpsl_fatal_isr,IRQF_DISABLED |IRQF_TRIGGER_FALLING ,"Fatal Battery" , sharpsl_fatal_isr)) { +dev_err (sharpsl_pm.dev,"Could not get irq %d.\n" ,pxa_gpio_to_irq (sharpsl_pm.machinfo->gpio_fatal)); } }if (sharpsl_pm.machinfo->batfull_irq) {/* Register interrupt handler. */ -if (request_irq (IRQ_GPIO (sharpsl_pm.machinfo->gpio_batfull), sharpsl_chrg_full_isr,IRQF_DISABLED |IRQF_TRIGGER_RISING ,"CO" , sharpsl_chrg_full_isr)) { -dev_err (sharpsl_pm.dev,"Could not get irq %d.\n" ,IRQ_GPIO (sharpsl_pm.machinfo->gpio_batfull)); +if (request_irq (pxa_gpio_to_irq (sharpsl_pm.machinfo->gpio_batfull), sharpsl_chrg_full_isr,IRQF_DISABLED |IRQF_TRIGGER_RISING ,"CO" , sharpsl_chrg_full_isr)) { +dev_err (sharpsl_pm.dev,"Could not get irq %d.\n" ,pxa_gpio_to_irq (sharpsl_pm.machinfo->gpio_batfull)); } }
@@ -953,14 +953,14 @@ static int sharpsl_pm_remove(struct platform_device *pdev)led_trigger_unregister_simple (sharpsl_charge_led_trigger); -free_irq (IRQ_GPIO (sharpsl_pm.machinfo->gpio_acin), sharpsl_ac_isr); -free_irq (IRQ_GPIO (sharpsl_pm.machinfo->gpio_batlock), sharpsl_fatal_isr); +free_irq (pxa_gpio_to_irq (sharpsl_pm.machinfo->gpio_acin), sharpsl_ac_isr); +free_irq (pxa_gpio_to_irq (sharpsl_pm.machinfo->gpio_batlock), sharpsl_fatal_isr);if (sharpsl_pm.machinfo->gpio_fatal) -free_irq (IRQ_GPIO (sharpsl_pm.machinfo->gpio_fatal), sharpsl_fatal_isr); +free_irq (pxa_gpio_to_irq (sharpsl_pm.machinfo->gpio_fatal), sharpsl_fatal_isr);if (sharpsl_pm.machinfo->batfull_irq) -free_irq (IRQ_GPIO (sharpsl_pm.machinfo->gpio_batfull), sharpsl_chrg_full_isr); +free_irq (pxa_gpio_to_irq (sharpsl_pm.machinfo->gpio_batfull), sharpsl_chrg_full_isr);gpio_free (sharpsl_pm.machinfo->gpio_batlock);gpio_free (sharpsl_pm.machinfo->gpio_batfull);
arch/arm/mach-pxa/stargate2.c +11 -11
@@ -376,7 +376,7 @@ static struct spi_board_info spi_board_info[] __initdata = { .bus_num = 1, .chip_select = 0, .controller_data = &staccel_chip_info, - .irq = IRQ_GPIO(96), + .irq = pxa_gpio_to_irq(96), }, { .modalias = "cc2420", .max_speed_hz = 6500000,
@@ -560,18 +560,18 @@ static struct i2c_board_info __initdata imote2_i2c_board_info[] = {/* Through a nand gate - Also beware, on V2 sensor board the * pull up resistors are missing. */ - .irq = IRQ_GPIO(99), + .irq = pxa_gpio_to_irq(99), }, { /* ITS400 Sensor board only */ .type = "tsl2561", .addr = 0x49, /* Through a nand gate - Also beware, on V2 sensor board the * pull up resistors are missing. */ - .irq = IRQ_GPIO(99), + .irq = pxa_gpio_to_irq(99), }, { /* ITS400 Sensor board only */ .type = "tmp175", .addr = 0x4A, - .irq = IRQ_GPIO(96), + .irq = pxa_gpio_to_irq(96), }, { /* IMB400 Multimedia board */ .type = "wm8940", .addr = 0x1A,
@@ -661,8 +661,8 @@ static struct resource smc91x_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = IRQ_GPIO(40), - .end = IRQ_GPIO(40), + .start = pxa_gpio_to_irq(40), + .end = pxa_gpio_to_irq(40), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, } };
@@ -707,7 +707,7 @@ static int stargate2_mci_init(struct device *dev, }gpio_direction_input (SG2_GPIO_nSD_DETECT); - err = request_irq(IRQ_GPIO(SG2_GPIO_nSD_DETECT), + err = request_irq(pxa_gpio_to_irq(SG2_GPIO_nSD_DETECT), stargate2_detect_int, IRQ_TYPE_EDGE_BOTH, "MMC card detect",
@@ -738,7 +738,7 @@ static void stargate2_mci_setpower(struct device *dev, unsigned int vdd)static void stargate2_mci_exit (struct device *dev,void *data) { -free_irq (IRQ_GPIO (SG2_GPIO_nSD_DETECT), data); +free_irq (pxa_gpio_to_irq (SG2_GPIO_nSD_DETECT), data);gpio_free (SG2_SD_POWER_ENABLE );gpio_free (SG2_GPIO_nSD_DETECT); }
@@ -938,18 +938,18 @@ static struct i2c_board_info __initdata stargate2_i2c_board_info[] = {/* Through a nand gate - Also beware, on V2 sensor board the * pull up resistors are missing. */ - .irq = IRQ_GPIO(99), + .irq = pxa_gpio_to_irq(99), }, { /* ITS400 Sensor board only */ .type = "tsl2561", .addr = 0x49, /* Through a nand gate - Also beware, on V2 sensor board the * pull up resistors are missing. */ - .irq = IRQ_GPIO(99), + .irq = pxa_gpio_to_irq(99), }, { /* ITS400 Sensor board only */ .type = "tmp175", .addr = 0x4A, - .irq = IRQ_GPIO(96), + .irq = pxa_gpio_to_irq(96), }, };
arch/arm/mach-pxa/vpac270.c +3 -3
@@ -395,8 +395,8 @@ static struct resource vpac270_dm9000_resources[] = { .flags = IORESOURCE_MEM, }, [2] = { - .start = IRQ_GPIO(GPIO114_VPAC270_ETH_IRQ), - .end = IRQ_GPIO(GPIO114_VPAC270_ETH_IRQ), + .start = pxa_gpio_to_irq(GPIO114_VPAC270_ETH_IRQ), + .end = pxa_gpio_to_irq(GPIO114_VPAC270_ETH_IRQ), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, }, };
@@ -433,7 +433,7 @@ static pxa2xx_audio_ops_t vpac270_ac97_pdata = { };static struct ucb1400_pdata vpac270_ucb1400_pdata = { - .irq =IRQ_GPIO (GPIO113_VPAC270_TS_IRQ ), + .irq =pxa_gpio_to_irq (GPIO113_VPAC270_TS_IRQ ), };static struct platform_device vpac270_ucb1400_device = {
arch/arm/mach-pxa/zylonite_pxa300.c +2 -2
@@ -231,12 +231,12 @@ static struct i2c_board_info zylonite_i2c_board_info[] = { .type = "pca9539", .addr = 0x74, .platform_data = &gpio_exp[0], - .irq = IRQ_GPIO(18), + .irq = pxa_gpio_to_irq(18), }, { .type = "pca9539", .addr = 0x75, .platform_data = &gpio_exp[1], - .irq = IRQ_GPIO(19), + .irq = pxa_gpio_to_irq(19), }, };
arch/arm/plat-pxa/gpio.c +14 -0
@@ -282,6 +282,20 @@ void __init pxa_init_gpio(int mux_irq, int start, int end,__raw_writel (~0 ,c->regbase +GEDR_OFFSET ); } +#ifdef CONFIG_ARCH_PXA + irq =gpio_to_irq (0 ); +irq_set_chip_and_handler (irq, &pxa_muxed_gpio_chip, + handle_edge_irq); +set_irq_flags (irq,IRQF_VALID |IRQF_PROBE ); +irq_set_chained_handler (IRQ_GPIO0 , pxa_gpio_demux_handler); + + irq =gpio_to_irq (1 ); +irq_set_chip_and_handler (irq, &pxa_muxed_gpio_chip, + handle_edge_irq); +set_irq_flags (irq,IRQF_VALID |IRQF_PROBE ); +irq_set_chained_handler (IRQ_GPIO1 , pxa_gpio_demux_handler); +#endif +for (irq =pxa_gpio_to_irq (start); irq <=pxa_gpio_to_irq (end); irq++) { irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
Signature · 1 line
1.7.2.5
PATCH 4/5 ARM: pxa: use chained irq for GPIO0 and GPIO1
Quoted 7 lines · Haojian Zhuang
Change interrupt of GPIO0 and GPIO1 to chained interrupt. So irq chip of gpio could be removed from
irq.c. Sopxa_gpio_to_irq()could be simplified.Since
IRQ_GPIO()is similar topxa_gpio_to_irq(), removeIRQ_GPIO().Signed-off-by Haojian Zhuang <[email protected]>
On brief review, looks okay to me.
g.
Quoted 1,189 lines
--- arch/arm/mach-mmp/include/mach/gpio.h | 3 - arch/arm/mach-mmp/include/mach/irqs.h | 3 +- arch/arm/mach-mmp/ttc_dkb.c | 2 +- arch/arm/mach-pxa/am200epd.c | 4 +- arch/arm/mach-pxa/am300epd.c | 4 +- arch/arm/mach-pxa/balloon3.c | 2 +- arch/arm/mach-pxa/cm-x270.c | 2 +- arch/arm/mach-pxa/cm-x2xx.c | 4 +- arch/arm/mach-pxa/cm-x300.c | 6 +- arch/arm/mach-pxa/em-x270.c | 6 +- arch/arm/mach-pxa/eseries.c | 4 +- arch/arm/mach-pxa/idp.c | 4 +- arch/arm/mach-pxa/include/mach/balloon3.h | 6 +- arch/arm/mach-pxa/include/mach/corgi.h | 24 ++++---- arch/arm/mach-pxa/include/mach/gpio.h | 15 ----- arch/arm/mach-pxa/include/mach/gumstix.h | 20 ++++---- arch/arm/mach-pxa/include/mach/idp.h | 14 +++--- arch/arm/mach-pxa/include/mach/irqs.h | 4 +- arch/arm/mach-pxa/include/mach/palmld.h | 8 ++-- arch/arm/mach-pxa/include/mach/palmt5.h | 8 ++-- arch/arm/mach-pxa/include/mach/palmtc.h | 4 +- arch/arm/mach-pxa/include/mach/palmtx.h | 8 ++-- arch/arm/mach-pxa/include/mach/pcm027.h | 8 ++-- arch/arm/mach-pxa/include/mach/pcm990_baseboard.h | 14 +++--- arch/arm/mach-pxa/include/mach/poodle.h | 24 ++++---- arch/arm/mach-pxa/include/mach/spitz.h | 34 ++++++------ arch/arm/mach-pxa/include/mach/tosa.h | 46 ++++++++-------- arch/arm/mach-pxa/include/mach/trizeps4.h | 16 +++--- arch/arm/mach-pxa/irq.c | 61 --------------------- arch/arm/mach-pxa/littleton.c | 4 +- arch/arm/mach-pxa/lpd270.c | 4 +- arch/arm/mach-pxa/lubbock.c | 4 +- arch/arm/mach-pxa/mainstone.c | 4 +- arch/arm/mach-pxa/poodle.c | 4 +- arch/arm/mach-pxa/sharpsl_pm.c | 24 ++++---- arch/arm/mach-pxa/stargate2.c | 22 ++++---- arch/arm/mach-pxa/vpac270.c | 6 +- arch/arm/mach-pxa/zylonite_pxa300.c | 4 +- arch/arm/plat-pxa/gpio.c | 14 +++++ 39 files changed, 192 insertions(+), 256 deletions(-)arch/arm/mach-mmp/include/mach/gpio.h +0
-3@@ -13,9 +13,6 @@#define NR_BUILTIN_GPIO IRQ_GPIO_NUM#define gpio_to_bank (gpio) ((gpio) >> 5) -#define pxa_gpio_to_irq (gpio) (IRQ_GPIO_START + (gpio)) -#define pxa_irq_to_gpio (irq) ((irq) - IRQ_GPIO_START) -#define __gpio_is_inverted (gpio) (0)#define __gpio_is_occupied (gpio) (0)arch/arm/mach-mmp/include/mach/irqs.h +2
-1@@ -220,7 +220,8 @@#define IRQ_GPIO_START 128#define IRQ_GPIO_NUM 192 -#define IRQ_GPIO (x) (IRQ_GPIO_START + (x)) +#define pxa_gpio_to_irq (gpio) (IRQ_GPIO_START + (gpio)) +#define pxa_irq_to_gpio (irq) ((irq) - IRQ_GPIO_START)#define IRQ_BOARD_START (IRQ_GPIO_START + IRQ_GPIO_NUM)arch/arm/mach-mmp/ttc_dkb.c +1
-1@@ -136,7 +136,7 @@ static struct i2c_board_info ttc_dkb_i2c_info[] = { { .type = "max7312", .addr = 0x23, - .irq = IRQ_GPIO(80), + .irq = pxa_gpio_to_irq(80), .platform_data = &max7312_data, }, };arch/arm/mach-pxa/am200epd.c +2
-2@@ -138,7 +138,7 @@ static void am200_cleanup(struct metronomefb_par *par) {int i; -free_irq (IRQ_GPIO (RDY_GPIO_PIN ), par); +free_irq (pxa_gpio_to_irq (RDY_GPIO_PIN ), par);for (i =0 ; i <ARRAY_SIZE (gpios); i++)gpio_free (gpios[i]);@@ -292,7 +292,7 @@ static int am200_setup_irq(struct fb_info *info) {int ret; - ret =request_irq (IRQ_GPIO (RDY_GPIO_PIN ), am200_handle_irq, + ret =request_irq (pxa_gpio_to_irq (RDY_GPIO_PIN ), am200_handle_irq,IRQF_DISABLED |IRQF_TRIGGER_FALLING ,"AM200" , info->par);if (ret)arch/arm/mach-pxa/am300epd.c +2
-2@@ -176,7 +176,7 @@ static void am300_cleanup(struct broadsheetfb_par *par) {int i; -free_irq (IRQ_GPIO (RDY_GPIO_PIN ), par); +free_irq (pxa_gpio_to_irq (RDY_GPIO_PIN ), par);for (i =0 ; i <ARRAY_SIZE (gpios); i++)gpio_free (gpios[i]);@@ -240,7 +240,7 @@ static int am300_setup_irq(struct fb_info *info)int ret;struct broadsheetfb_par *par = info->par; - ret =request_irq (IRQ_GPIO (RDY_GPIO_PIN ), am300_handle_irq, + ret =request_irq (pxa_gpio_to_irq (RDY_GPIO_PIN ), am300_handle_irq,IRQF_DISABLED |IRQF_TRIGGER_RISING ,"AM300" , par);if (ret)arch/arm/mach-pxa/balloon3.c +1
-1@@ -179,7 +179,7 @@ static unsigned long balloon3_ac97_pin_config[] __initdata = { };static struct ucb1400_pdata vpac270_ucb1400_pdata = { - .irq =IRQ_GPIO (BALLOON3_GPIO_CODEC_IRQ ), + .irq =pxa_gpio_to_irq (BALLOON3_GPIO_CODEC_IRQ ), };arch/arm/mach-pxa/cm-x270.c +1
-1@@ -33,7 +33,7 @@/* GPIO IRQ usage */ #define GPIO83_MMC_IRQ (83) -#define CMX270_MMC_IRQ IRQ_GPIO(GPIO83_MMC_IRQ) +#define CMX270_MMC_IRQ pxa_gpio_to_irq(GPIO83_MMC_IRQ)/* MMC power enable */ #define GPIO105_MMC_POWER (105)arch/arm/mach-pxa/cm-x2xx.c +2
-2@@ -58,8 +58,8 @@ extern void cmx270_init(void);#define CMX255_GPIO_IT8152_IRQ (0)#define CMX270_GPIO_IT8152_IRQ (22) -#define CMX255_ETHIRQ IRQ_GPIO(GPIO22_ETHIRQ) -#define CMX270_ETHIRQ IRQ_GPIO(GPIO10_ETHIRQ) +#define CMX255_ETHIRQ pxa_gpio_to_irq(GPIO22_ETHIRQ) +#define CMX270_ETHIRQ pxa_gpio_to_irq(GPIO10_ETHIRQ)#if defined(CONFIG_DM9000 ) || defined(CONFIG_DM9000_MODULE ) static struct resource cmx255_dm9000_resource[] = {arch/arm/mach-pxa/cm-x300.c +3
-3@@ -64,7 +64,7 @@#define GPIO82_MMC_IRQ (82)#define GPIO85_MMC_WP (85) -#define CM_X300_MMC_IRQ IRQ_GPIO(GPIO82_MMC_IRQ) +#define CM_X300_MMC_IRQ pxa_gpio_to_irq(GPIO82_MMC_IRQ)#define GPIO95_RTC_CS (95)#define GPIO96_RTC_WR (96)@@ -229,8 +229,8 @@ static struct resource dm9000_resources[] = { .flags = IORESOURCE_MEM, }, [2] = { - .start = IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO99)), - .end = IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO99)), + .start = pxa_gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO99)), + .end = pxa_gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO99)), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, } };arch/arm/mach-pxa/em-x270.c +3
-3@@ -70,7 +70,7 @@/* common GPIOs */ #define GPIO11_NAND_CS (11)#define GPIO41_ETHIRQ (41) -#define EM_X270_ETHIRQ IRQ_GPIO(GPIO41_ETHIRQ) +#define EM_X270_ETHIRQ pxa_gpio_to_irq(GPIO41_ETHIRQ)#define GPIO115_WLAN_PWEN (115)#define GPIO19_WLAN_STRAP (19)#define GPIO9_USB_VBUS_EN (9)@@ -805,7 +805,7 @@ static struct spi_board_info em_x270_spi_devices[] __initdata = { .modalias = "libertas_spi", .max_speed_hz = 13000000, .bus_num = 2, - .irq = IRQ_GPIO(116), + .irq = pxa_gpio_to_irq(116), .chip_select = 0, .controller_data = &em_x270_libertas_chip, .platform_data = &em_x270_libertas_pdata,@@ -1203,7 +1203,7 @@ static struct da903x_platform_data em_x270_da9030_info = {static struct i2c_board_info em_x270_i2c_pmic_info = {I2C_BOARD_INFO ("da9030" ,0x49 ), - .irq =IRQ_GPIO (0 ), + .irq =pxa_gpio_to_irq (0 ), .platform_data = &em_x270_da9030_info, };arch/arm/mach-pxa/eseries.c +2
-2@@ -120,8 +120,8 @@ struct resource eseries_tmio_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = IRQ_GPIO(GPIO_ESERIES_TMIO_IRQ), - .end = IRQ_GPIO(GPIO_ESERIES_TMIO_IRQ), + .start = pxa_gpio_to_irq(GPIO_ESERIES_TMIO_IRQ), + .end = pxa_gpio_to_irq(GPIO_ESERIES_TMIO_IRQ), .flags = IORESOURCE_IRQ, }, };arch/arm/mach-pxa/idp.c +2
-2@@ -75,8 +75,8 @@ static struct resource smc91x_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = IRQ_GPIO(4), - .end = IRQ_GPIO(4), + .start = pxa_gpio_to_irq(4), + .end = pxa_gpio_to_irq(4), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, } };arch/arm/mach-pxa/include/mach/balloon3.h +3
-3@@ -172,9 +172,9 @@ enum balloon3_features {/* Balloon3 Interrupts */ #define BALLOON3_IRQ (x) (IRQ_BOARD_START + (x)) -#define BALLOON3_AUX_NIRQ IRQ_GPIO(BALLOON3_GPIO_AUX_NIRQ) -#define BALLOON3_CODEC_IRQ IRQ_GPIO(BALLOON3_GPIO_CODEC_IRQ) -#define BALLOON3_S0_CD_IRQ IRQ_GPIO(BALLOON3_GPIO_S0_CD) +#define BALLOON3_AUX_NIRQ pxa_gpio_to_irq(BALLOON3_GPIO_AUX_NIRQ) +#define BALLOON3_CODEC_IRQ pxa_gpio_to_irq(BALLOON3_GPIO_CODEC_IRQ) +#define BALLOON3_S0_CD_IRQ pxa_gpio_to_irq(BALLOON3_GPIO_S0_CD)#define BALLOON3_NR_IRQS (IRQ_BOARD_START + 16)arch/arm/mach-pxa/include/mach/corgi.h +12
-12@@ -66,18 +66,18 @@/* * Corgi Interrupts */ -#define CORGI_IRQ_GPIO_KEY_INT IRQ_GPIO(0) -#define CORGI_IRQ_GPIO_AC_IN IRQ_GPIO(1) -#define CORGI_IRQ_GPIO_WAKEUP IRQ_GPIO(3) -#define CORGI_IRQ_GPIO_AK_INT IRQ_GPIO(4) -#define CORGI_IRQ_GPIO_TP_INT IRQ_GPIO(5) -#define CORGI_IRQ_GPIO_nSD_DETECT IRQ_GPIO(9) -#define CORGI_IRQ_GPIO_nSD_INT IRQ_GPIO(10) -#define CORGI_IRQ_GPIO_MAIN_BAT_LOW IRQ_GPIO(11) -#define CORGI_IRQ_GPIO_CF_CD IRQ_GPIO(14) -#define CORGI_IRQ_GPIO_CHRG_FULL IRQ_GPIO(16)/* Battery fully charged */ -#define CORGI_IRQ_GPIO_CF_IRQ IRQ_GPIO(17) -#define CORGI_IRQ_GPIO_KEY_SENSE (a) IRQ_GPIO(58+(a))/* Keyboard Sense lines */ +#define CORGI_IRQ_GPIO_KEY_INT pxa_gpio_to_irq(0) +#define CORGI_IRQ_GPIO_AC_IN pxa_gpio_to_irq(1) +#define CORGI_IRQ_GPIO_WAKEUP pxa_gpio_to_irq(3) +#define CORGI_IRQ_GPIO_AK_INT pxa_gpio_to_irq(4) +#define CORGI_IRQ_GPIO_TP_INT pxa_gpio_to_irq(5) +#define CORGI_IRQ_GPIO_nSD_DETECT pxa_gpio_to_irq(9) +#define CORGI_IRQ_GPIO_nSD_INT pxa_gpio_to_irq(10) +#define CORGI_IRQ_GPIO_MAIN_BAT_LOW pxa_gpio_to_irq(11) +#define CORGI_IRQ_GPIO_CF_CD pxa_gpio_to_irq(14) +#define CORGI_IRQ_GPIO_CHRG_FULL pxa_gpio_to_irq(16)/* Battery fully charged */ +#define CORGI_IRQ_GPIO_CF_IRQ pxa_gpio_to_irq(17) +#define CORGI_IRQ_GPIO_KEY_SENSE (a) pxa_gpio_to_irq(58+(a))/* Keyboard Sense lines */ /* arch/arm/mach-pxa/include/mach/gpio.h +0
-15@@ -58,21 +58,6 @@#define NR_BUILTIN_GPIO PXA_GPIO_IRQ_NUM#define gpio_to_bank (gpio) ((gpio) >> 5) -#define pxa_gpio_to_irq (gpio) IRQ_GPIO(gpio) - -static inline int pxa_irq_to_gpio (unsigned int irq) -{ -int gpio; - -if (irq ==IRQ_GPIO0 || irq ==IRQ_GPIO1 ) -return irq -IRQ_GPIO0 ; - - gpio = irq -PXA_GPIO_IRQ_BASE ; -if (gpio >=2 && gpio <NR_BUILTIN_GPIO ) -return gpio; - -return -1 ; -}#ifdef CONFIG_CPU_PXA26x/* GPIO86/87/88/89 on PXA26x have their direction bits in GPDR2 inverted, arch/arm/mach-pxa/include/mach/gumstix.h +10
-10@@ -24,7 +24,7 @@ has detected a cable insertion; driven low otherwise. */#define GPIO_GUMSTIX_USB_GPIOx 41/* usb state change */ -#define GUMSTIX_USB_INTR_IRQ IRQ_GPIO(GPIO_GUMSTIX_USB_GPIOn) +#define GUMSTIX_USB_INTR_IRQ pxa_gpio_to_irq(GPIO_GUMSTIX_USB_GPIOn)#define GPIO_GUMSTIX_USB_GPIOn_MD (GPIO_GUMSTIX_USB_GPIOn | GPIO_IN)#define GPIO_GUMSTIX_USB_GPIOx_CON_MD (GPIO_GUMSTIX_USB_GPIOx | GPIO_OUT)@@ -35,7 +35,7 @@ has detected a cable insertion; driven low otherwise. */*/ #define GUMSTIX_GPIO_nSD_WP 22/* SD Write Protect */ #define GUMSTIX_GPIO_nSD_DETECT 11/* MMC/SD Card Detect */ -#define GUMSTIX_IRQ_GPIO_nSD_DETECT IRQ_GPIO(GUMSTIX_GPIO_nSD_DETECT) +#define GUMSTIX_IRQ_GPIO_nSD_DETECT pxa_gpio_to_irq(GUMSTIX_GPIO_nSD_DETECT)/* * SMC Ethernet definitions @@ -49,10 +49,10 @@ has detected a cable insertion; driven low otherwise. */#define GPIO_GUMSTIX_ETH0 36#define GPIO_GUMSTIX_ETH0_MD (GPIO_GUMSTIX_ETH0 | GPIO_IN) -#define GUMSTIX_ETH0_IRQ IRQ_GPIO(GPIO_GUMSTIX_ETH0) +#define GUMSTIX_ETH0_IRQ pxa_gpio_to_irq(GPIO_GUMSTIX_ETH0)#define GPIO_GUMSTIX_ETH1 27#define GPIO_GUMSTIX_ETH1_MD (GPIO_GUMSTIX_ETH1 | GPIO_IN) -#define GUMSTIX_ETH1_IRQ IRQ_GPIO(GPIO_GUMSTIX_ETH1) +#define GUMSTIX_ETH1_IRQ pxa_gpio_to_irq(GPIO_GUMSTIX_ETH1)/* CF reset line */ @@ -63,18 +63,18 @@ has detected a cable insertion; driven low otherwise. */#define GPIO4_nSTSCHG GPIO4_nBVD1#define GPIO11_nCD 11#define GPIO26_PRDY_nBSY 26 -#define GUMSTIX_S0_nSTSCHG_IRQ IRQ_GPIO(GPIO4_nSTSCHG) -#define GUMSTIX_S0_nCD_IRQ IRQ_GPIO(GPIO11_nCD) -#define GUMSTIX_S0_PRDY_nBSY_IRQ IRQ_GPIO(GPIO26_PRDY_nBSY) +#define GUMSTIX_S0_nSTSCHG_IRQ pxa_gpio_to_irq(GPIO4_nSTSCHG) +#define GUMSTIX_S0_nCD_IRQ pxa_gpio_to_irq(GPIO11_nCD) +#define GUMSTIX_S0_PRDY_nBSY_IRQ pxa_gpio_to_irq(GPIO26_PRDY_nBSY)/* CF slot 1 */ #define GPIO18_nBVD1 18#define GPIO18_nSTSCHG GPIO18_nBVD1#define GPIO36_nCD 36#define GPIO27_PRDY_nBSY 27 -#define GUMSTIX_S1_nSTSCHG_IRQ IRQ_GPIO(GPIO18_nSTSCHG) -#define GUMSTIX_S1_nCD_IRQ IRQ_GPIO(GPIO36_nCD) -#define GUMSTIX_S1_PRDY_nBSY_IRQ IRQ_GPIO(GPIO27_PRDY_nBSY) +#define GUMSTIX_S1_nSTSCHG_IRQ pxa_gpio_to_irq(GPIO18_nSTSCHG) +#define GUMSTIX_S1_nCD_IRQ pxa_gpio_to_irq(GPIO36_nCD) +#define GUMSTIX_S1_PRDY_nBSY_IRQ pxa_gpio_to_irq(GPIO27_PRDY_nBSY)/* CF GPIO line modes */ #define GPIO4_nSTSCHG_MD (GPIO4_nSTSCHG | GPIO_IN)arch/arm/mach-pxa/include/mach/idp.h +7
-7@@ -135,24 +135,24 @@/* A listing of interrupts used by external hardware devices */ -#define TOUCH_PANEL_IRQ IRQ_GPIO(5) -#define IDE_IRQ IRQ_GPIO(21) +#define TOUCH_PANEL_IRQ pxa_gpio_to_irq(5) +#define IDE_IRQ pxa_gpio_to_irq(21)#define TOUCH_PANEL_IRQ_EDGE IRQ_TYPE_EDGE_FALLING -#define ETHERNET_IRQ IRQ_GPIO(4) +#define ETHERNET_IRQ pxa_gpio_to_irq(4)#define ETHERNET_IRQ_EDGE IRQ_TYPE_EDGE_RISING#define IDE_IRQ_EDGE IRQ_TYPE_EDGE_RISING -#define PCMCIA_S0_CD_VALID IRQ_GPIO(7) +#define PCMCIA_S0_CD_VALID pxa_gpio_to_irq(7)#define PCMCIA_S0_CD_VALID_EDGE IRQ_TYPE_EDGE_BOTH -#define PCMCIA_S1_CD_VALID IRQ_GPIO(8) +#define PCMCIA_S1_CD_VALID pxa_gpio_to_irq(8)#define PCMCIA_S1_CD_VALID_EDGE IRQ_TYPE_EDGE_BOTH -#define PCMCIA_S0_RDYINT IRQ_GPIO(19) -#define PCMCIA_S1_RDYINT IRQ_GPIO(22) +#define PCMCIA_S0_RDYINT pxa_gpio_to_irq(19) +#define PCMCIA_S1_RDYINT pxa_gpio_to_irq(22)/* arch/arm/mach-pxa/include/mach/irqs.h +2
-2@@ -90,8 +90,8 @@#define PXA_GPIO_IRQ_BASE PXA_IRQ(96)#define PXA_GPIO_IRQ_NUM (192) -#define GPIO_2_x_TO_IRQ (x) (PXA_GPIO_IRQ_BASE + (x)) -#define IRQ_GPIO (x) (((x) < 2) ? (IRQ_GPIO0 + (x)) : GPIO_2_x_TO_IRQ(x)) +#define pxa_gpio_to_irq (gpio) (PXA_GPIO_IRQ_BASE + (gpio)) +#define pxa_irq_to_gpio (irq) ((irq) - PXA_GPIO_IRQ_BASE)/* * The following interrupts are for board specific purposes. Since arch/arm/mach-pxa/include/mach/palmld.h +4
-4@@ -68,10 +68,10 @@/* 20, 53 and 86 are usb related too */ /* INTERRUPTS */ -#define IRQ_GPIO_PALMLD_GPIO_RESET IRQ_GPIO(GPIO_NR_PALMLD_GPIO_RESET) -#define IRQ_GPIO_PALMLD_SD_DETECT_N IRQ_GPIO(GPIO_NR_PALMLD_SD_DETECT_N) -#define IRQ_GPIO_PALMLD_WM9712_IRQ IRQ_GPIO(GPIO_NR_PALMLD_WM9712_IRQ) -#define IRQ_GPIO_PALMLD_IDE_IRQ IRQ_GPIO(GPIO_NR_PALMLD_IDE_IRQ) +#define IRQ_GPIO_PALMLD_GPIO_RESET pxa_gpio_to_irq(GPIO_NR_PALMLD_GPIO_RESET) +#define IRQ_GPIO_PALMLD_SD_DETECT_N pxa_gpio_to_irq(GPIO_NR_PALMLD_SD_DETECT_N) +#define IRQ_GPIO_PALMLD_WM9712_IRQ pxa_gpio_to_irq(GPIO_NR_PALMLD_WM9712_IRQ) +#define IRQ_GPIO_PALMLD_IDE_IRQ pxa_gpio_to_irq(GPIO_NR_PALMLD_IDE_IRQ)/** HERE ARE INIT VALUES **/ arch/arm/mach-pxa/include/mach/palmt5.h +4
-4@@ -48,10 +48,10 @@#define GPIO_NR_PALMT5_BT_RESET 83/* INTERRUPTS */ -#define IRQ_GPIO_PALMT5_SD_DETECT_N IRQ_GPIO(GPIO_NR_PALMT5_SD_DETECT_N) -#define IRQ_GPIO_PALMT5_WM9712_IRQ IRQ_GPIO(GPIO_NR_PALMT5_WM9712_IRQ) -#define IRQ_GPIO_PALMT5_USB_DETECT IRQ_GPIO(GPIO_NR_PALMT5_USB_DETECT) -#define IRQ_GPIO_PALMT5_GPIO_RESET IRQ_GPIO(GPIO_NR_PALMT5_GPIO_RESET) +#define IRQ_GPIO_PALMT5_SD_DETECT_N pxa_gpio_to_irq(GPIO_NR_PALMT5_SD_DETECT_N) +#define IRQ_GPIO_PALMT5_WM9712_IRQ pxa_gpio_to_irq(GPIO_NR_PALMT5_WM9712_IRQ) +#define IRQ_GPIO_PALMT5_USB_DETECT pxa_gpio_to_irq(GPIO_NR_PALMT5_USB_DETECT) +#define IRQ_GPIO_PALMT5_GPIO_RESET pxa_gpio_to_irq(GPIO_NR_PALMT5_GPIO_RESET)/** HERE ARE INIT VALUES **/ arch/arm/mach-pxa/include/mach/palmtc.h +2
-2@@ -52,8 +52,8 @@#define GPIO_NR_PALMTC_IR_DISABLE 45/* IRQs */ -#define IRQ_GPIO_PALMTC_SD_DETECT_N IRQ_GPIO(GPIO_NR_PALMTC_SD_DETECT_N) -#define IRQ_GPIO_PALMTC_WLAN_READY IRQ_GPIO(GPIO_NR_PALMTC_WLAN_READY) +#define IRQ_GPIO_PALMTC_SD_DETECT_N pxa_gpio_to_irq(GPIO_NR_PALMTC_SD_DETECT_N) +#define IRQ_GPIO_PALMTC_WLAN_READY pxa_gpio_to_irq(GPIO_NR_PALMTC_WLAN_READY)/* UCB1400 GPIOs */ #define GPIO_NR_PALMTC_POWER_DETECT (0x80 | 0x00)arch/arm/mach-pxa/include/mach/palmtx.h +4
-4@@ -62,10 +62,10 @@#define GPIO_NR_PALMTX_NAND_BUFFER_DIR 79/* INTERRUPTS */ -#define IRQ_GPIO_PALMTX_SD_DETECT_N IRQ_GPIO(GPIO_NR_PALMTX_SD_DETECT_N) -#define IRQ_GPIO_PALMTX_WM9712_IRQ IRQ_GPIO(GPIO_NR_PALMTX_WM9712_IRQ) -#define IRQ_GPIO_PALMTX_USB_DETECT IRQ_GPIO(GPIO_NR_PALMTX_USB_DETECT) -#define IRQ_GPIO_PALMTX_GPIO_RESET IRQ_GPIO(GPIO_NR_PALMTX_GPIO_RESET) +#define IRQ_GPIO_PALMTX_SD_DETECT_N pxa_gpio_to_irq(GPIO_NR_PALMTX_SD_DETECT_N) +#define IRQ_GPIO_PALMTX_WM9712_IRQ pxa_gpio_to_irq(GPIO_NR_PALMTX_WM9712_IRQ) +#define IRQ_GPIO_PALMTX_USB_DETECT pxa_gpio_to_irq(GPIO_NR_PALMTX_USB_DETECT) +#define IRQ_GPIO_PALMTX_GPIO_RESET pxa_gpio_to_irq(GPIO_NR_PALMTX_GPIO_RESET)/** HERE ARE INIT VALUES **/ arch/arm/mach-pxa/include/mach/pcm027.h +4
-4@@ -34,7 +34,7 @@/* I2C RTC */ #define PCM027_RTC_IRQ_GPIO 0 -#define PCM027_RTC_IRQ IRQ_GPIO(PCM027_RTC_IRQ_GPIO) +#define PCM027_RTC_IRQ pxa_gpio_to_irq(PCM027_RTC_IRQ_GPIO)#define PCM027_RTC_IRQ_EDGE IRQ_TYPE_EDGE_FALLING#define ADR_PCM027_RTC 0x51/* I2C address */ @@ -43,21 +43,21 @@/* Ethernet chip (SMSC91C111) */ #define PCM027_ETH_IRQ_GPIO 52 -#define PCM027_ETH_IRQ IRQ_GPIO(PCM027_ETH_IRQ_GPIO) +#define PCM027_ETH_IRQ pxa_gpio_to_irq(PCM027_ETH_IRQ_GPIO)#define PCM027_ETH_IRQ_EDGE IRQ_TYPE_EDGE_RISING#define PCM027_ETH_PHYS PXA_CS5_PHYS#define PCM027_ETH_SIZE (1*1024*1024)/* CAN controller SJA1000 (unsupported yet) */ #define PCM027_CAN_IRQ_GPIO 114 -#define PCM027_CAN_IRQ IRQ_GPIO(PCM027_CAN_IRQ_GPIO) +#define PCM027_CAN_IRQ pxa_gpio_to_irq(PCM027_CAN_IRQ_GPIO)#define PCM027_CAN_IRQ_EDGE IRQ_TYPE_EDGE_FALLING#define PCM027_CAN_PHYS 0x22000000#define PCM027_CAN_SIZE 0x100/* SPI GPIO expander (unsupported yet) */ #define PCM027_EGPIO_IRQ_GPIO 27 -#define PCM027_EGPIO_IRQ IRQ_GPIO(PCM027_EGPIO_IRQ_GPIO) +#define PCM027_EGPIO_IRQ pxa_gpio_to_irq(PCM027_EGPIO_IRQ_GPIO)#define PCM027_EGPIO_IRQ_EDGE IRQ_TYPE_EDGE_FALLING#define PCM027_EGPIO_CS 24/* arch/arm/mach-pxa/include/mach/pcm990_baseboard.h +7
-7@@ -28,14 +28,14 @@/* CPLD's interrupt controller is connected to PCM-027 GPIO 9 */ #define PCM990_CTRL_INT_IRQ_GPIO 9 -#define PCM990_CTRL_INT_IRQ IRQ_GPIO(PCM990_CTRL_INT_IRQ_GPIO) +#define PCM990_CTRL_INT_IRQ pxa_gpio_to_irq(PCM990_CTRL_INT_IRQ_GPIO)#define PCM990_CTRL_INT_IRQ_EDGE IRQ_TYPE_EDGE_RISING#define PCM990_CTRL_PHYS PXA_CS1_PHYS/* 16-Bit */ #define PCM990_CTRL_BASE 0xea000000#define PCM990_CTRL_SIZE (1*1024*1024)#define PCM990_CTRL_PWR_IRQ_GPIO 14 -#define PCM990_CTRL_PWR_IRQ IRQ_GPIO(PCM990_CTRL_PWR_IRQ_GPIO) +#define PCM990_CTRL_PWR_IRQ pxa_gpio_to_irq(PCM990_CTRL_PWR_IRQ_GPIO)#define PCM990_CTRL_PWR_IRQ_EDGE IRQ_TYPE_EDGE_RISING/* visible CPLD (U7) registers */ @@ -132,7 +132,7 @@* IDE */ #define PCM990_IDE_IRQ_GPIO 13 -#define PCM990_IDE_IRQ IRQ_GPIO(PCM990_IDE_IRQ_GPIO) +#define PCM990_IDE_IRQ pxa_gpio_to_irq(PCM990_IDE_IRQ_GPIO)#define PCM990_IDE_IRQ_EDGE IRQ_TYPE_EDGE_RISING#define PCM990_IDE_PLD_PHYS 0x20000000/* 16 bit wide */ #define PCM990_IDE_PLD_BASE 0xee000000@@ -188,11 +188,11 @@* Compact Flash */ #define PCM990_CF_IRQ_GPIO 11 -#define PCM990_CF_IRQ IRQ_GPIO(PCM990_CF_IRQ_GPIO) +#define PCM990_CF_IRQ pxa_gpio_to_irq(PCM990_CF_IRQ_GPIO)#define PCM990_CF_IRQ_EDGE IRQ_TYPE_EDGE_RISING#define PCM990_CF_CD_GPIO 12 -#define PCM990_CF_CD IRQ_GPIO(PCM990_CF_CD_GPIO) +#define PCM990_CF_CD pxa_gpio_to_irq(PCM990_CF_CD_GPIO)#define PCM990_CF_CD_EDGE IRQ_TYPE_EDGE_RISING#define PCM990_CF_PLD_PHYS 0x30000000/* 16 bit wide */ @@ -258,14 +258,14 @@* Wolfson AC97 Touch */ #define PCM990_AC97_IRQ_GPIO 10 -#define PCM990_AC97_IRQ IRQ_GPIO(PCM990_AC97_IRQ_GPIO) +#define PCM990_AC97_IRQ pxa_gpio_to_irq(PCM990_AC97_IRQ_GPIO)#define PCM990_AC97_IRQ_EDGE IRQ_TYPE_EDGE_RISING/* * MMC phyCORE */ #define PCM990_MMC0_IRQ_GPIO 9 -#define PCM990_MMC0_IRQ IRQ_GPIO(PCM990_MMC0_IRQ_GPIO) +#define PCM990_MMC0_IRQ pxa_gpio_to_irq(PCM990_MMC0_IRQ_GPIO)#define PCM990_MMC0_IRQ_EDGE IRQ_TYPE_EDGE_FALLING/* arch/arm/mach-pxa/include/mach/poodle.h +12
-12@@ -47,18 +47,18 @@#define POODLE_GPIO_DISCHARGE_ON (42)/* Enable battery discharge */ /* PXA GPIOs */ -#define POODLE_IRQ_GPIO_ON_KEY IRQ_GPIO(0) -#define POODLE_IRQ_GPIO_AC_IN IRQ_GPIO(1) -#define POODLE_IRQ_GPIO_HP_IN IRQ_GPIO(4) -#define POODLE_IRQ_GPIO_CO IRQ_GPIO(16) -#define POODLE_IRQ_GPIO_TP_INT IRQ_GPIO(5) -#define POODLE_IRQ_GPIO_WAKEUP IRQ_GPIO(11) -#define POODLE_IRQ_GPIO_GA_INT IRQ_GPIO(10) -#define POODLE_IRQ_GPIO_CF_IRQ IRQ_GPIO(17) -#define POODLE_IRQ_GPIO_CF_CD IRQ_GPIO(14) -#define POODLE_IRQ_GPIO_nSD_INT IRQ_GPIO(8) -#define POODLE_IRQ_GPIO_nSD_DETECT IRQ_GPIO(9) -#define POODLE_IRQ_GPIO_MAIN_BAT_LOW IRQ_GPIO(13) +#define POODLE_IRQ_GPIO_ON_KEY pxa_gpio_to_irq(0) +#define POODLE_IRQ_GPIO_AC_IN pxa_gpio_to_irq(1) +#define POODLE_IRQ_GPIO_HP_IN pxa_gpio_to_irq(4) +#define POODLE_IRQ_GPIO_CO pxa_gpio_to_irq(16) +#define POODLE_IRQ_GPIO_TP_INT pxa_gpio_to_irq(5) +#define POODLE_IRQ_GPIO_WAKEUP pxa_gpio_to_irq(11) +#define POODLE_IRQ_GPIO_GA_INT pxa_gpio_to_irq(10) +#define POODLE_IRQ_GPIO_CF_IRQ pxa_gpio_to_irq(17) +#define POODLE_IRQ_GPIO_CF_CD pxa_gpio_to_irq(14) +#define POODLE_IRQ_GPIO_nSD_INT pxa_gpio_to_irq(8) +#define POODLE_IRQ_GPIO_nSD_DETECT pxa_gpio_to_irq(9) +#define POODLE_IRQ_GPIO_MAIN_BAT_LOW pxa_gpio_to_irq(13)/* SCOOP GPIOs */ #define POODLE_SCOOP_CHARGE_ON SCOOP_GPCR_PA11arch/arm/mach-pxa/include/mach/spitz.h +17
-17@@ -164,23 +164,23 @@/* Spitz IRQ Definitions */ -#define SPITZ_IRQ_GPIO_KEY_INT IRQ_GPIO(SPITZ_GPIO_KEY_INT) -#define SPITZ_IRQ_GPIO_AC_IN IRQ_GPIO(SPITZ_GPIO_AC_IN) -#define SPITZ_IRQ_GPIO_AK_INT IRQ_GPIO(SPITZ_GPIO_AK_INT) -#define SPITZ_IRQ_GPIO_HP_IN IRQ_GPIO(SPITZ_GPIO_HP_IN) -#define SPITZ_IRQ_GPIO_TP_INT IRQ_GPIO(SPITZ_GPIO_TP_INT) -#define SPITZ_IRQ_GPIO_SYNC IRQ_GPIO(SPITZ_GPIO_SYNC) -#define SPITZ_IRQ_GPIO_ON_KEY IRQ_GPIO(SPITZ_GPIO_ON_KEY) -#define SPITZ_IRQ_GPIO_SWA IRQ_GPIO(SPITZ_GPIO_SWA) -#define SPITZ_IRQ_GPIO_SWB IRQ_GPIO(SPITZ_GPIO_SWB) -#define SPITZ_IRQ_GPIO_BAT_COVER IRQ_GPIO(SPITZ_GPIO_BAT_COVER) -#define SPITZ_IRQ_GPIO_FATAL_BAT IRQ_GPIO(SPITZ_GPIO_FATAL_BAT) -#define SPITZ_IRQ_GPIO_CO IRQ_GPIO(SPITZ_GPIO_CO) -#define SPITZ_IRQ_GPIO_CF_IRQ IRQ_GPIO(SPITZ_GPIO_CF_IRQ) -#define SPITZ_IRQ_GPIO_CF_CD IRQ_GPIO(SPITZ_GPIO_CF_CD) -#define SPITZ_IRQ_GPIO_CF2_IRQ IRQ_GPIO(SPITZ_GPIO_CF2_IRQ) -#define SPITZ_IRQ_GPIO_nSD_INT IRQ_GPIO(SPITZ_GPIO_nSD_INT) -#define SPITZ_IRQ_GPIO_nSD_DETECT IRQ_GPIO(SPITZ_GPIO_nSD_DETECT) +#define SPITZ_IRQ_GPIO_KEY_INT pxa_gpio_to_irq(SPITZ_GPIO_KEY_INT) +#define SPITZ_IRQ_GPIO_AC_IN pxa_gpio_to_irq(SPITZ_GPIO_AC_IN) +#define SPITZ_IRQ_GPIO_AK_INT pxa_gpio_to_irq(SPITZ_GPIO_AK_INT) +#define SPITZ_IRQ_GPIO_HP_IN pxa_gpio_to_irq(SPITZ_GPIO_HP_IN) +#define SPITZ_IRQ_GPIO_TP_INT pxa_gpio_to_irq(SPITZ_GPIO_TP_INT) +#define SPITZ_IRQ_GPIO_SYNC pxa_gpio_to_irq(SPITZ_GPIO_SYNC) +#define SPITZ_IRQ_GPIO_ON_KEY pxa_gpio_to_irq(SPITZ_GPIO_ON_KEY) +#define SPITZ_IRQ_GPIO_SWA pxa_gpio_to_irq(SPITZ_GPIO_SWA) +#define SPITZ_IRQ_GPIO_SWB pxa_gpio_to_irq(SPITZ_GPIO_SWB) +#define SPITZ_IRQ_GPIO_BAT_COVER pxa_gpio_to_irq(SPITZ_GPIO_BAT_COVER) +#define SPITZ_IRQ_GPIO_FATAL_BAT pxa_gpio_to_irq(SPITZ_GPIO_FATAL_BAT) +#define SPITZ_IRQ_GPIO_CO pxa_gpio_to_irq(SPITZ_GPIO_CO) +#define SPITZ_IRQ_GPIO_CF_IRQ pxa_gpio_to_irq(SPITZ_GPIO_CF_IRQ) +#define SPITZ_IRQ_GPIO_CF_CD pxa_gpio_to_irq(SPITZ_GPIO_CF_CD) +#define SPITZ_IRQ_GPIO_CF2_IRQ pxa_gpio_to_irq(SPITZ_GPIO_CF2_IRQ) +#define SPITZ_IRQ_GPIO_nSD_INT pxa_gpio_to_irq(SPITZ_GPIO_nSD_INT) +#define SPITZ_IRQ_GPIO_nSD_DETECT pxa_gpio_to_irq(SPITZ_GPIO_nSD_DETECT)/* * Shared data structures arch/arm/mach-pxa/include/mach/tosa.h +24
-24@@ -141,30 +141,30 @@/* * Interrupts */ -#define TOSA_IRQ_GPIO_WAKEUP IRQ_GPIO(TOSA_GPIO_WAKEUP) -#define TOSA_IRQ_GPIO_AC_IN IRQ_GPIO(TOSA_GPIO_AC_IN) -#define TOSA_IRQ_GPIO_RECORD_BTN IRQ_GPIO(TOSA_GPIO_RECORD_BTN) -#define TOSA_IRQ_GPIO_SYNC IRQ_GPIO(TOSA_GPIO_SYNC) -#define TOSA_IRQ_GPIO_USB_IN IRQ_GPIO(TOSA_GPIO_USB_IN) -#define TOSA_IRQ_GPIO_JACKET_DETECT IRQ_GPIO(TOSA_GPIO_JACKET_DETECT) -#define TOSA_IRQ_GPIO_nSD_INT IRQ_GPIO(TOSA_GPIO_nSD_INT) -#define TOSA_IRQ_GPIO_nSD_DETECT IRQ_GPIO(TOSA_GPIO_nSD_DETECT) -#define TOSA_IRQ_GPIO_BAT1_CRG IRQ_GPIO(TOSA_GPIO_BAT1_CRG) -#define TOSA_IRQ_GPIO_CF_CD IRQ_GPIO(TOSA_GPIO_CF_CD) -#define TOSA_IRQ_GPIO_BAT0_CRG IRQ_GPIO(TOSA_GPIO_BAT0_CRG) -#define TOSA_IRQ_GPIO_TC6393XB_INT IRQ_GPIO(TOSA_GPIO_TC6393XB_INT) -#define TOSA_IRQ_GPIO_BAT0_LOW IRQ_GPIO(TOSA_GPIO_BAT0_LOW) -#define TOSA_IRQ_GPIO_EAR_IN IRQ_GPIO(TOSA_GPIO_EAR_IN) -#define TOSA_IRQ_GPIO_CF_IRQ IRQ_GPIO(TOSA_GPIO_CF_IRQ) -#define TOSA_IRQ_GPIO_ON_KEY IRQ_GPIO(TOSA_GPIO_ON_KEY) -#define TOSA_IRQ_GPIO_VGA_LINE IRQ_GPIO(TOSA_GPIO_VGA_LINE) -#define TOSA_IRQ_GPIO_TP_INT IRQ_GPIO(TOSA_GPIO_TP_INT) -#define TOSA_IRQ_GPIO_JC_CF_IRQ IRQ_GPIO(TOSA_GPIO_JC_CF_IRQ) -#define TOSA_IRQ_GPIO_BAT_LOCKED IRQ_GPIO(TOSA_GPIO_BAT_LOCKED) -#define TOSA_IRQ_GPIO_BAT1_LOW IRQ_GPIO(TOSA_GPIO_BAT1_LOW) -#define TOSA_IRQ_GPIO_KEY_SENSE (a) IRQ_GPIO(69+(a)) - -#define TOSA_IRQ_GPIO_MAIN_BAT_LOW IRQ_GPIO(TOSA_GPIO_MAIN_BAT_LOW) +#define TOSA_IRQ_GPIO_WAKEUP pxa_gpio_to_irq(TOSA_GPIO_WAKEUP) +#define TOSA_IRQ_GPIO_AC_IN pxa_gpio_to_irq(TOSA_GPIO_AC_IN) +#define TOSA_IRQ_GPIO_RECORD_BTN pxa_gpio_to_irq(TOSA_GPIO_RECORD_BTN) +#define TOSA_IRQ_GPIO_SYNC pxa_gpio_to_irq(TOSA_GPIO_SYNC) +#define TOSA_IRQ_GPIO_USB_IN pxa_gpio_to_irq(TOSA_GPIO_USB_IN) +#define TOSA_IRQ_GPIO_JACKET_DETECT pxa_gpio_to_irq(TOSA_GPIO_JACKET_DETECT) +#define TOSA_IRQ_GPIO_nSD_INT pxa_gpio_to_irq(TOSA_GPIO_nSD_INT) +#define TOSA_IRQ_GPIO_nSD_DETECT pxa_gpio_to_irq(TOSA_GPIO_nSD_DETECT) +#define TOSA_IRQ_GPIO_BAT1_CRG pxa_gpio_to_irq(TOSA_GPIO_BAT1_CRG) +#define TOSA_IRQ_GPIO_CF_CD pxa_gpio_to_irq(TOSA_GPIO_CF_CD) +#define TOSA_IRQ_GPIO_BAT0_CRG pxa_gpio_to_irq(TOSA_GPIO_BAT0_CRG) +#define TOSA_IRQ_GPIO_TC6393XB_INT pxa_gpio_to_irq(TOSA_GPIO_TC6393XB_INT) +#define TOSA_IRQ_GPIO_BAT0_LOW pxa_gpio_to_irq(TOSA_GPIO_BAT0_LOW) +#define TOSA_IRQ_GPIO_EAR_IN pxa_gpio_to_irq(TOSA_GPIO_EAR_IN) +#define TOSA_IRQ_GPIO_CF_IRQ pxa_gpio_to_irq(TOSA_GPIO_CF_IRQ) +#define TOSA_IRQ_GPIO_ON_KEY pxa_gpio_to_irq(TOSA_GPIO_ON_KEY) +#define TOSA_IRQ_GPIO_VGA_LINE pxa_gpio_to_irq(TOSA_GPIO_VGA_LINE) +#define TOSA_IRQ_GPIO_TP_INT pxa_gpio_to_irq(TOSA_GPIO_TP_INT) +#define TOSA_IRQ_GPIO_JC_CF_IRQ pxa_gpio_to_irq(TOSA_GPIO_JC_CF_IRQ) +#define TOSA_IRQ_GPIO_BAT_LOCKED pxa_gpio_to_irq(TOSA_GPIO_BAT_LOCKED) +#define TOSA_IRQ_GPIO_BAT1_LOW pxa_gpio_to_irq(TOSA_GPIO_BAT1_LOW) +#define TOSA_IRQ_GPIO_KEY_SENSE (a) pxa_gpio_to_irq(69+(a)) + +#define TOSA_IRQ_GPIO_MAIN_BAT_LOW pxa_gpio_to_irq(TOSA_GPIO_MAIN_BAT_LOW)#define TOSA_KEY_SYNC KEY_102ND/* ??? */ arch/arm/mach-pxa/include/mach/trizeps4.h +8
-8@@ -43,30 +43,30 @@/* Ethernet Controller Davicom DM9000 */ #define GPIO_DM9000 101 -#define TRIZEPS4_ETH_IRQ IRQ_GPIO(GPIO_DM9000) +#define TRIZEPS4_ETH_IRQ pxa_gpio_to_irq(GPIO_DM9000)/* UCB1400 audio / TS-controller */ #define GPIO_UCB1400 1 -#define TRIZEPS4_UCB1400_IRQ IRQ_GPIO(GPIO_UCB1400) +#define TRIZEPS4_UCB1400_IRQ pxa_gpio_to_irq(GPIO_UCB1400)/* PCMCIA socket Compact Flash */ #define GPIO_PCD 11/* PCMCIA Card Detect */ -#define TRIZEPS4_CD_IRQ IRQ_GPIO(GPIO_PCD) +#define TRIZEPS4_CD_IRQ pxa_gpio_to_irq(GPIO_PCD)#define GPIO_PRDY 13/* READY / nINT */ -#define TRIZEPS4_READY_NINT IRQ_GPIO(GPIO_PRDY) +#define TRIZEPS4_READY_NINT pxa_gpio_to_irq(GPIO_PRDY)/* MMC socket */ #define GPIO_MMC_DET 12 -#define TRIZEPS4_MMC_IRQ IRQ_GPIO(GPIO_MMC_DET) +#define TRIZEPS4_MMC_IRQ pxa_gpio_to_irq(GPIO_MMC_DET)/* DOC NAND chip */ #define GPIO_DOC_LOCK 94#define GPIO_DOC_IRQ 93 -#define TRIZEPS4_DOC_IRQ IRQ_GPIO(GPIO_DOC_IRQ) +#define TRIZEPS4_DOC_IRQ pxa_gpio_to_irq(GPIO_DOC_IRQ)/* SPI interface */ #define GPIO_SPI 53 -#define TRIZEPS4_SPI_IRQ IRQ_GPIO(GPIO_SPI) +#define TRIZEPS4_SPI_IRQ pxa_gpio_to_irq(GPIO_SPI)/* LEDS using tx2 / rx2 */ #define GPIO_SYS_BUSY_LED 46@@ -74,7 +74,7 @@/* Off-module PIC on ConXS board */ #define GPIO_PIC 0 -#define TRIZEPS4_PIC_IRQ IRQ_GPIO(GPIO_PIC) +#define TRIZEPS4_PIC_IRQ pxa_gpio_to_irq(GPIO_PIC)#ifdef CONFIG_MACH_TRIZEPS_CONXS /* for CONXS base board define these registers */ arch/arm/mach-pxa/irq.c +0
-61@@ -11,7 +11,6 @@* it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -#include <linux/gpio.h> #include <linux/init.h> #include <linux/module.h> #include <linux/interrupt.h> @@ -90,45 +89,6 @@ static struct irq_chip pxa_internal_irq_chip = { .irq_unmask = pxa_unmask_irq, }; -/* -* GPIO IRQs for GPIO 0 and 1 -*/ -static int pxa_set_low_gpio_type (struct irq_data *d,unsigned int type) -{ -int gpio = d->irq -IRQ_GPIO0 ; - -if (__gpio_is_occupied (gpio)) { -pr_err ("%s failed: GPIO is configured\n" , __func__); -return -EINVAL ; - } - -if (type &IRQ_TYPE_EDGE_RISING ) -GRER (gpio) |=GPIO_bit (gpio); -else -GRER (gpio) &= ~GPIO_bit (gpio); - -if (type &IRQ_TYPE_EDGE_FALLING ) -GFER (gpio) |=GPIO_bit (gpio); -else -GFER (gpio) &= ~GPIO_bit (gpio); - -return 0 ; -} - -static void pxa_ack_low_gpio (struct irq_data *d) -{ -int gpio = d->irq -IRQ_GPIO0 ; -GEDR (gpio) =1 << gpio; -} - -static struct irq_chip pxa_low_gpio_chip = { - .name ="GPIO-l" , - .irq_ack = pxa_ack_low_gpio, - .irq_mask = pxa_mask_irq, - .irq_unmask = pxa_unmask_irq, - .irq_set_type = pxa_set_low_gpio_type, -}; - asmlinkage void __exception_irq_entry icip_handle_irq(struct pt_regs *regs) {uint32_t icip, icmr, mask;@@ -159,26 +119,6 @@ asmlinkage void __exception_irq_entry ichp_handle_irq(struct pt_regs *regs) }while (1 ); } -static void __init pxa_init_low_gpio_irq (int (*fn)(struct irq_data *, -unsigned int )) -{ -int irq; - -/* clear edge detection on GPIO 0 and 1 */ -GFER (0 ) &= ~0x3 ; -GRER (0 ) &= ~0x3 ; -GEDR (0 ) =0x3 ; - -for (irq =IRQ_GPIO0 ; irq <=IRQ_GPIO1 ; irq++) { -irq_set_chip_and_handler (irq, &pxa_low_gpio_chip, - handle_edge_irq); -irq_set_chip_data (irq,irq_base (0 )); -set_irq_flags (irq,IRQF_VALID ); - } - - pxa_low_gpio_chip.irq_set_wake = fn; -} -void __init pxa_init_irq (int irq_nr,int (*fn)(struct irq_data *,unsigned int )) {int irq, i, n;@@ -209,7 +149,6 @@ void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int))__raw_writel (1 ,irq_base (0 ) +ICCR ); pxa_internal_irq_chip.irq_set_wake = fn; -pxa_init_low_gpio_irq (fn); }#ifdef CONFIG_PM arch/arm/mach-pxa/littleton.c +2
-2@@ -124,8 +124,8 @@ static struct resource smc91x_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO90)), - .end = IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO90)), + .start = pxa_gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO90)), + .end = pxa_gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO90)), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, } };arch/arm/mach-pxa/lpd270.c +2
-2@@ -152,8 +152,8 @@ static void __init lpd270_init_irq(void) handle_level_irq);set_irq_flags (irq,IRQF_VALID |IRQF_PROBE ); } -irq_set_chained_handler (IRQ_GPIO (0 ), lpd270_irq_handler); -irq_set_irq_type (IRQ_GPIO (0 ),IRQ_TYPE_EDGE_FALLING ); +irq_set_chained_handler (pxa_gpio_to_irq (0 ), lpd270_irq_handler); +irq_set_irq_type (pxa_gpio_to_irq (0 ),IRQ_TYPE_EDGE_FALLING ); }arch/arm/mach-pxa/lubbock.c +2
-2@@ -170,8 +170,8 @@ static void __init lubbock_init_irq(void)set_irq_flags (irq,IRQF_VALID |IRQF_PROBE ); } -irq_set_chained_handler (IRQ_GPIO (0 ), lubbock_irq_handler); -irq_set_irq_type (IRQ_GPIO (0 ),IRQ_TYPE_EDGE_FALLING ); +irq_set_chained_handler (pxa_gpio_to_irq (0 ), lubbock_irq_handler); +irq_set_irq_type (pxa_gpio_to_irq (0 ),IRQ_TYPE_EDGE_FALLING ); }#ifdef CONFIG_PM arch/arm/mach-pxa/mainstone.c +2
-2@@ -178,8 +178,8 @@ static void __init mainstone_init_irq(void)MST_INTMSKENA =0 ;MST_INTSETCLR =0 ; -irq_set_chained_handler (IRQ_GPIO (0 ), mainstone_irq_handler); -irq_set_irq_type (IRQ_GPIO (0 ),IRQ_TYPE_EDGE_FALLING ); +irq_set_chained_handler (pxa_gpio_to_irq (0 ), mainstone_irq_handler); +irq_set_irq_type (pxa_gpio_to_irq (0 ),IRQ_TYPE_EDGE_FALLING ); }#ifdef CONFIG_PM arch/arm/mach-pxa/poodle.c +2
-2@@ -166,8 +166,8 @@ static struct resource locomo_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = IRQ_GPIO(10), - .end = IRQ_GPIO(10), + .start = pxa_gpio_to_irq(10), + .end = pxa_gpio_to_irq(10), .flags = IORESOURCE_IRQ, }, };arch/arm/mach-pxa/sharpsl_pm.c +12
-12@@ -907,24 +907,24 @@ static int __devinit sharpsl_pm_probe(struct platform_device *pdev)gpio_direction_input (sharpsl_pm.machinfo->gpio_batlock);/* Register interrupt handlers */ -if (request_irq (IRQ_GPIO (sharpsl_pm.machinfo->gpio_acin), sharpsl_ac_isr,IRQF_DISABLED |IRQF_TRIGGER_RISING |IRQF_TRIGGER_FALLING ,"AC Input Detect" , sharpsl_ac_isr)) { -dev_err (sharpsl_pm.dev,"Could not get irq %d.\n" ,IRQ_GPIO (sharpsl_pm.machinfo->gpio_acin)); +if (request_irq (pxa_gpio_to_irq (sharpsl_pm.machinfo->gpio_acin), sharpsl_ac_isr,IRQF_DISABLED |IRQF_TRIGGER_RISING |IRQF_TRIGGER_FALLING ,"AC Input Detect" , sharpsl_ac_isr)) { +dev_err (sharpsl_pm.dev,"Could not get irq %d.\n" ,pxa_gpio_to_irq (sharpsl_pm.machinfo->gpio_acin)); } -if (request_irq (IRQ_GPIO (sharpsl_pm.machinfo->gpio_batlock), sharpsl_fatal_isr,IRQF_DISABLED |IRQF_TRIGGER_FALLING ,"Battery Cover" , sharpsl_fatal_isr)) { -dev_err (sharpsl_pm.dev,"Could not get irq %d.\n" ,IRQ_GPIO (sharpsl_pm.machinfo->gpio_batlock)); +if (request_irq (pxa_gpio_to_irq (sharpsl_pm.machinfo->gpio_batlock), sharpsl_fatal_isr,IRQF_DISABLED |IRQF_TRIGGER_FALLING ,"Battery Cover" , sharpsl_fatal_isr)) { +dev_err (sharpsl_pm.dev,"Could not get irq %d.\n" ,pxa_gpio_to_irq (sharpsl_pm.machinfo->gpio_batlock)); }if (sharpsl_pm.machinfo->gpio_fatal) { -if (request_irq (IRQ_GPIO (sharpsl_pm.machinfo->gpio_fatal), sharpsl_fatal_isr,IRQF_DISABLED |IRQF_TRIGGER_FALLING ,"Fatal Battery" , sharpsl_fatal_isr)) { -dev_err (sharpsl_pm.dev,"Could not get irq %d.\n" ,IRQ_GPIO (sharpsl_pm.machinfo->gpio_fatal)); +if (request_irq (pxa_gpio_to_irq (sharpsl_pm.machinfo->gpio_fatal), sharpsl_fatal_isr,IRQF_DISABLED |IRQF_TRIGGER_FALLING ,"Fatal Battery" , sharpsl_fatal_isr)) { +dev_err (sharpsl_pm.dev,"Could not get irq %d.\n" ,pxa_gpio_to_irq (sharpsl_pm.machinfo->gpio_fatal)); } }if (sharpsl_pm.machinfo->batfull_irq) {/* Register interrupt handler. */ -if (request_irq (IRQ_GPIO (sharpsl_pm.machinfo->gpio_batfull), sharpsl_chrg_full_isr,IRQF_DISABLED |IRQF_TRIGGER_RISING ,"CO" , sharpsl_chrg_full_isr)) { -dev_err (sharpsl_pm.dev,"Could not get irq %d.\n" ,IRQ_GPIO (sharpsl_pm.machinfo->gpio_batfull)); +if (request_irq (pxa_gpio_to_irq (sharpsl_pm.machinfo->gpio_batfull), sharpsl_chrg_full_isr,IRQF_DISABLED |IRQF_TRIGGER_RISING ,"CO" , sharpsl_chrg_full_isr)) { +dev_err (sharpsl_pm.dev,"Could not get irq %d.\n" ,pxa_gpio_to_irq (sharpsl_pm.machinfo->gpio_batfull)); } }@@ -953,14 +953,14 @@ static int sharpsl_pm_remove(struct platform_device *pdev)led_trigger_unregister_simple (sharpsl_charge_led_trigger); -free_irq (IRQ_GPIO (sharpsl_pm.machinfo->gpio_acin), sharpsl_ac_isr); -free_irq (IRQ_GPIO (sharpsl_pm.machinfo->gpio_batlock), sharpsl_fatal_isr); +free_irq (pxa_gpio_to_irq (sharpsl_pm.machinfo->gpio_acin), sharpsl_ac_isr); +free_irq (pxa_gpio_to_irq (sharpsl_pm.machinfo->gpio_batlock), sharpsl_fatal_isr);if (sharpsl_pm.machinfo->gpio_fatal) -free_irq (IRQ_GPIO (sharpsl_pm.machinfo->gpio_fatal), sharpsl_fatal_isr); +free_irq (pxa_gpio_to_irq (sharpsl_pm.machinfo->gpio_fatal), sharpsl_fatal_isr);if (sharpsl_pm.machinfo->batfull_irq) -free_irq (IRQ_GPIO (sharpsl_pm.machinfo->gpio_batfull), sharpsl_chrg_full_isr); +free_irq (pxa_gpio_to_irq (sharpsl_pm.machinfo->gpio_batfull), sharpsl_chrg_full_isr);gpio_free (sharpsl_pm.machinfo->gpio_batlock);gpio_free (sharpsl_pm.machinfo->gpio_batfull);arch/arm/mach-pxa/stargate2.c +11
-11@@ -376,7 +376,7 @@ static struct spi_board_info spi_board_info[] __initdata = { .bus_num = 1, .chip_select = 0, .controller_data = &staccel_chip_info, - .irq = IRQ_GPIO(96), + .irq = pxa_gpio_to_irq(96), }, { .modalias = "cc2420", .max_speed_hz = 6500000,@@ -560,18 +560,18 @@ static struct i2c_board_info __initdata imote2_i2c_board_info[] = {/* Through a nand gate - Also beware, on V2 sensor board the * pull up resistors are missing. */ - .irq = IRQ_GPIO(99), + .irq = pxa_gpio_to_irq(99), }, { /* ITS400 Sensor board only */ .type = "tsl2561", .addr = 0x49, /* Through a nand gate - Also beware, on V2 sensor board the * pull up resistors are missing. */ - .irq = IRQ_GPIO(99), + .irq = pxa_gpio_to_irq(99), }, { /* ITS400 Sensor board only */ .type = "tmp175", .addr = 0x4A, - .irq = IRQ_GPIO(96), + .irq = pxa_gpio_to_irq(96), }, { /* IMB400 Multimedia board */ .type = "wm8940", .addr = 0x1A,@@ -661,8 +661,8 @@ static struct resource smc91x_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = IRQ_GPIO(40), - .end = IRQ_GPIO(40), + .start = pxa_gpio_to_irq(40), + .end = pxa_gpio_to_irq(40), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, } };@@ -707,7 +707,7 @@ static int stargate2_mci_init(struct device *dev, }gpio_direction_input (SG2_GPIO_nSD_DETECT); - err = request_irq(IRQ_GPIO(SG2_GPIO_nSD_DETECT), + err = request_irq(pxa_gpio_to_irq(SG2_GPIO_nSD_DETECT), stargate2_detect_int, IRQ_TYPE_EDGE_BOTH, "MMC card detect",@@ -738,7 +738,7 @@ static void stargate2_mci_setpower(struct device *dev, unsigned int vdd)static void stargate2_mci_exit (struct device *dev,void *data) { -free_irq (IRQ_GPIO (SG2_GPIO_nSD_DETECT), data); +free_irq (pxa_gpio_to_irq (SG2_GPIO_nSD_DETECT), data);gpio_free (SG2_SD_POWER_ENABLE );gpio_free (SG2_GPIO_nSD_DETECT); }@@ -938,18 +938,18 @@ static struct i2c_board_info __initdata stargate2_i2c_board_info[] = {/* Through a nand gate - Also beware, on V2 sensor board the * pull up resistors are missing. */ - .irq = IRQ_GPIO(99), + .irq = pxa_gpio_to_irq(99), }, { /* ITS400 Sensor board only */ .type = "tsl2561", .addr = 0x49, /* Through a nand gate - Also beware, on V2 sensor board the * pull up resistors are missing. */ - .irq = IRQ_GPIO(99), + .irq = pxa_gpio_to_irq(99), }, { /* ITS400 Sensor board only */ .type = "tmp175", .addr = 0x4A, - .irq = IRQ_GPIO(96), + .irq = pxa_gpio_to_irq(96), }, };arch/arm/mach-pxa/vpac270.c +3
-3@@ -395,8 +395,8 @@ static struct resource vpac270_dm9000_resources[] = { .flags = IORESOURCE_MEM, }, [2] = { - .start = IRQ_GPIO(GPIO114_VPAC270_ETH_IRQ), - .end = IRQ_GPIO(GPIO114_VPAC270_ETH_IRQ), + .start = pxa_gpio_to_irq(GPIO114_VPAC270_ETH_IRQ), + .end = pxa_gpio_to_irq(GPIO114_VPAC270_ETH_IRQ), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, }, };@@ -433,7 +433,7 @@ static pxa2xx_audio_ops_t vpac270_ac97_pdata = { };static struct ucb1400_pdata vpac270_ucb1400_pdata = { - .irq =IRQ_GPIO (GPIO113_VPAC270_TS_IRQ ), + .irq =pxa_gpio_to_irq (GPIO113_VPAC270_TS_IRQ ), };static struct platform_device vpac270_ucb1400_device = {arch/arm/mach-pxa/zylonite_pxa300.c +2
-2@@ -231,12 +231,12 @@ static struct i2c_board_info zylonite_i2c_board_info[] = { .type = "pca9539", .addr = 0x74, .platform_data = &gpio_exp[0], - .irq = IRQ_GPIO(18), + .irq = pxa_gpio_to_irq(18), }, { .type = "pca9539", .addr = 0x75, .platform_data = &gpio_exp[1], - .irq = IRQ_GPIO(19), + .irq = pxa_gpio_to_irq(19), }, };arch/arm/plat-pxa/gpio.c +14
-0@@ -282,6 +282,20 @@ void __init pxa_init_gpio(int mux_irq, int start, int end,__raw_writel (~0 ,c->regbase +GEDR_OFFSET ); } +#ifdef CONFIG_ARCH_PXA + irq =gpio_to_irq (0 ); +irq_set_chip_and_handler (irq, &pxa_muxed_gpio_chip, + handle_edge_irq); +set_irq_flags (irq,IRQF_VALID |IRQF_PROBE ); +irq_set_chained_handler (IRQ_GPIO0 , pxa_gpio_demux_handler); + + irq =gpio_to_irq (1 ); +irq_set_chip_and_handler (irq, &pxa_muxed_gpio_chip, + handle_edge_irq); +set_irq_flags (irq,IRQF_VALID |IRQF_PROBE ); +irq_set_chained_handler (IRQ_GPIO1 , pxa_gpio_demux_handler); +#endif +for (irq =pxa_gpio_to_irq (start); irq <=pxa_gpio_to_irq (end); irq++) { irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,Signature · 7 lines
1.7.2.5 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel at lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
PATCH 5/5 ARM: pxa: move gpio driver into drivers directory
In reply to a message not in the archiveMove gpio driver from plat-pxa to drivers/gpio directory. Only leave gpio number macro in mach/gpio.h.
Signed-off-by Haojian Zhuang <[email protected]>
--- arch/arm/mach-mmp/Kconfig | 3 + arch/arm/mach-mmp/Makefile | 2 +- arch/arm/mach-mmp/aspenite.c | 4 +- arch/arm/mach-mmp/flint.c | 4 +- arch/arm/mach-mmp/gpio.c | 89 ++++++ arch/arm/mach-mmp/gplugd.c | 2 +- arch/arm/mach-mmp/include/mach/gpio.h | 24 +-- arch/arm/mach-mmp/include/mach/irqs.h | 4 +- arch/arm/mach-mmp/mmp2.c | 17 -- arch/arm/mach-mmp/pxa168.c | 17 -- arch/arm/mach-mmp/pxa910.c | 17 -- arch/arm/mach-mmp/tavorevb.c | 4 +- arch/arm/mach-mmp/teton_bga.c | 2 +- arch/arm/mach-mmp/ttc_dkb.c | 2 +- arch/arm/mach-pxa/Kconfig | 6 + arch/arm/mach-pxa/Makefile | 2 +- arch/arm/mach-pxa/gpio.c | 92 ++++++ arch/arm/mach-pxa/include/mach/gpio.h | 64 ----- arch/arm/mach-pxa/pxa25x.c | 3 - arch/arm/mach-pxa/pxa27x.c | 2 - arch/arm/mach-pxa/pxa3xx.c | 2 - arch/arm/mach-pxa/pxa95x.c | 2 - arch/arm/plat-pxa/Makefile | 1 - arch/arm/plat-pxa/gpio.c | 352 ----------------------- arch/arm/plat-pxa/include/plat/gpio.h | 65 ----- drivers/gpio/Kconfig | 6 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-pxa.c | 500 +++++++++++++++++++++++++++++++++ include/linux/gpio-pxa.h | 105 +++++++ 29 files changed, 816 insertions(+), 578 deletions(-) create mode 100644 arch/arm/mach-mmp/gpio.c create mode 100644 arch/arm/mach-pxa/gpio.c delete mode 100644 arch/arm/plat-pxa/gpio.c delete mode 100644 arch/arm/plat-pxa/include/plat/gpio.h create mode 100644 drivers/gpio/gpio-pxa.c create mode 100644 include/linux/gpio-pxa.h
arch/arm/mach-mmp/Kconfig +3 -0
@@ -89,18 +89,21 @@ endmenu config CPU_PXA168 bool select CPU_MOHAWK + select GPIO_PXA help Select code specific to PXA168 config CPU_PXA910 bool select CPU_MOHAWK + select GPIO_PXA help Select code specific to PXA910 config CPU_MMP2 bool select CPU_PJ4 + select GPIO_PXA help Select code specific to MMP2. MMP2 is ARMv7 compatible. endif
arch/arm/mach-mmp/Makefile +1 -1
@@ -2,7 +2,7 @@ # Makefile for Marvell's PXA168 processors line # -obj-y += common.o clock.o devices.o time.o +obj-y += common.o clock.o devices.o time.o gpio.o # SoC support obj-$(CONFIG_CPU_PXA168) += pxa168.o irq-pxa168.o
arch/arm/mach-mmp/aspenite.c +2 -2
@@ -119,8 +119,8 @@ static struct resource smc91x_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = pxa_gpio_to_irq(27), - .end = pxa_gpio_to_irq(27), + .start = mmp_gpio_to_irq(27), + .end = mmp_gpio_to_irq(27), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, } };
arch/arm/mach-mmp/flint.c +2 -2
@@ -87,8 +87,8 @@ static struct resource smc91x_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = pxa_gpio_to_irq(155), - .end = pxa_gpio_to_irq(155), + .start = mmp_gpio_to_irq(155), + .end = mmp_gpio_to_irq(155), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, } };
arch/arm/mach-mmp/gpio.c new file +89 -0
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arch/arm/mach-mmp/gplugd.c +1 -1
@@ -9,11 +9,11 @@*/ #include <linux/init.h> +#include <linux/gpio.h> #include <asm/mach/arch.h> #include <asm/mach-types.h> -#include <mach/gpio.h> #include <mach/pxa168.h> #include <mach/mfp-pxa168.h>
arch/arm/mach-mmp/include/mach/gpio.h +1 -23
@@ -3,31 +3,9 @@#include <mach/addr-map.h> #include <mach/irqs.h> -#include <asm-generic/gpio.h> -#define GPIO_REGS_VIRT (APB_VIRT_BASE + 0x19000) - -#define BANK_OFF (n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2)) -#define GPIO_REG (x) (*((volatile u32 *)(GPIO_REGS_VIRT + (x)))) +#define GPIO_REGS_VIRT (APB_VIRT_BASE + 0x19000)#define NR_BUILTIN_GPIO IRQ_GPIO_NUM -#define gpio_to_bank (gpio) ((gpio) >> 5) - -#define __gpio_is_inverted (gpio) (0) -#define __gpio_is_occupied (gpio) (0) - -/* NOTE: these macros are defined here to make optimization of -* gpio_{get,set}_value() to work when 'gpio' is a constant. -* Usage of these macros otherwise is no longer recommended, -* use generic GPIO API whenever possible. -*/ -#define GPIO_bit (gpio) (1 << ((gpio) & 0x1f)) - -#define GPLR (x) GPIO_REG(BANK_OFF(gpio_to_bank(x)) + 0x00) -#define GPDR (x) GPIO_REG(BANK_OFF(gpio_to_bank(x)) + 0x0c) -#define GPSR (x) GPIO_REG(BANK_OFF(gpio_to_bank(x)) + 0x18) -#define GPCR (x) GPIO_REG(BANK_OFF(gpio_to_bank(x)) + 0x24) - -#include <plat/gpio.h> #endif /* __ASM_MACH_GPIO_H */
arch/arm/mach-mmp/include/mach/irqs.h +2 -2
@@ -220,8 +220,8 @@#define IRQ_GPIO_START 128#define IRQ_GPIO_NUM 192 -#define pxa_gpio_to_irq (gpio) (IRQ_GPIO_START + (gpio)) -#define pxa_irq_to_gpio (irq) ((irq) - IRQ_GPIO_START) +#define mmp_gpio_to_irq (gpio) (IRQ_GPIO_START + (gpio)) +#define mmp_irq_to_gpio (irq) ((irq) - IRQ_GPIO_START)#define IRQ_BOARD_START (IRQ_GPIO_START + IRQ_GPIO_NUM)
arch/arm/mach-mmp/mmp2.c +0 -17
@@ -33,8 +33,6 @@#define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000) -#define APMASK (i) (GPIO_REGS_VIRT + BANK_OFF(i) + 0x9c) -static struct mfp_addr_map mmp2_addr_map[]__initdata = {MFP_ADDR_X (GPIO0 ,GPIO58 ,0x54 ),
@@ -94,24 +92,9 @@ void mmp2_clear_pmic_int(void)__raw_writel (data, mfpr_pmic); } -static void __init mmp2_init_gpio (void ) -{ -int i; - -/* enable GPIO clock */ -__raw_writel (APBC_APBCLK |APBC_FNCLK ,APBC_MMP2_GPIO ); - -/* unmask GPIO edge detection for all 6 banks -- APMASKx */ -for (i =0 ; i <6 ; i++) -__raw_writel (0xffffffff ,APMASK (i)); - -pxa_init_gpio (IRQ_MMP2_GPIO ,0 ,167 ,NULL ); -} -void __init mmp2_init_irq (void ) {mmp2_init_icu (); -mmp2_init_gpio (); }static void sdhc_clk_enable (struct clk *clk)
arch/arm/mach-mmp/pxa168.c +0 -17
@@ -43,26 +43,9 @@ static struct mfp_addr_map pxa168_mfp_addr_map[] __initdata = MFP_ADDR_END, }; -#define APMASK (i) (GPIO_REGS_VIRT + BANK_OFF(i) + 0x09c) - -static void __init pxa168_init_gpio (void ) -{ -int i; - -/* enable GPIO clock */ -__raw_writel (APBC_APBCLK |APBC_FNCLK ,APBC_PXA168_GPIO ); - -/* unmask GPIO edge detection for all 4 banks - APMASKx */ -for (i =0 ; i <4 ; i++) -__raw_writel (0xffffffff ,APMASK (i)); - -pxa_init_gpio (IRQ_PXA168_GPIOX ,0 ,127 ,NULL ); -} -void __init pxa168_init_irq (void ) {icu_init_irq (); -pxa168_init_gpio (); }/* APB peripheral clocks */
arch/arm/mach-mmp/pxa910.c +0 -17
@@ -77,26 +77,9 @@ static struct mfp_addr_map pxa910_mfp_addr_map[] __initdata = MFP_ADDR_END, }; -#define APMASK (i) (GPIO_REGS_VIRT + BANK_OFF(i) + 0x09c) - -static void __init pxa910_init_gpio (void ) -{ -int i; - -/* enable GPIO clock */ -__raw_writel (APBC_APBCLK |APBC_FNCLK ,APBC_PXA910_GPIO ); - -/* unmask GPIO edge detection for all 4 banks - APMASKx */ -for (i =0 ; i <4 ; i++) -__raw_writel (0xffffffff ,APMASK (i)); - -pxa_init_gpio (IRQ_PXA910_AP_GPIO ,0 ,127 ,NULL ); -} -void __init pxa910_init_irq (void ) {icu_init_irq (); -pxa910_init_gpio (); }/* APB peripheral clocks */
arch/arm/mach-mmp/tavorevb.c +2 -2
@@ -70,8 +70,8 @@ static struct resource smc91x_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = pxa_gpio_to_irq(80), - .end = pxa_gpio_to_irq(80), + .start = mmp_gpio_to_irq(80), + .end = mmp_gpio_to_irq(80), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, } };
arch/arm/mach-mmp/teton_bga.c +1 -1
@@ -66,7 +66,7 @@ static struct pxa27x_keypad_platform_data teton_bga_keypad_info __initdata = {static struct i2c_board_info teton_bga_i2c_info[]__initdata = { {I2C_BOARD_INFO ("ds1337" ,0x68 ), - .irq =pxa_gpio_to_irq (RTC_INT_GPIO ) + .irq =mmp_gpio_to_irq (RTC_INT_GPIO ) }, };
arch/arm/mach-mmp/ttc_dkb.c +1 -1
@@ -136,7 +136,7 @@ static struct i2c_board_info ttc_dkb_i2c_info[] = { { .type = "max7312", .addr = 0x23, - .irq = pxa_gpio_to_irq(80), + .irq = mmp_gpio_to_irq(80), .platform_data = &max7312_data, }, };
arch/arm/mach-pxa/Kconfig +6 -0
@@ -604,24 +604,28 @@ endmenu config PXA25x bool select CPU_XSCALE + select GPIO_PXA help Select code specific to PXA21x/25x/26x variants config PXA27x bool select CPU_XSCALE + select GPIO_PXA help Select code specific to PXA27x variants config CPU_PXA26x bool select PXA25x + select GPIO_PXA help Select code specific to PXA26x (codename Dalhart) config PXA3xx bool select CPU_XSC3 + select GPIO_PXA help Select code specific to PXA3xx variants
@@ -647,6 +651,7 @@ config CPU_PXA320 config CPU_PXA930 bool select PXA3xx + select GPIO_PXA help PXA930 (codename Tavor-P)
@@ -659,6 +664,7 @@ config CPU_PXA935 config PXA95x bool select CPU_PJ4 + select GPIO_PXA help Select code specific to PXA95x variants
arch/arm/mach-pxa/Makefile +1 -1
@@ -3,7 +3,7 @@ # # Common support (must be linked before board specific support) -obj-y += clock.o devices.o generic.o irq.o \ +obj-y += clock.o devices.o generic.o irq.o gpio.o\ time.o reset.o obj-$(CONFIG_PM) += pm.o sleep.o standby.o
arch/arm/mach-pxa/gpio.c new file +92 -0
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arch/arm/mach-pxa/include/mach/gpio.h +0 -64
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arch/arm/mach-pxa/pxa25x.c +0 -3
@@ -311,14 +311,12 @@ set_pwer:void __init pxa25x_init_irq (void ) {pxa_init_irq (32 , pxa25x_set_wake); -pxa_init_gpio (IRQ_GPIO_2_x,2 ,84 , pxa25x_set_wake); }#ifdef CONFIG_CPU_PXA26xvoid __init pxa26x_init_irq (void ) {pxa_init_irq (32 , pxa25x_set_wake); -pxa_init_gpio (IRQ_GPIO_2_x,2 ,89 , pxa25x_set_wake); }#endif
@@ -368,7 +366,6 @@ static int __init pxa25x_init(void)register_syscore_ops (&pxa_irq_syscore_ops);register_syscore_ops (&pxa2xx_mfp_syscore_ops); -register_syscore_ops (&pxa_gpio_syscore_ops);register_syscore_ops (&pxa2xx_clock_syscore_ops); ret = platform_add_devices(pxa25x_devices,
arch/arm/mach-pxa/pxa27x.c +0 -2
@@ -385,7 +385,6 @@ static int pxa27x_set_wake(struct irq_data *d, unsigned int on)void __init pxa27x_init_irq (void ) {pxa_init_irq (34 , pxa27x_set_wake); -pxa_init_gpio (IRQ_GPIO_2_x,2 ,120 , pxa27x_set_wake); }static struct map_desc pxa27x_io_desc[]__initdata = {
@@ -454,7 +453,6 @@ static int __init pxa27x_init(void)register_syscore_ops (&pxa_irq_syscore_ops);register_syscore_ops (&pxa2xx_mfp_syscore_ops); -register_syscore_ops (&pxa_gpio_syscore_ops);register_syscore_ops (&pxa2xx_clock_syscore_ops); ret =platform_add_devices (devices,ARRAY_SIZE (devices));
arch/arm/mach-pxa/pxa3xx.c +0 -2
@@ -389,7 +389,6 @@ void __init pxa3xx_init_irq(void)pxa_init_irq (56 , pxa3xx_set_wake);pxa_init_ext_wakeup_irq (pxa3xx_set_wake); -pxa_init_gpio (IRQ_GPIO_2_x,2 ,127 ,NULL ); }static struct map_desc pxa3xx_io_desc[]__initdata = {
@@ -461,7 +460,6 @@ static int __init pxa3xx_init(void)register_syscore_ops (&pxa_irq_syscore_ops);register_syscore_ops (&pxa3xx_mfp_syscore_ops); -register_syscore_ops (&pxa_gpio_syscore_ops);register_syscore_ops (&pxa3xx_clock_syscore_ops); ret =platform_add_devices (devices,ARRAY_SIZE (devices));
arch/arm/mach-pxa/pxa95x.c +0 -2
@@ -235,7 +235,6 @@ static struct clk_lookup pxa95x_clkregs[] = {void __init pxa95x_init_irq (void ) {pxa_init_irq (96 ,NULL ); -pxa_init_gpio (IRQ_GPIO_2_x,2 ,127 ,NULL ); }/*
@@ -282,7 +281,6 @@ static int __init pxa95x_init(void)return ret;register_syscore_ops (&pxa_irq_syscore_ops); -register_syscore_ops (&pxa_gpio_syscore_ops);register_syscore_ops (&pxa3xx_clock_syscore_ops); ret =platform_add_devices (devices,ARRAY_SIZE (devices));
arch/arm/plat-pxa/Makefile +0 -1
@@ -4,7 +4,6 @@ obj-y := dma.o -obj-$(CONFIG_GENERIC_GPIO) += gpio.o obj-$(CONFIG_PXA3xx) += mfp.o obj-$(CONFIG_PXA95x) += mfp.o obj-$(CONFIG_ARCH_MMP) += mfp.o
arch/arm/plat-pxa/gpio.c deleted +0 -352
352 lines not on this page · raw message
arch/arm/plat-pxa/include/plat/gpio.h deleted +0 -65
65 lines not on this page · raw message
drivers/gpio/Kconfig +6 -0
@@ -141,6 +141,12 @@ config GPIO_PL061 help Say yes here to support the PrimeCell PL061 GPIO device +config GPIO_PXA + def_bool y + depends on ARCH_PXA || ARCH_MMP + help + Say yes here to support the PXA GPIO device + config GPIO_XILINX bool "Xilinx GPIO support" depends on PPC_OF || MICROBLAZE
drivers/gpio/Makefile +1 -0
@@ -40,6 +40,7 @@ obj-$(CONFIG_GPIO_PCA953X) += gpio-pca953x.o obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf857x.o obj-$(CONFIG_GPIO_PCH) += gpio-pch.o obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o +obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o obj-$(CONFIG_PLAT_SAMSUNG) += gpio-samsung.o
drivers/gpio/gpio-pxa.c new file +500 -0
500 lines not on this page · raw message
include/linux/gpio-pxa.h new file +105 -0
105 lines not on this page · raw message
Signature · 1 line
1.7.2.5
PATCH 5/5 ARM: pxa: move gpio driver into drivers directory
arch/arm/mach-mmp/gpio.c line 19
Quoted 4 lines · Haojian Zhuang
arch/arm/mach-mmp/gpio.c new file +4
-0+#include <linux/gpio-pxa.h> +#include <linux/platform_device.h> + +#include <asm/io.h>
linux/gpio.h please.
Haojian Zhuang
maintainerPATCH 5/5 ARM: pxa: move gpio driver into drivers directory
Quoted 8 lines · Russell King - ARM Linux
arch/arm/mach-mmp/gpio.c line 19
Quoted 4 lines · Haojian Zhuang
arch/arm/mach-mmp/gpio.c new file +4
-0+#include <linux/gpio-pxa.h> +#include <linux/platform_device.h> + +#include <asm/io.h>
linux/gpio.hplease.
Excuse me that I didn't use any gpio API in mach-pxa/gpio.c. It seems that I needn't include "linux/gpio.h" at mach-pxa/gpio.c.
Thanks
Haojian
PATCH 5/5 ARM: pxa: move gpio driver into drivers directory
Quoted 11 lines · Haojian Zhuang
Quoted 8 lines · Russell King - ARM Linux
arch/arm/mach-mmp/gpio.c line 19
Quoted 4 lines · Haojian Zhuang
arch/arm/mach-mmp/gpio.c new file +4
-0+#include <linux/gpio-pxa.h> +#include <linux/platform_device.h> + +#include <asm/io.h>
linux/gpio.hplease.
Quoted 2 lines
Excuse me that I didn't use any gpio API in
mach-pxa/gpio.c. It seems that I needn't include "linux/gpio.h" atmach-pxa/gpio.c.
Sorry, that should've been linux/io.h not gpio.h
PATCH 5/5 ARM: pxa: move gpio driver into drivers directory
In reply to Haojian ZhuangQuoted 196 lines · Haojian Zhuang
Move gpio driver from plat-pxa to
drivers/gpiodirectory. Only leave gpio number macro inmach/gpio.h.Signed-off-by Haojian Zhuang <[email protected]>--- arch/arm/mach-mmp/Kconfig | 3 + arch/arm/mach-mmp/Makefile | 2 +- arch/arm/mach-mmp/aspenite.c | 4 +- arch/arm/mach-mmp/flint.c | 4 +- arch/arm/mach-mmp/gpio.c | 89 ++++++ arch/arm/mach-mmp/gplugd.c | 2 +- arch/arm/mach-mmp/include/mach/gpio.h | 24 +-- arch/arm/mach-mmp/include/mach/irqs.h | 4 +- arch/arm/mach-mmp/mmp2.c | 17 -- arch/arm/mach-mmp/pxa168.c | 17 -- arch/arm/mach-mmp/pxa910.c | 17 -- arch/arm/mach-mmp/tavorevb.c | 4 +- arch/arm/mach-mmp/teton_bga.c | 2 +- arch/arm/mach-mmp/ttc_dkb.c | 2 +- arch/arm/mach-pxa/Kconfig | 6 + arch/arm/mach-pxa/Makefile | 2 +- arch/arm/mach-pxa/gpio.c | 92 ++++++ arch/arm/mach-pxa/include/mach/gpio.h | 64 ----- arch/arm/mach-pxa/pxa25x.c | 3 - arch/arm/mach-pxa/pxa27x.c | 2 - arch/arm/mach-pxa/pxa3xx.c | 2 - arch/arm/mach-pxa/pxa95x.c | 2 - arch/arm/plat-pxa/Makefile | 1 - arch/arm/plat-pxa/gpio.c | 352 ----------------------- arch/arm/plat-pxa/include/plat/gpio.h | 65 ----- drivers/gpio/Kconfig | 6 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-pxa.c | 500 +++++++++++++++++++++++++++++++++ include/linux/gpio-pxa.h | 105 +++++++ 29 files changed, 816 insertions(+), 578 deletions(-) create mode 100644 arch/arm/mach-mmp/gpio.c create mode 100644 arch/arm/mach-pxa/gpio.c delete mode 100644 arch/arm/plat-pxa/gpio.c delete mode 100644 arch/arm/plat-pxa/include/plat/gpio.h create mode 100644 drivers/gpio/gpio-pxa.c create mode 100644 include/linux/gpio-pxa.harch/arm/mach-mmp/Kconfig +3
-0@@ -89,18 +89,21 @@ endmenu config CPU_PXA168 bool select CPU_MOHAWK + select GPIO_PXA help Select code specific to PXA168 config CPU_PXA910 bool select CPU_MOHAWK + select GPIO_PXA help Select code specific to PXA910 config CPU_MMP2 bool select CPU_PJ4 + select GPIO_PXA help Select code specific to MMP2. MMP2 is ARMv7 compatible. endifarch/arm/mach-mmp/Makefile +1
-1@@ -2,7 +2,7 @@ # Makefile for Marvell's PXA168 processors line # -obj-y += common.o clock.o devices.o time.o +obj-y += common.o clock.o devices.o time.o gpio.o # SoC support obj-$(CONFIG_CPU_PXA168) += pxa168.o irq-pxa168.oarch/arm/mach-mmp/aspenite.c +2
-2@@ -119,8 +119,8 @@ static struct resource smc91x_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = pxa_gpio_to_irq(27), - .end = pxa_gpio_to_irq(27), + .start = mmp_gpio_to_irq(27), + .end = mmp_gpio_to_irq(27), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, } };arch/arm/mach-mmp/flint.c +2
-2@@ -87,8 +87,8 @@ static struct resource smc91x_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = pxa_gpio_to_irq(155), - .end = pxa_gpio_to_irq(155), + .start = mmp_gpio_to_irq(155), + .end = mmp_gpio_to_irq(155), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, } };arch/arm/mach-mmp/gpio.c new file +79
-0@@ -0,0 +1,89 @@ +/* +* linux/arch/arm/mach-mmp/gpio.c +* +* MMP series specific gpio init +* +* Copyright (C) 2011 Marvell International Ltd. +* +* Author: +* Haojian Zhuang <[email protected]> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +*/ + +#include <linux/gpio-pxa.h> +#include <linux/platform_device.h> + +#include <asm/io.h> + +#include <mach/cputype.h> +#include <mach/irqs.h> +#include <mach/regs-apbc.h> + +#define GPIO_REGS_VIRT (APB_VIRT_BASE + 0x19000) +#define APMASK (i) (GPIO_REGS_VIRT + BANK_OFF(i) + 0x09c) + +static struct __initdata pxa_gpio_platform_data mmp_gpio_config; + +static struct __initdata resource mmp_resources_gpio[] = { + { + .start =0xd4010000 , + .end =0xd401ffff , + .flags =IORESOURCE_MEM , + }, { + .start =IRQ_PXA168_GPIOX , + .end =IRQ_PXA168_GPIOX , + .name ="gpio_mux" , + .flags =IORESOURCE_IRQ , + }, +}; + +static struct platform_device mmp_gpio = { + .name ="pxa-gpio" , + .id =-1 , + .num_resources =ARRAY_SIZE (mmp_resources_gpio), + .resource = mmp_resources_gpio, +}; + +static int __init mmp_gpio_init (void ) +{ +int size =sizeof (struct pxa_gpio_platform_data ); +u32 reg_base =GPIO_REGS_VIRT ; +int i; + +if (cpu_is_pxa168 () ||cpu_is_pxa910 ()) { +/* enable GPIO clock */ +__raw_writel (APBC_APBCLK |APBC_FNCLK ,APBC_PXA168_GPIO ); + +/* unmask GPIO edge detection for all 4 banks - APMASKx */ +for (i =0 ; i <4 ; i++) +__raw_writel (0xffffffff ,APMASK (i)); + mmp_gpio_config.gpio_type =MMP_GPIO ; + mmp_gpio_config.gpio_end =127 ; + }else if (cpu_is_mmp2 ()) { +/* enable GPIO clock */ +__raw_writel (APBC_APBCLK |APBC_FNCLK ,APBC_MMP2_GPIO ); + +/* unmask GPIO edge detection for all 6 banks -- APMASKx */ +for (i =0 ; i <6 ; i++) +__raw_writel (0xffffffff ,APMASK (i)); + mmp_gpio_config.gpio_type =MMP2_GPIO ; + mmp_gpio_config.gpio_end =191 ; + }else +return 0 ; + + pxa_gpio_regs.gplr = reg_base +GPLR_OFFSET ; + pxa_gpio_regs.gpdr = reg_base +GPDR_OFFSET ; + pxa_gpio_regs.gpsr = reg_base +GPSR_OFFSET ;
arch/arm/mach-mmp/gpio.c line 89
Quoted 10 lines
arch/arm/mach-mmp/gpio.c new file +10
-0+ pxa_gpio_regs.gpcr = reg_base +GPCR_OFFSET ; + pxa_gpio_regs.grer = reg_base +GRER_OFFSET ; + pxa_gpio_regs.gfer = reg_base +GFER_OFFSET ; + pxa_gpio_regs.gedr = reg_base +GEDR_OFFSET ; + +platform_device_add_data (&mmp_gpio, &mmp_gpio_config, size); +platform_device_register (&mmp_gpio); +return 0 ; +} +postcore_initcall (mmp_gpio_init);
You'll also want to bail on this init function if a DT is passed to the kernel. Otherwise it looks okay.
Quoted 22 lines
arch/arm/mach-mmp/gplugd.c +1
-1@@ -9,11 +9,11 @@*/ #include <linux/init.h> +#include <linux/gpio.h> #include <asm/mach/arch.h> #include <asm/mach-types.h> -#include <mach/gpio.h> #include <mach/pxa168.h> #include <mach/mfp-pxa168.h> arch/arm/mach-mmp/include/mach/gpio.h +0
-0
arch/arm/mach-mmp/include/mach/gpio.h line 7
Quoted 10 lines
arch/arm/mach-mmp/include/mach/gpio.h +1
-5@@ -3,31 +3,9 @@#include <mach/addr-map.h> #include <mach/irqs.h> -#include <asm-generic/gpio.h> -#define GPIO_REGS_VIRT (APB_VIRT_BASE + 0x19000) - -#define BANK_OFF (n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2)) -#define GPIO_REG (x) (*((volatile u32 *)(GPIO_REGS_VIRT + (x)))) +#define GPIO_REGS_VIRT (APB_VIRT_BASE + 0x19000)
Nit: don't change the whitespace on this line because it isn't actually changing functionally, but diff makes it look like it is.
I assume these remaining macros will be removed/reworked in a future patch?
Quoted 260 lines
arch/arm/mach-mmp/include/mach/gpio.h +0
-18#define NR_BUILTIN_GPIO IRQ_GPIO_NUM -#define gpio_to_bank (gpio) ((gpio) >> 5) - -#define __gpio_is_inverted (gpio) (0) -#define __gpio_is_occupied (gpio) (0) - -/* NOTE: these macros are defined here to make optimization of -* gpio_{get,set}_value() to work when 'gpio' is a constant. -* Usage of these macros otherwise is no longer recommended, -* use generic GPIO API whenever possible. -*/ -#define GPIO_bit (gpio) (1 << ((gpio) & 0x1f)) - -#define GPLR (x) GPIO_REG(BANK_OFF(gpio_to_bank(x)) + 0x00) -#define GPDR (x) GPIO_REG(BANK_OFF(gpio_to_bank(x)) + 0x0c) -#define GPSR (x) GPIO_REG(BANK_OFF(gpio_to_bank(x)) + 0x18) -#define GPCR (x) GPIO_REG(BANK_OFF(gpio_to_bank(x)) + 0x24) - -#include <plat/gpio.h> #endif /* __ASM_MACH_GPIO_H */ arch/arm/mach-mmp/include/mach/irqs.h +2
-2@@ -220,8 +220,8 @@#define IRQ_GPIO_START 128#define IRQ_GPIO_NUM 192 -#define pxa_gpio_to_irq (gpio) (IRQ_GPIO_START + (gpio)) -#define pxa_irq_to_gpio (irq) ((irq) - IRQ_GPIO_START) +#define mmp_gpio_to_irq (gpio) (IRQ_GPIO_START + (gpio)) +#define mmp_irq_to_gpio (irq) ((irq) - IRQ_GPIO_START)#define IRQ_BOARD_START (IRQ_GPIO_START + IRQ_GPIO_NUM)arch/arm/mach-mmp/mmp2.c +0
-17@@ -33,8 +33,6 @@#define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000) -#define APMASK (i) (GPIO_REGS_VIRT + BANK_OFF(i) + 0x9c) -static struct mfp_addr_map mmp2_addr_map[]__initdata = {MFP_ADDR_X (GPIO0 ,GPIO58 ,0x54 ),@@ -94,24 +92,9 @@ void mmp2_clear_pmic_int(void)__raw_writel (data, mfpr_pmic); } -static void __init mmp2_init_gpio (void ) -{ -int i; - -/* enable GPIO clock */ -__raw_writel (APBC_APBCLK |APBC_FNCLK ,APBC_MMP2_GPIO ); - -/* unmask GPIO edge detection for all 6 banks -- APMASKx */ -for (i =0 ; i <6 ; i++) -__raw_writel (0xffffffff ,APMASK (i)); - -pxa_init_gpio (IRQ_MMP2_GPIO ,0 ,167 ,NULL ); -} -void __init mmp2_init_irq (void ) {mmp2_init_icu (); -mmp2_init_gpio (); }static void sdhc_clk_enable (struct clk *clk)arch/arm/mach-mmp/pxa168.c +0
-17@@ -43,26 +43,9 @@ static struct mfp_addr_map pxa168_mfp_addr_map[] __initdata = MFP_ADDR_END, }; -#define APMASK (i) (GPIO_REGS_VIRT + BANK_OFF(i) + 0x09c) - -static void __init pxa168_init_gpio (void ) -{ -int i; - -/* enable GPIO clock */ -__raw_writel (APBC_APBCLK |APBC_FNCLK ,APBC_PXA168_GPIO ); - -/* unmask GPIO edge detection for all 4 banks - APMASKx */ -for (i =0 ; i <4 ; i++) -__raw_writel (0xffffffff ,APMASK (i)); - -pxa_init_gpio (IRQ_PXA168_GPIOX ,0 ,127 ,NULL ); -} -void __init pxa168_init_irq (void ) {icu_init_irq (); -pxa168_init_gpio (); }/* APB peripheral clocks */ arch/arm/mach-mmp/pxa910.c +0
-17@@ -77,26 +77,9 @@ static struct mfp_addr_map pxa910_mfp_addr_map[] __initdata = MFP_ADDR_END, }; -#define APMASK (i) (GPIO_REGS_VIRT + BANK_OFF(i) + 0x09c) - -static void __init pxa910_init_gpio (void ) -{ -int i; - -/* enable GPIO clock */ -__raw_writel (APBC_APBCLK |APBC_FNCLK ,APBC_PXA910_GPIO ); - -/* unmask GPIO edge detection for all 4 banks - APMASKx */ -for (i =0 ; i <4 ; i++) -__raw_writel (0xffffffff ,APMASK (i)); - -pxa_init_gpio (IRQ_PXA910_AP_GPIO ,0 ,127 ,NULL ); -} -void __init pxa910_init_irq (void ) {icu_init_irq (); -pxa910_init_gpio (); }/* APB peripheral clocks */ arch/arm/mach-mmp/tavorevb.c +2
-2@@ -70,8 +70,8 @@ static struct resource smc91x_resources[] = { .flags = IORESOURCE_MEM, }, [1] = { - .start = pxa_gpio_to_irq(80), - .end = pxa_gpio_to_irq(80), + .start = mmp_gpio_to_irq(80), + .end = mmp_gpio_to_irq(80), .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, } };arch/arm/mach-mmp/teton_bga.c +1
-1@@ -66,7 +66,7 @@ static struct pxa27x_keypad_platform_data teton_bga_keypad_info __initdata = {static struct i2c_board_info teton_bga_i2c_info[]__initdata = { {I2C_BOARD_INFO ("ds1337" ,0x68 ), - .irq =pxa_gpio_to_irq (RTC_INT_GPIO ) + .irq =mmp_gpio_to_irq (RTC_INT_GPIO ) }, };arch/arm/mach-mmp/ttc_dkb.c +1
-1@@ -136,7 +136,7 @@ static struct i2c_board_info ttc_dkb_i2c_info[] = { { .type = "max7312", .addr = 0x23, - .irq = pxa_gpio_to_irq(80), + .irq = mmp_gpio_to_irq(80), .platform_data = &max7312_data, }, };arch/arm/mach-pxa/Kconfig +6
-0@@ -604,24 +604,28 @@ endmenu config PXA25x bool select CPU_XSCALE + select GPIO_PXA help Select code specific to PXA21x/25x/26x variants config PXA27x bool select CPU_XSCALE + select GPIO_PXA help Select code specific to PXA27x variants config CPU_PXA26x bool select PXA25x + select GPIO_PXA help Select code specific to PXA26x (codename Dalhart) config PXA3xx bool select CPU_XSC3 + select GPIO_PXA help Select code specific to PXA3xx variants@@ -647,6 +651,7 @@ config CPU_PXA320 config CPU_PXA930 bool select PXA3xx + select GPIO_PXA help PXA930 (codename Tavor-P)@@ -659,6 +664,7 @@ config CPU_PXA935 config PXA95x bool select CPU_PJ4 + select GPIO_PXA help Select code specific to PXA95x variantsarch/arm/mach-pxa/Makefile +1
-1@@ -3,7 +3,7 @@ # # Common support (must be linked before board specific support) -obj-y += clock.o devices.o generic.o irq.o \ +obj-y += clock.o devices.o generic.o irq.o gpio.o\ time.o reset.o obj-$(CONFIG_PM) += pm.o sleep.o standby.oarch/arm/mach-pxa/gpio.c new file +14
-0@@ -0,0 +1,92 @@ +/* +* linux/arch/arm/mach-pxa/gpio.c +* +* PXA series specific gpio init +* +* Copyright (C) 2011 Marvell International Ltd. +* +* Author: +* Haojian Zhuang <[email protected]> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +*/
arch/arm/mach-pxa/gpio.c line 24
Quoted 10 lines
arch/arm/mach-pxa/gpio.c new file +10
-0+ +#include <linux/gpio-pxa.h> +#include <linux/platform_device.h> + +#include <mach/hardware.h> +#include <mach/irqs.h> + +static struct __initdata pxa_gpio_platform_data pxa_gpio_config; + +static struct __initdata resource pxa_resources_gpio[] = {
static struct resource pxa_resources_gpio[] __initdata = {
Quoted 32 lines
arch/arm/mach-pxa/gpio.c new file +32
-0+ { + .start = 0x40e00000, + .end = 0x40e0ffff, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_GPIO0, + .end = IRQ_GPIO0, + .name = "gpio0", + .flags = IORESOURCE_IRQ, + }, { + .start = IRQ_GPIO1, + .end = IRQ_GPIO1, + .name = "gpio1", + .flags = IORESOURCE_IRQ, + }, { + .start = IRQ_GPIO_2_x, + .end = IRQ_GPIO_2_x, + .name = "gpio_mux", + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device pxa_gpio = { + .name = "pxa-gpio", + .id = -1, + .num_resources = ARRAY_SIZE(pxa_resources_gpio), + .resource = pxa_resources_gpio, +}; + +static int __init pxa_gpio_init(void) +{ + int size = sizeof(struct pxa_gpio_platform_data);
arch/arm/mach-pxa/gpio.c line 66
Quoted 10 lines
arch/arm/mach-pxa/gpio.c new file +10
-0+u32 reg_base =io_p2v (0x40E00000 ); + +if (cpu_is_pxa25x ()) { +#ifdef CONFIG_PXA26x + pxa_gpio_config.gpio_type =PXA26X_GPIO ; + pxa_gpio_config.gpio_end =89 ; +#else + pxa_gpio_config.gpio_type =PXA25X_GPIO ; + pxa_gpio_config.gpio_end =84 ; +#endif
Not multiplatform friendly. The subarch may not support multiplatform, but that's no excuse for adding either/or #ifdef blocks. I'd rather see one #ifdef for PXA26x and another for PXA25x, and the code organizes so that they can peacefully co-exist.
Quoted 10 lines
arch/arm/mach-pxa/gpio.c new file +10
-0+ }else if (cpu_is_pxa27x ()) { + pxa_gpio_config.gpio_type =PXA27X_GPIO ; + pxa_gpio_config.gpio_end =120 ; + }else if (cpu_is_pxa93x () ||cpu_is_pxa95x ()) { + pxa_gpio_config.gpio_type =PXA93X_GPIO ; + pxa_gpio_config.gpio_end =191 ; + }else if (cpu_is_pxa3xx ()) { + pxa_gpio_config.gpio_type =PXA3XX_GPIO ; + pxa_gpio_config.gpio_end =127 ; + }else
arch/arm/mach-pxa/gpio.c line 86
Quoted 10 lines
arch/arm/mach-pxa/gpio.c new file +10
-0+return 0 ; + + pxa_gpio_regs.gplr = reg_base +GPLR_OFFSET ; + pxa_gpio_regs.gpdr = reg_base +GPDR_OFFSET ; + pxa_gpio_regs.gpsr = reg_base +GPSR_OFFSET ; + pxa_gpio_regs.gpcr = reg_base +GPCR_OFFSET ; + pxa_gpio_regs.grer = reg_base +GRER_OFFSET ; + pxa_gpio_regs.gfer = reg_base +GFER_OFFSET ; + pxa_gpio_regs.gedr = reg_base +GEDR_OFFSET ; + pxa_gpio_regs.gafr = reg_base +GAFR_OFFSET ;
I'd rather have this layout knowledge as part of the driver rather than using platform data to pass stuff. The driver can make the selection either based on device name, or by testing cpio_is_pxa*() directly. We already have the mechanisms needed for this.
Same goes for mmp_gpio_init().
arch/arm/mach-pxa/gpio.c line 92
Quoted 6 lines
arch/arm/mach-pxa/gpio.c new file +6
-0+ +platform_device_add_data (&pxa_gpio, &pxa_gpio_config, size); +platform_device_register (&pxa_gpio); +return 0 ; +} +postcore_initcall (pxa_gpio_init);
Same as mmp_gpio_init, this function needs to be skipped if a DT is passed to the kernel.
Quoted 717 lines
arch/arm/mach-pxa/include/mach/gpio.h +0
-64@@ -25,71 +25,7 @@#define __ASM_ARCH_PXA_GPIO_H#include <mach/irqs.h> -#include <mach/hardware.h> -#include <asm-generic/gpio.h> - -#define GPIO_REGS_VIRT io_p2v(0x40E00000) - -#define BANK_OFF (n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2)) -#define GPIO_REG (x) (*(volatile u32 *)(GPIO_REGS_VIRT + (x))) - -/* More handy macros. The argument is a literal GPIO number. */ - -#define GPIO_bit (x) (1 << ((x) & 0x1f)) - -/* GPIO Pin Level Registers */ -#define GPLR (x) GPIO_REG(BANK_OFF((x) >> 5) + 0x00) -/* GPIO Pin Direction Registers */ -#define GPDR (x) GPIO_REG(BANK_OFF((x) >> 5) + 0x0c) -/* GPIO Pin Output Set Registers */ -#define GPSR (x) GPIO_REG(BANK_OFF((x) >> 5) + 0x18) -/* GPIO Pin Output Clear Registers */ -#define GPCR (x) GPIO_REG(BANK_OFF((x) >> 5) + 0x24) -/* GPIO Rising Edge Detect Registers */ -#define GRER (x) GPIO_REG(BANK_OFF((x) >> 5) + 0x30) -/* GPIO Falling Edge Detect Registers */ -#define GFER (x) GPIO_REG(BANK_OFF((x) >> 5) + 0x3c) -/* GPIO Edge Detect Status Registers */ -#define GEDR (x) GPIO_REG(BANK_OFF((x) >> 5) + 0x48) -/* GPIO Alternate Function Select Registers */ -#define GAFR (x) GPIO_REG(0x54 + (((x) & 0x70) >> 2)) -#define NR_BUILTIN_GPIO PXA_GPIO_IRQ_NUM -#define gpio_to_bank (gpio) ((gpio) >> 5) - -#ifdef CONFIG_CPU_PXA26x -/* GPIO86/87/88/89 on PXA26x have their direction bits in GPDR2 inverted, -* as well as their Alternate Function value being '1' for GPIO in GAFRx. -*/ -static inline int __gpio_is_inverted (unsigned gpio) -{ -return cpu_is_pxa25x () && gpio >85 ; -} -#else -static inline int __gpio_is_inverted (unsigned gpio) {return 0 ; } -#endif - -/* -* On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate -* function of a GPIO, and GPDRx cannot be altered once configured. It -* is attributed as "occupied" here (I know this terminology isn't -* accurate, you are welcome to propose a better one :-) -*/ -static inline int __gpio_is_occupied (unsigned gpio) -{ -if (cpu_is_pxa27x () ||cpu_is_pxa25x ()) { -int af = (GAFR (gpio) >> ((gpio &0xf ) *2 )) &0x3 ; -int dir =GPDR (gpio) &GPIO_bit (gpio); - -if (__gpio_is_inverted (gpio)) -return af !=1 || dir ==0 ; -else -return af !=0 || dir !=0 ; - }else -return GPDR (gpio) &GPIO_bit (gpio); -} - -#include <plat/gpio.h> #endif arch/arm/mach-pxa/pxa25x.c +0
-3@@ -311,14 +311,12 @@ set_pwer:void __init pxa25x_init_irq (void ) {pxa_init_irq (32 , pxa25x_set_wake); -pxa_init_gpio (IRQ_GPIO_2_x,2 ,84 , pxa25x_set_wake); }#ifdef CONFIG_CPU_PXA26xvoid __init pxa26x_init_irq (void ) {pxa_init_irq (32 , pxa25x_set_wake); -pxa_init_gpio (IRQ_GPIO_2_x,2 ,89 , pxa25x_set_wake); }#endif @@ -368,7 +366,6 @@ static int __init pxa25x_init(void)register_syscore_ops (&pxa_irq_syscore_ops);register_syscore_ops (&pxa2xx_mfp_syscore_ops); -register_syscore_ops (&pxa_gpio_syscore_ops);register_syscore_ops (&pxa2xx_clock_syscore_ops); ret = platform_add_devices(pxa25x_devices,arch/arm/mach-pxa/pxa27x.c +0
-2@@ -385,7 +385,6 @@ static int pxa27x_set_wake(struct irq_data *d, unsigned int on)void __init pxa27x_init_irq (void ) {pxa_init_irq (34 , pxa27x_set_wake); -pxa_init_gpio (IRQ_GPIO_2_x,2 ,120 , pxa27x_set_wake); }static struct map_desc pxa27x_io_desc[]__initdata = {@@ -454,7 +453,6 @@ static int __init pxa27x_init(void)register_syscore_ops (&pxa_irq_syscore_ops);register_syscore_ops (&pxa2xx_mfp_syscore_ops); -register_syscore_ops (&pxa_gpio_syscore_ops);register_syscore_ops (&pxa2xx_clock_syscore_ops); ret =platform_add_devices (devices,ARRAY_SIZE (devices));arch/arm/mach-pxa/pxa3xx.c +0
-2@@ -389,7 +389,6 @@ void __init pxa3xx_init_irq(void)pxa_init_irq (56 , pxa3xx_set_wake);pxa_init_ext_wakeup_irq (pxa3xx_set_wake); -pxa_init_gpio (IRQ_GPIO_2_x,2 ,127 ,NULL ); }static struct map_desc pxa3xx_io_desc[]__initdata = {@@ -461,7 +460,6 @@ static int __init pxa3xx_init(void)register_syscore_ops (&pxa_irq_syscore_ops);register_syscore_ops (&pxa3xx_mfp_syscore_ops); -register_syscore_ops (&pxa_gpio_syscore_ops);register_syscore_ops (&pxa3xx_clock_syscore_ops); ret =platform_add_devices (devices,ARRAY_SIZE (devices));arch/arm/mach-pxa/pxa95x.c +0
-2@@ -235,7 +235,6 @@ static struct clk_lookup pxa95x_clkregs[] = {void __init pxa95x_init_irq (void ) {pxa_init_irq (96 ,NULL ); -pxa_init_gpio (IRQ_GPIO_2_x,2 ,127 ,NULL ); }/* @@ -282,7 +281,6 @@ static int __init pxa95x_init(void)return ret;register_syscore_ops (&pxa_irq_syscore_ops); -register_syscore_ops (&pxa_gpio_syscore_ops);register_syscore_ops (&pxa3xx_clock_syscore_ops); ret =platform_add_devices (devices,ARRAY_SIZE (devices));arch/arm/plat-pxa/Makefile +0
-1@@ -4,7 +4,6 @@ obj-y := dma.o -obj-$(CONFIG_GENERIC_GPIO) += gpio.o obj-$(CONFIG_PXA3xx) += mfp.o obj-$(CONFIG_PXA95x) += mfp.o obj-$(CONFIG_ARCH_MMP) += mfp.oarch/arm/plat-pxa/gpio.c deleted +0
-352@@ -1,352 +0,0 @@ -/* -* linux/arch/arm/plat-pxa/gpio.c -* -* Generic PXA GPIO handling -* -* Author: Nicolas Pitre -* Created: Jun 15, 2001 -* Copyright: MontaVista Software Inc. -* -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License version 2 as -* published by the Free Software Foundation. -*/ -#include <linux/gpio.h> -#include <linux/init.h> -#include <linux/irq.h> -#include <linux/io.h> -#include <linux/syscore_ops.h> -#include <linux/slab.h> - -int pxa_last_gpio; - -struct pxa_gpio_chip { -struct gpio_chip chip; -void __iomem *regbase; -char label[10 ]; - -unsigned long irq_mask; -unsigned long irq_edge_rise; -unsigned long irq_edge_fall; - -#ifdef CONFIG_PM -unsigned long saved_gplr; -unsigned long saved_gpdr; -unsigned long saved_grer; -unsigned long saved_gfer; -#endif -}; - -static DEFINE_SPINLOCK (gpio_lock); -static struct pxa_gpio_chip *pxa_gpio_chips; - -#define for_each_gpio_chip (i, c) \ - for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++) - -static inline void __iomem *gpio_chip_base (struct gpio_chip *c) -{ - return container_of(c, struct pxa_gpio_chip, chip)->regbase; -} - -static inline struct pxa_gpio_chip *gpio_to_pxachip (unsigned gpio) -{ -return &pxa_gpio_chips[gpio_to_bank (gpio)]; -} - -static int pxa_gpio_direction_input (struct gpio_chip *chip,unsigned offset) -{ -void __iomem *base =gpio_chip_base (chip); -uint32_t value, mask =1 << offset; -unsigned long flags; - -spin_lock_irqsave (&gpio_lock, flags); - - value =__raw_readl (base +GPDR_OFFSET ); -if (__gpio_is_inverted (chip->base + offset)) - value |= mask; -else - value &= ~mask; -__raw_writel (value, base +GPDR_OFFSET ); - -spin_unlock_irqrestore (&gpio_lock, flags); -return 0 ; -} - -static int pxa_gpio_direction_output (struct gpio_chip *chip, -unsigned offset,int value) -{ -void __iomem *base =gpio_chip_base (chip); -uint32_t tmp, mask =1 << offset; -unsigned long flags; - -__raw_writel (mask, base + (value ?GPSR_OFFSET :GPCR_OFFSET )); - -spin_lock_irqsave (&gpio_lock, flags); - - tmp =__raw_readl (base +GPDR_OFFSET ); -if (__gpio_is_inverted (chip->base + offset)) - tmp &= ~mask; -else - tmp |= mask; -__raw_writel (tmp, base +GPDR_OFFSET ); - -spin_unlock_irqrestore (&gpio_lock, flags); -return 0 ; -} - -static int pxa_gpio_get (struct gpio_chip *chip,unsigned offset) -{ -return __raw_readl (gpio_chip_base (chip) +GPLR_OFFSET ) & (1 << offset); -} - -static void pxa_gpio_set (struct gpio_chip *chip,unsigned offset,int value) -{ -__raw_writel (1 << offset,gpio_chip_base (chip) + - (value ?GPSR_OFFSET :GPCR_OFFSET )); -} - -static int __init pxa_init_gpio_chip (int gpio_end) -{ -int i, gpio, nbanks =gpio_to_bank (gpio_end) +1 ; -struct pxa_gpio_chip *chips; - - chips =kzalloc (nbanks *sizeof (struct pxa_gpio_chip ),GFP_KERNEL ); -if (chips ==NULL ) { -pr_err ("%s: failed to allocate GPIO chips\n" , __func__); -return -ENOMEM ; - } - -for (i =0 , gpio =0 ; i < nbanks; i++, gpio +=32 ) { -struct gpio_chip *c = &chips[i].chip; - -sprintf (chips[i].label,"gpio-%d" , i); - chips[i].regbase = (void __iomem *)GPIO_BANK (i); - - c->base = gpio; - c->label = chips[i].label; - - c->direction_input = pxa_gpio_direction_input; - c->direction_output = pxa_gpio_direction_output; - c->get = pxa_gpio_get; - c->set = pxa_gpio_set; - -/* number of GPIOs on last bank may be less than 32 */ - c->ngpio = (gpio +31 > gpio_end) ? (gpio_end - gpio +1 ) :32 ; -gpiochip_add (c); - } - pxa_gpio_chips = chips; -return 0 ; -} - -/* Update only those GRERx and GFERx edge detection register bits if those -* bits are set in c->irq_mask -*/ -static inline void update_edge_detect (struct pxa_gpio_chip *c) -{ -uint32_t grer, gfer; - - grer =__raw_readl (c->regbase +GRER_OFFSET ) & ~c->irq_mask; - gfer =__raw_readl (c->regbase +GFER_OFFSET ) & ~c->irq_mask; - grer |= c->irq_edge_rise & c->irq_mask; - gfer |= c->irq_edge_fall & c->irq_mask; -__raw_writel (grer, c->regbase +GRER_OFFSET ); -__raw_writel (gfer, c->regbase +GFER_OFFSET ); -} - -static int pxa_gpio_irq_type (struct irq_data *d,unsigned int type) -{ -struct pxa_gpio_chip *c; -int gpio =pxa_irq_to_gpio (d->irq); -unsigned long gpdr, mask =GPIO_bit (gpio); - - c =gpio_to_pxachip (gpio); - -if (type ==IRQ_TYPE_PROBE ) { -/* Don't mess with enabled GPIOs using preconfigured edges or -* GPIOs set to alternate function or to output during probe -*/ -if ((c->irq_edge_rise | c->irq_edge_fall) &GPIO_bit (gpio)) -return 0 ; - -if (__gpio_is_occupied (gpio)) -return 0 ; - - type =IRQ_TYPE_EDGE_RISING |IRQ_TYPE_EDGE_FALLING ; - } - - gpdr =__raw_readl (c->regbase +GPDR_OFFSET ); - -if (__gpio_is_inverted (gpio)) -__raw_writel (gpdr | mask, c->regbase +GPDR_OFFSET ); -else -__raw_writel (gpdr & ~mask, c->regbase +GPDR_OFFSET ); - -if (type &IRQ_TYPE_EDGE_RISING ) - c->irq_edge_rise |= mask; -else - c->irq_edge_rise &= ~mask; - -if (type &IRQ_TYPE_EDGE_FALLING ) - c->irq_edge_fall |= mask; -else - c->irq_edge_fall &= ~mask; - -update_edge_detect (c); - -pr_debug ("%s: IRQ%d (GPIO%d) - edge%s%s\n" , __func__, d->irq, gpio, - ((type &IRQ_TYPE_EDGE_RISING ) ?" rising" :"" ), - ((type &IRQ_TYPE_EDGE_FALLING ) ?" falling" :"" )); -return 0 ; -} - -static void pxa_gpio_demux_handler (unsigned int irq,struct irq_desc *desc) -{ -struct pxa_gpio_chip *c; -int loop, gpio, gpio_base, n; -unsigned long gedr; - -do { - loop =0 ; -for_each_gpio_chip (gpio, c) { - gpio_base = c->chip.base; - - gedr =__raw_readl (c->regbase +GEDR_OFFSET ); - gedr = gedr & c->irq_mask; -__raw_writel (gedr, c->regbase +GEDR_OFFSET ); - - n =find_first_bit (&gedr,BITS_PER_LONG ); -while (n <BITS_PER_LONG ) { - loop =1 ; - -generic_handle_irq (pxa_gpio_to_irq (gpio_base + n)); - n =find_next_bit (&gedr,BITS_PER_LONG , n +1 ); - } - } - }while (loop); -} - -static void pxa_ack_muxed_gpio (struct irq_data *d) -{ -int gpio =pxa_irq_to_gpio (d->irq); -struct pxa_gpio_chip *c =gpio_to_pxachip (gpio); - -__raw_writel (GPIO_bit (gpio), c->regbase +GEDR_OFFSET ); -} - -static void pxa_mask_muxed_gpio (struct irq_data *d) -{ -int gpio =pxa_irq_to_gpio (d->irq); -struct pxa_gpio_chip *c =gpio_to_pxachip (gpio); -uint32_t grer, gfer; - - c->irq_mask &= ~GPIO_bit (gpio); - - grer =__raw_readl (c->regbase +GRER_OFFSET ) & ~GPIO_bit (gpio); - gfer =__raw_readl (c->regbase +GFER_OFFSET ) & ~GPIO_bit (gpio); -__raw_writel (grer, c->regbase +GRER_OFFSET ); -__raw_writel (gfer, c->regbase +GFER_OFFSET ); -} - -static void pxa_unmask_muxed_gpio (struct irq_data *d) -{ -int gpio =pxa_irq_to_gpio (d->irq); -struct pxa_gpio_chip *c =gpio_to_pxachip (gpio); - - c->irq_mask |=GPIO_bit (gpio); -update_edge_detect (c); -} - -static struct irq_chip pxa_muxed_gpio_chip = { - .name ="GPIO" , - .irq_ack = pxa_ack_muxed_gpio, - .irq_mask = pxa_mask_muxed_gpio, - .irq_unmask = pxa_unmask_muxed_gpio, - .irq_set_type = pxa_gpio_irq_type, -}; - -void __init pxa_init_gpio (int mux_irq,int start,int end, -int (*fn)(struct irq_data *,unsigned int )) -{ -struct pxa_gpio_chip *c; -int gpio, irq; - - pxa_last_gpio = end; - -/* Initialize GPIO chips */ -pxa_init_gpio_chip (end); - -/* clear all GPIO edge detects */ -for_each_gpio_chip (gpio, c) { -__raw_writel (0 , c->regbase +GFER_OFFSET ); -__raw_writel (0 , c->regbase +GRER_OFFSET ); -__raw_writel (~0 ,c->regbase +GEDR_OFFSET ); - } - -#ifdef CONFIG_ARCH_PXA - irq =gpio_to_irq (0 ); -irq_set_chip_and_handler (irq, &pxa_muxed_gpio_chip, - handle_edge_irq); -set_irq_flags (irq,IRQF_VALID |IRQF_PROBE ); -irq_set_chained_handler (IRQ_GPIO0 , pxa_gpio_demux_handler); - - irq =gpio_to_irq (1 ); -irq_set_chip_and_handler (irq, &pxa_muxed_gpio_chip, - handle_edge_irq); -set_irq_flags (irq,IRQF_VALID |IRQF_PROBE ); -irq_set_chained_handler (IRQ_GPIO1 , pxa_gpio_demux_handler); -#endif - -for (irq =pxa_gpio_to_irq (start); irq <=pxa_gpio_to_irq (end); - irq++) { -irq_set_chip_and_handler (irq, &pxa_muxed_gpio_chip, - handle_edge_irq); -set_irq_flags (irq,IRQF_VALID |IRQF_PROBE ); - } - -/* Install handler for GPIO>=2 edge detect interrupts */ -irq_set_chained_handler (mux_irq, pxa_gpio_demux_handler); - pxa_muxed_gpio_chip.irq_set_wake = fn; -} - -#ifdef CONFIG_PM -static int pxa_gpio_suspend (void ) -{ -struct pxa_gpio_chip *c; -int gpio; - -for_each_gpio_chip (gpio, c) { - c->saved_gplr =__raw_readl (c->regbase +GPLR_OFFSET ); - c->saved_gpdr =__raw_readl (c->regbase +GPDR_OFFSET ); - c->saved_grer =__raw_readl (c->regbase +GRER_OFFSET ); - c->saved_gfer =__raw_readl (c->regbase +GFER_OFFSET ); - -/* Clear GPIO transition detect bits */ -__raw_writel (0xffffffff , c->regbase +GEDR_OFFSET ); - } -return 0 ; -} - -static void pxa_gpio_resume (void ) -{ -struct pxa_gpio_chip *c; -int gpio; - -for_each_gpio_chip (gpio, c) { -/* restore level with set/clear */ -__raw_writel ( c->saved_gplr, c->regbase +GPSR_OFFSET ); -__raw_writel (~c->saved_gplr, c->regbase +GPCR_OFFSET ); - -__raw_writel (c->saved_grer, c->regbase +GRER_OFFSET ); -__raw_writel (c->saved_gfer, c->regbase +GFER_OFFSET ); -__raw_writel (c->saved_gpdr, c->regbase +GPDR_OFFSET ); - } -} -#else -#define pxa_gpio_suspend NULL -#define pxa_gpio_resume NULL -#endif - -struct syscore_ops pxa_gpio_syscore_ops = { - .suspend = pxa_gpio_suspend, - .resume = pxa_gpio_resume, -};arch/arm/plat-pxa/include/plat/gpio.h deleted +0
-65@@ -1,65 +0,0 @@ -#ifndef __PLAT_GPIO_H -#define __PLAT_GPIO_H - -#define __ARM_GPIOLIB_COMPLEX - -struct irq_data ; - -/* -* We handle the GPIOs by banks, each bank covers up to 32 GPIOs with -* one set of registers. The register offsets are organized below: -* -* GPLR GPDR GPSR GPCR GRER GFER GEDR -* BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048 -* BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C -* BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050 -* -* BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148 -* BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C -* BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150 -* -* NOTE: -* BANK 3 is only available on PXA27x and later processors. -* BANK 4 and 5 are only available on PXA935 -*/ - -#define GPIO_BANK (n) (GPIO_REGS_VIRT + BANK_OFF(n)) - -#define GPLR_OFFSET 0x00 -#define GPDR_OFFSET 0x0C -#define GPSR_OFFSET 0x18 -#define GPCR_OFFSET 0x24 -#define GRER_OFFSET 0x30 -#define GFER_OFFSET 0x3C -#define GEDR_OFFSET 0x48 - -static inline int gpio_get_value (unsigned gpio) -{ -if (__builtin_constant_p (gpio) && (gpio <NR_BUILTIN_GPIO )) -return GPLR (gpio) &GPIO_bit (gpio); -else -return __gpio_get_value (gpio); -} - -static inline void gpio_set_value (unsigned gpio,int value) -{ -if (__builtin_constant_p (gpio) && (gpio <NR_BUILTIN_GPIO )) { -if (value) -GPSR (gpio) =GPIO_bit (gpio); -else -GPCR (gpio) =GPIO_bit (gpio); - }else -__gpio_set_value (gpio, value); -} - -#define gpio_cansleep __gpio_cansleep - -/* NOTE: some PXAs have fewer on-chip GPIOs (like PXA255, with 85). -* Those cases currently cause holes in the GPIO number space, the -* actual number of the last GPIO is recorded by 'pxa_last_gpio'. -*/ -extern int pxa_last_gpio; - -extern void pxa_init_gpio (int mux_irq,int start,int end, -int (*fn)(struct irq_data *,unsigned int )); -#endif /* __PLAT_GPIO_H */ drivers/gpio/Kconfig +6
-0@@ -141,6 +141,12 @@ config GPIO_PL061 help Say yes here to support the PrimeCell PL061 GPIO device +config GPIO_PXA + def_bool y + depends on ARCH_PXA || ARCH_MMP + help + Say yes here to support the PXA GPIO device + config GPIO_XILINX bool "Xilinx GPIO support" depends on PPC_OF || MICROBLAZEdrivers/gpio/Makefile +1
-0@@ -40,6 +40,7 @@ obj-$(CONFIG_GPIO_PCA953X) += gpio-pca953x.o obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf857x.o obj-$(CONFIG_GPIO_PCH) += gpio-pch.o obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o +obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o obj-$(CONFIG_PLAT_SAMSUNG) += gpio-samsung.odrivers/gpio/gpio-pxa.c new file +78
-0@@ -0,0 +1,500 @@ +/* +* linux/arch/arm/plat-pxa/gpio.c +* +* Generic PXA GPIO handling +* +* Author: Nicolas Pitre +* Created: Jun 15, 2001 +* Copyright: MontaVista Software Inc. +* +* Copyright (C) 2011 Marvell Technology +* Moved to drivers/gpio - Haojian Zhuang <[email protected]> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +*/ + +#include <linux/gpio.h> +#include <linux/gpio-pxa.h> +#include <linux/irq.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/syscore_ops.h> + +static int pxa_last_gpio; + +struct pxa_gpio_irq_data { +int gpio_type; +int irq_gpio0; +int irq_gpio1; +int irq_mux; +}; + +struct pxa_gpio_chip { +struct gpio_chip chip; +void __iomem *regbase; +char label[10 ]; + +unsigned long irq_mask; +unsigned long irq_edge_rise; +unsigned long irq_edge_fall; +struct pxa_gpio_irq_data *data; + +#ifdef CONFIG_PM +unsigned long saved_gplr; +unsigned long saved_gpdr; +unsigned long saved_grer; +unsigned long saved_gfer; +#endif +}; + +struct pxa_gpio_regs pxa_gpio_regs; + +static DEFINE_SPINLOCK (gpio_lock); +static struct pxa_gpio_chip *pxa_gpio_chips; + +#define for_each_gpio_chip (i, c) \ + for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++) + +static inline void __iomem *gpio_chip_base (struct gpio_chip *c) +{ + return container_of(c, struct pxa_gpio_chip, chip)->regbase; +} + +static inline struct pxa_gpio_chip *gpio_to_pxachip (unsigned gpio) +{ +return &pxa_gpio_chips[gpio_to_bank (gpio)]; +} + +static int __gpio_is_inverted (int gpio) +{ +struct pxa_gpio_chip *c; +struct pxa_gpio_irq_data *data; + + c =gpio_to_pxachip (gpio); + data = c->data; +#ifdef CONFIG_ARCH_PXA +if (gpio_is_pxa_type (data->gpio_type)) {
drivers/gpio/gpio-pxa.c line 88
Quoted 10 lines
drivers/gpio/gpio-pxa.c new file +10
-0+if (data->gpio_type ==PXA26X_GPIO && gpio >84 ) +return 1 ; +else + return 0; + } +#endif +#ifdef CONFIG_ARCH_MMP +if (gpio_is_mmp_type (data->gpio_type)) +return 0 ; +#endif
Instead of encoding it into pdata, it would be simpler to select the type by assiging an (platform_driver*)->id_table and using the .data member in the table to select the correct initialization data. That means using the name of the device to select the correct initialization.
Quoted 269 lines
drivers/gpio/gpio-pxa.c new file +269
-0+return 0 ; +} + +static int __gpio_is_irq (int gpio) +{ +struct pxa_gpio_chip *c; +struct pxa_gpio_irq_data *data; +int af =0 , dir =0 ; +int ret; + + c =gpio_to_pxachip (gpio); + data = c->data; +switch (data->gpio_type) { +case PXA25X_GPIO : +case PXA26X_GPIO : +case PXA27X_GPIO : + af = (GAFR (gpio) >> ((gpio &0xf ) *2 )) &0x3 ; + dir =GPDR (gpio) &GPIO_bit (gpio); +if ((data->gpio_type ==PXA26X_GPIO ) && (gpio >84 )) + ret = (af !=1 ) || (dir ==0 ); +else + ret = (af !=0 ) || (dir !=0 ); +break ; +default : + ret =GPDR (gpio) &GPIO_bit (gpio); +break ; + } +return ret; +} + +static inline int mgpio_to_irq (int gpio) +{ +struct pxa_gpio_chip *c; +struct pxa_gpio_irq_data *data; + + c =gpio_to_pxachip (gpio); + data = c->data; +#ifdef CONFIG_ARCH_PXA +if (gpio_is_pxa_type (data->gpio_type)) +return pxa_gpio_to_irq (gpio); +#endif +#ifdef CONFIG_ARCH_MMP +if (gpio_is_mmp_type (data->gpio_type)) +return mmp_gpio_to_irq (gpio); +#endif +return 0 ; +} + +static inline int mirq_to_gpio (struct irq_data *d) +{ +struct pxa_gpio_irq_data *data =irq_data_get_irq_chip_data (d); + +#ifdef CONFIG_ARCH_PXA +if (gpio_is_pxa_type (data->gpio_type)) +return pxa_irq_to_gpio (d->irq); +#endif +#ifdef CONFIG_ARCH_MMP +if (gpio_is_mmp_type (data->gpio_type)) +return mmp_irq_to_gpio (d->irq); +#endif +return 0 ; +} + +static int pxa_gpio_direction_input (struct gpio_chip *chip,unsigned offset) +{ +void __iomem *base =gpio_chip_base (chip); +uint32_t value, mask =1 << offset; +unsigned long flags; + +spin_lock_irqsave (&gpio_lock, flags); + + value =__raw_readl (base +GPDR_OFFSET ); +if (__gpio_is_inverted (chip->base + offset)) + value |= mask; +else + value &= ~mask; +__raw_writel (value, base +GPDR_OFFSET ); + +spin_unlock_irqrestore (&gpio_lock, flags); +return 0 ; +} + +static int pxa_gpio_direction_output (struct gpio_chip *chip, +unsigned offset,int value) +{ +void __iomem *base =gpio_chip_base (chip); +uint32_t tmp, mask =1 << offset; +unsigned long flags; + +__raw_writel (mask, base + (value ?GPSR_OFFSET :GPCR_OFFSET )); + +spin_lock_irqsave (&gpio_lock, flags); + + tmp =__raw_readl (base +GPDR_OFFSET ); +if (__gpio_is_inverted (chip->base + offset)) + tmp &= ~mask; +else + tmp |= mask; +__raw_writel (tmp, base +GPDR_OFFSET ); + +spin_unlock_irqrestore (&gpio_lock, flags); +return 0 ; +} + +static int pxa_gpio_get (struct gpio_chip *chip,unsigned offset) +{ +return __raw_readl (gpio_chip_base (chip) +GPLR_OFFSET ) & (1 << offset); +} + +static void pxa_gpio_set (struct gpio_chip *chip,unsigned offset,int value) +{ +__raw_writel (1 << offset,gpio_chip_base (chip) + + (value ?GPSR_OFFSET :GPCR_OFFSET )); +} + +static int __init pxa_init_gpio_chip (int gpio_end, +struct pxa_gpio_irq_data *data) +{ +int i, gpio, nbanks =gpio_to_bank (gpio_end) +1 ; +struct pxa_gpio_chip *chips; + + chips =kzalloc (nbanks *sizeof (struct pxa_gpio_chip ),GFP_KERNEL ); +if (chips ==NULL ) { +pr_err ("%s: failed to allocate GPIO chips\n" , __func__); +return -ENOMEM ; + } + +for (i =0 , gpio =0 ; i < nbanks; i++, gpio +=32 ) { +struct gpio_chip *c = &chips[i].chip; + +sprintf (chips[i].label,"gpio-%d" , i); + chips[i].regbase = (void __iomem *)GPIO_BANK (i); + chips[i].data = data; + + c->base = gpio; + c->label = chips[i].label; + + c->direction_input = pxa_gpio_direction_input; + c->direction_output = pxa_gpio_direction_output; + c->get = pxa_gpio_get; + c->set = pxa_gpio_set; + +/* number of GPIOs on last bank may be less than 32 */ + c->ngpio = (gpio +31 > gpio_end) ? (gpio_end - gpio +1 ) :32 ; +gpiochip_add (c); + } + pxa_gpio_chips = chips; +return 0 ; +} + +/* Update only those GRERx and GFERx edge detection register bits if those +* bits are set in c->irq_mask +*/ +static inline void update_edge_detect (struct pxa_gpio_chip *c) +{ +uint32_t grer, gfer; + + grer =__raw_readl (c->regbase +GRER_OFFSET ) & ~c->irq_mask; + gfer =__raw_readl (c->regbase +GFER_OFFSET ) & ~c->irq_mask; + grer |= c->irq_edge_rise & c->irq_mask; + gfer |= c->irq_edge_fall & c->irq_mask; +__raw_writel (grer, c->regbase +GRER_OFFSET ); +__raw_writel (gfer, c->regbase +GFER_OFFSET ); +} + +static int pxa_gpio_irq_type (struct irq_data *d,unsigned int type) +{ +struct pxa_gpio_chip *c; +int gpio =mirq_to_gpio (d); +unsigned long gpdr, mask =GPIO_bit (gpio); + + c =gpio_to_pxachip (gpio); + +if (type ==IRQ_TYPE_PROBE ) { +/* Don't mess with enabled GPIOs using preconfigured edges or +* GPIOs set to alternate function or to output during probe +*/ +if ((c->irq_edge_rise | c->irq_edge_fall) &GPIO_bit (gpio)) +return 0 ; + +if (!__gpio_is_irq (gpio)) +return 0 ; + + type =IRQ_TYPE_EDGE_RISING |IRQ_TYPE_EDGE_FALLING ; + } + + gpdr =__raw_readl (c->regbase +GPDR_OFFSET ); + +if (__gpio_is_inverted (gpio)) +__raw_writel (gpdr | mask, c->regbase +GPDR_OFFSET ); +else +__raw_writel (gpdr & ~mask, c->regbase +GPDR_OFFSET ); + +if (type &IRQ_TYPE_EDGE_RISING ) + c->irq_edge_rise |= mask; +else + c->irq_edge_rise &= ~mask; + +if (type &IRQ_TYPE_EDGE_FALLING ) + c->irq_edge_fall |= mask; +else + c->irq_edge_fall &= ~mask; + +update_edge_detect (c); + +pr_debug ("%s: IRQ%d (GPIO%d) - edge%s%s\n" , __func__, d->irq, gpio, + ((type &IRQ_TYPE_EDGE_RISING ) ?" rising" :"" ), + ((type &IRQ_TYPE_EDGE_FALLING ) ?" falling" :"" )); +return 0 ; +} + +static void pxa_gpio_demux_handler (unsigned int irq,struct irq_desc *desc) +{ +struct pxa_gpio_chip *c; +int loop, gpio, gpio_base, n; +unsigned long gedr; + +do { + loop =0 ; +for_each_gpio_chip (gpio, c) { + gpio_base = c->chip.base; + + gedr =__raw_readl (c->regbase +GEDR_OFFSET ); + gedr = gedr & c->irq_mask; +__raw_writel (gedr, c->regbase +GEDR_OFFSET ); + + n =find_first_bit (&gedr,BITS_PER_LONG ); +while (n <BITS_PER_LONG ) { + loop =1 ; + + irq =mgpio_to_irq (gpio_base + n); +generic_handle_irq (irq); + n =find_next_bit (&gedr,BITS_PER_LONG , n +1 ); + } + } + }while (loop); +} + +static void pxa_ack_muxed_gpio (struct irq_data *d) +{ +int gpio =mirq_to_gpio (d); +struct pxa_gpio_chip *c =gpio_to_pxachip (gpio); + +__raw_writel (GPIO_bit (gpio), c->regbase +GEDR_OFFSET ); +} + +static void pxa_mask_muxed_gpio (struct irq_data *d) +{ +int gpio =mirq_to_gpio (d); +struct pxa_gpio_chip *c =gpio_to_pxachip (gpio); +uint32_t grer, gfer; + + c->irq_mask &= ~GPIO_bit (gpio); + + grer =__raw_readl (c->regbase +GRER_OFFSET ) & ~GPIO_bit (gpio); + gfer =__raw_readl (c->regbase +GFER_OFFSET ) & ~GPIO_bit (gpio); +__raw_writel (grer, c->regbase +GRER_OFFSET ); +__raw_writel (gfer, c->regbase +GFER_OFFSET ); +} + +static void pxa_unmask_muxed_gpio (struct irq_data *d) +{ +int gpio =mirq_to_gpio (d); +struct pxa_gpio_chip *c =gpio_to_pxachip (gpio); + + c->irq_mask |=GPIO_bit (gpio); +update_edge_detect (c); +} +
drivers/gpio/gpio-pxa.c line 367
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drivers/gpio/gpio-pxa.c new file +10
-0+static struct irq_chip pxa_muxed_gpio_chip = { + .name ="GPIO" , + .irq_ack = pxa_ack_muxed_gpio, + .irq_mask = pxa_mask_muxed_gpio, + .irq_unmask = pxa_unmask_muxed_gpio, + .irq_set_type = pxa_gpio_irq_type, +}; + + +static int __init pxa_gpio_probe (struct platform_device *pdev)
This needs to be __devinit for correctness.
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drivers/gpio/gpio-pxa.c new file +133
-0+{ +struct pxa_gpio_platform_data *pdata; +struct pxa_gpio_chip *c; +struct pxa_gpio_irq_data *mux_data; +int gpio, irq; +int irq0 =0 , irq1 =0 , irq_mux, gpio_offset =0 ; + +if (!pdev->dev.platform_data) +return -EINVAL ; + pdata = pdev->dev.platform_data; + pxa_last_gpio = pdata->gpio_end; + + mux_data =kzalloc (sizeof (struct pxa_gpio_irq_data ),GFP_KERNEL ); +if (mux_data <0 ) +return -ENOMEM ; + + irq0 =platform_get_irq_byname (pdev,"gpio0" ); + irq1 =platform_get_irq_byname (pdev,"gpio1" ); + irq_mux =platform_get_irq_byname (pdev,"gpio_mux" ); +if ((irq0 >0 && irq1 <0 ) || (irq0 <0 && irq1 >0 ) || (irq_mux <0 )) +return -EINVAL ; + +if (irq0 >0 ) { + mux_data->irq_gpio0 = irq0; + mux_data->irq_gpio1 = irq1; + gpio_offset =2 ; + } + mux_data->irq_mux = irq_mux; + mux_data->gpio_type = pdata->gpio_type; + +/* Initialize GPIO chips */ +pxa_init_gpio_chip (pdata->gpio_end, mux_data); + +/* clear all GPIO edge detects */ +for_each_gpio_chip (gpio, c) { +__raw_writel (0 , c->regbase +GFER_OFFSET ); +__raw_writel (0 , c->regbase +GRER_OFFSET ); +__raw_writel (~0 ,c->regbase +GEDR_OFFSET ); + } + +#ifdef CONFIG_ARCH_PXA +if (irq0 >0 ) { + irq =pxa_gpio_to_irq (0 ); +irq_set_chip_data (irq, mux_data); +irq_set_chip_and_handler (irq, &pxa_muxed_gpio_chip, + handle_edge_irq); +set_irq_flags (irq,IRQF_VALID |IRQF_PROBE ); +irq_set_chained_handler (irq0, pxa_gpio_demux_handler); + + irq =pxa_gpio_to_irq (1 ); +irq_set_chip_data (irq, mux_data); +irq_set_chip_and_handler (irq, &pxa_muxed_gpio_chip, + handle_edge_irq); +set_irq_flags (irq,IRQF_VALID |IRQF_PROBE ); +irq_set_chained_handler (irq1, pxa_gpio_demux_handler); + } +#endif /* CONFIG_ARCH_PXA */ + +for (irq =mgpio_to_irq (gpio_offset); + irq <=mgpio_to_irq (pdata->gpio_end); irq++) { +irq_set_chip_data (irq, mux_data); +irq_set_chip_and_handler (irq, &pxa_muxed_gpio_chip, + handle_edge_irq); +set_irq_flags (irq,IRQF_VALID |IRQF_PROBE ); + } + +irq_set_chained_handler (irq_mux, pxa_gpio_demux_handler); +return 0 ; +} + +static struct platform_driver pxa_gpio_driver = { + .probe = pxa_gpio_probe, + .driver = { + .owner =THIS_MODULE , + .name ="pxa-gpio" , + }, +}; + +static int __init pxa_gpio_init (void ) +{ +return platform_driver_register (&pxa_gpio_driver); +} +postcore_initcall (pxa_gpio_init); + +#ifdef CONFIG_PM +static int pxa_gpio_suspend (void ) +{ +struct pxa_gpio_chip *c; +int gpio; + +for_each_gpio_chip (gpio, c) { + c->saved_gplr =__raw_readl (c->regbase +GPLR_OFFSET ); + c->saved_gpdr =__raw_readl (c->regbase +GPDR_OFFSET ); + c->saved_grer =__raw_readl (c->regbase +GRER_OFFSET ); + c->saved_gfer =__raw_readl (c->regbase +GFER_OFFSET ); + +/* Clear GPIO transition detect bits */ +__raw_writel (0xffffffff , c->regbase +GEDR_OFFSET ); + } +return 0 ; +} + +static void pxa_gpio_resume (void ) +{ +struct pxa_gpio_chip *c; +int gpio; + +for_each_gpio_chip (gpio, c) { +/* restore level with set/clear */ +__raw_writel ( c->saved_gplr, c->regbase +GPSR_OFFSET ); +__raw_writel (~c->saved_gplr, c->regbase +GPCR_OFFSET ); + +__raw_writel (c->saved_grer, c->regbase +GRER_OFFSET ); +__raw_writel (c->saved_gfer, c->regbase +GFER_OFFSET ); +__raw_writel (c->saved_gpdr, c->regbase +GPDR_OFFSET ); + } +} +#else +#define pxa_gpio_suspend NULL +#define pxa_gpio_resume NULL +#endif + +struct syscore_ops pxa_gpio_syscore_ops = { + .suspend = pxa_gpio_suspend, + .resume = pxa_gpio_resume, +}; + +static int __init pxa_gpio_sysinit (void ) +{ +register_syscore_ops (&pxa_gpio_syscore_ops); +return 0 ; +} +postcore_initcall (pxa_gpio_sysinit);include/linux/gpio-pxa.h new file +93
-0@@ -0,0 +1,105 @@ +#ifndef __GPIO_PXA_H +#define __GPIO_PXA_H + +#include <asm/io.h> + +/* +* We handle the GPIOs by banks, each bank covers up to 32 GPIOs with +* one set of registers. The register offsets are organized below: +* +* GPLR -- GPIO Pin Level Registers +* GPDR -- GPIO Pin Direction Registers +* GPSR -- GPIO Pin Output Set Registers +* GPCR -- GPIO Pin Output Clear Registers +* GRER -- GPIO Rising Edge Detect Registers +* GFER -- GPIO Falling Edge Detect Registers +* GEDR -- GPIO Edge Detect Status Registers +* +* GPLR GPDR GPSR GPCR GRER GFER GEDR +* BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048 +* BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C +* BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050 +* +* BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148 +* BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C +* BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150 +* +* NOTE: +* BANK 3 is only available on PXA27x and later processors. +* BANK 4 and 5 are only available on PXA935 +*/ + +#define BANK_OFF (n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2)) + +#define gpio_to_bank (x) ((x) >> 5) + +/* More handy macros. The argument is a literal GPIO number. */ + +#define GPIO_bit (x) (1 << ((x) & 0x1f)) + +#define GPLR_OFFSET 0x00 +#define GPDR_OFFSET 0x0C +#define GPSR_OFFSET 0x18 +#define GPCR_OFFSET 0x24 +#define GRER_OFFSET 0x30 +#define GFER_OFFSET 0x3C +#define GEDR_OFFSET 0x48 +#define GAFR_OFFSET 0x54 + +enum { +/* +* Interrupt of GPIO0 & GPIO1 is dependant in PXA series. +* Interrupt of all GPIO is muxed into one in MMP series. +*/ +PXA25X_GPIO =0 , +PXA26X_GPIO , +PXA27X_GPIO , +PXA3XX_GPIO , +PXA93X_GPIO , +MMP_GPIO =0x10 , +MMP2_GPIO , +}; + +#define MASK_GPIO_PXA 0x0f +#define MASK_GPIO_MMP 0xf0 + +struct pxa_gpio_platform_data { +int gpio_end; +int gpio_type; +}; + +static inline int gpio_is_pxa_type (int type) +{ +return type &MASK_GPIO_PXA ; +} + +static inline int gpio_is_mmp_type (int type) +{ +return type &MASK_GPIO_MMP ; +} + +struct pxa_gpio_regs { +u32 gplr; +u32 gpdr; +u32 gpsr; +u32 gpcr; +u32 grer; +u32 gfer; +u32 gedr; +u32 gafr; +}; + +extern struct pxa_gpio_regs pxa_gpio_regs; +
include/linux/gpio-pxa.h line 103
Quoted 10 lines
include/linux/gpio-pxa.h new file +10
-0+#define GPLR (x) (*(volatile u32 *)(pxa_gpio_regs.gplr + BANK_OFF((x >> 5)))) +#define GPDR (x) (*(volatile u32 *)(pxa_gpio_regs.gpdr + BANK_OFF((x >> 5)))) +#define GPSR (x) (*(volatile u32 *)(pxa_gpio_regs.gpsr + BANK_OFF((x >> 5)))) +#define GPCR (x) (*(volatile u32 *)(pxa_gpio_regs.gpcr + BANK_OFF((x >> 5)))) +#define GRER (x) (*(volatile u32 *)(pxa_gpio_regs.grer + BANK_OFF((x >> 5)))) +#define GFER (x) (*(volatile u32 *)(pxa_gpio_regs.gfer + BANK_OFF((x >> 5)))) +#define GEDR (x) (*(volatile u32 *)(pxa_gpio_regs.gedr + BANK_OFF((x >> 5)))) +#define GAFR (x) (*(volatile u32 *)(pxa_gpio_regs.gafr + (((x) & 0x70) >> 2))) + +#define GPIO_BANK (n) (pxa_gpio_regs.gplr + BANK_OFF(n))
All these macros really need a pxa_gpio prefix, but that can be done in a separate patch.
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include/linux/gpio-pxa.h new file +2
-0+ +#endif /* __GPIO_PXA_H */ Signature · 7 lines
1.7.2.5 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel at lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Haojian Zhuang
maintainerPATCH 5/5 ARM: pxa: move gpio driver into drivers directory
Quoted 4 lines · Grant Likely
Quoted 3 lines · Haojian Zhuang
Move gpio driver from plat-pxa to
drivers/gpiodirectory. Only leave gpio number macro inmach/gpio.h.
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arch/arm/mach-mmp/gpio.c line 89
Quoted 10 lines
Signed-off-by Haojian Zhuang <[email protected]>---
arch/arm/mach-mmp/gpio.c new file +8
-0+static int __init mmp_gpio_init (void ) +{ + [...] + ? ? platform_device_add_data(&mmp_gpio, &mmp_gpio_config, size); + ? ? platform_device_register(&mmp_gpio); + ? ? return 0; +} +postcore_initcall (mmp_gpio_init);You'll also want to bail on this init function if a DT is passed to the kernel. ?Otherwise it looks okay.
I can avoid to use this init function. So platform driver will register gpio directly.
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Review
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(quoted diff) +1
-1-#define GPIO_REG(x) ?(*((volatile u32 *)(GPIO_REGS_VIRT + (x)))) +#define GPIO_REGS_VIRT ? ? ? ? ? ? ? (APB_VIRT_BASE + 0x19000)Nit: don't change the whitespace on this line because it isn't actually changing functionally, but diff makes it look like it is.
I assume these remaining macros will be removed/reworked in a future patch?
Do you mean that abandon APB_VIRT_BASE?
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arch/arm/mach-pxa/gpio.c new file +10
-0+static int __init pxa_gpio_init (void ) +{ + ? ? int size = sizeof(struct pxa_gpio_platform_data); + ? ? u32 reg_base = io_p2v(0x40E00000); + + ? ? if (cpu_is_pxa25x()) { +#ifdef CONFIG_PXA26x + ? ? ? ? ? ? pxa_gpio_config.gpio_type = PXA26X_GPIO; + ? ? ? ? ? ? pxa_gpio_config.gpio_end = 89; +#else
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+ ? ? ? ? ? ? pxa_gpio_config.gpio_type =
PXA25X_GPIO;
+ ? ? ? ? ? ? pxa_gpio_config.gpio_end = 84; +#endifNot multiplatform friendly. ?The subarch may not support multiplatform, but that's no excuse for adding either/or #ifdef blocks. ?I'd rather see one #ifdef for PXA26x and another for PXA25x, and the code organizes so that they can peacefully co-exist.
OK.
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+ ? ? } else if (
cpu_is_pxa27x()) {
+ ? ? ? ? ? ? pxa_gpio_config.gpio_type =PXA27X_GPIO;
+ ? ? ? ? ? ? pxa_gpio_config.gpio_end = 120;
+ ? ? } else if (cpu_is_pxa93x()||cpu_is_pxa95x()) {
+ ? ? ? ? ? ? pxa_gpio_config.gpio_type =PXA93X_GPIO;
+ ? ? ? ? ? ? pxa_gpio_config.gpio_end = 191;
+ ? ? } else if (cpu_is_pxa3xx()) {
+ ? ? ? ? ? ? pxa_gpio_config.gpio_type =PXA3XX_GPIO;
+ ? ? ? ? ? ? pxa_gpio_config.gpio_end = 127;
+ ? ? } else
+ ? ? ? ? ? ? return 0;
+Quoted 8 lines
+ ? ? pxa_gpio_regs.gplr =
reg_base+GPLR_OFFSET;
+ ? ? pxa_gpio_regs.gpdr =reg_base+GPDR_OFFSET;
+ ? ? pxa_gpio_regs.gpsr =reg_base+GPSR_OFFSET;
+ ? ? pxa_gpio_regs.gpcr =reg_base+GPCR_OFFSET;
+ ? ? pxa_gpio_regs.grer =reg_base+GRER_OFFSET;
+ ? ? pxa_gpio_regs.gfer =reg_base+GFER_OFFSET;
+ ? ? pxa_gpio_regs.gedr =reg_base+GEDR_OFFSET;
+ ? ? pxa_gpio_regs.gafr =reg_base+GAFR_OFFSET;
Quoted 8 lines
I'd rather have this layout knowledge as part of the driver rather than using platform data to pass stuff. ?The driver can make the selection either based on device name, or by testing cpio_is_pxa*() directly. ?We already have the mechanisms needed for this.
Same goes for
mmp_gpio_init().
OK. I'll move these code into drivers/gpio/gpio-pxa.c.
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arch/arm/mach-pxa/gpio.c line 92
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arch/arm/mach-pxa/gpio.c new file +6
-0+ + ? ? platform_device_add_data(&pxa_gpio, &pxa_gpio_config, size); + ? ? platform_device_register(&pxa_gpio); + ? ? return 0; +} +postcore_initcall (pxa_gpio_init);Same as
mmp_gpio_init, this function needs to be skipped if a DT is passed to the kernel.
OK
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(quoted diff) +0
-1@@ -282,7 +281,6 @@ static int __init pxa95x_init(void) ? ? ? ? ? ? ? ? ? ? ? return ret; ? ? ? ? ? ? ? register_syscore_ops(&pxa_irq_syscore_ops); - ? ? ? ? ? ? register_syscore_ops(&pxa_gpio_syscore_ops); ? ? ? ? ? ? ? register_syscore_ops(&pxa3xx_clock_syscore_ops);
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Review static int __init pxa95x_init(void) · line 286
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(quoted diff) +0
-0? ? ? ? ? ? ? ret = platform_add_devices(devices, ARRAY_SIZE(devices));Instead of encoding it into pdata, it would be simpler to select the type by assiging an (platform_driver*)->id_table and using the .data member in the table to select the correct initialization data. ?That means using the name of the device to select the correct initialization.
Yes, you're right. I'll change it to id_table.
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drivers/gpio/gpio-pxa.c line 367
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drivers/gpio/gpio-pxa.c new file +2
-0+ +static int __init pxa_gpio_probe (struct platform_device *pdev)This needs to be
__devinitfor correctness.
OK
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Review
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(quoted diff) +10
-0+#define GPLR(x) ? ? ? ? ? ? ?(*(volatile u32 *)(pxa_gpio_regs.gplr + BANK_OFF((x >> 5)))) +#define GPDR(x) ? ? ? ? ? ? ?(*(volatile u32 *)(pxa_gpio_regs.gpdr + BANK_OFF((x >> 5)))) +#define GPSR(x) ? ? ? ? ? ? ?(*(volatile u32 *)(pxa_gpio_regs.gpsr + BANK_OFF((x >> 5)))) +#define GPCR(x) ? ? ? ? ? ? ?(*(volatile u32 *)(pxa_gpio_regs.gpcr + BANK_OFF((x >> 5)))) +#define GRER(x) ? ? ? ? ? ? ?(*(volatile u32 *)(pxa_gpio_regs.grer + BANK_OFF((x >> 5)))) +#define GFER(x) ? ? ? ? ? ? ?(*(volatile u32 *)(pxa_gpio_regs.gfer + BANK_OFF((x >> 5)))) +#define GEDR(x) ? ? ? ? ? ? ?(*(volatile u32 *)(pxa_gpio_regs.gedr + BANK_OFF((x >> 5)))) +#define GAFR(x) ? ? ? ? ? ? ?(*(volatile u32 *)(pxa_gpio_regs.gafr + (((x) & 0x70) >> 2))) + +#define GPIO_BANK(n) (pxa_gpio_regs.gplr + BANK_OFF(n))All these macros really need a
pxa_gpioprefix, but that can be done in a separate patch.
OK