x86/cpu changes for v3.2
Subsystems (4)
Linus,
Please pull the latest x86-cpu-for-linus git tree from:
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86-cpu-for-linus
Please have a good look at:
dfb09f9b7ab0: x86, amd: Avoid cache aliasing penalties on AMD family 15h
As it changes the MM allocation layout in a CPU family dependent fashion.
Thanks,
Ingo
------------------>
Borislav Petkov (4):
x86, amd: Avoid cache aliasing penalties on AMD family 15h
x86: Add a BSP cpu_dev helper
x86, amd: Move BSP code to cpu_dev helper
x86-32, amd: Move va_align definition to unbreak 32-bit build
Frank Arnold (1):
x86: cache_info: Update calculation of AMD L3 cache indices
H. Peter Anvin (1):
x86, msr: Fix typo in ENERGY_PERF_BIAS_POWERSAVE
Len Brown (2):
x86, intel, power: Initialize MSR_IA32_ENERGY_PERF_BIAS x86, intel, power: Correct the MSR_IA32_ENERGY_PERF_BIAS message
Stephen Rothwell (2):
x86, amd: Include elf.h explicitly, prepare the code for the module.h split x86, amd: Include linux/elf.h since we use stuff from asm/elf.h
Thomas Gleixner (3):
x86: cache_info: Remove bogus free of amd_l3_cache data
x86: cache_info: Kill the moronic shadow struct
x86: cache_info: Kill the atomic allocation in amd_init_l3_cache()
Documentation/kernel-parameters.txt | 13 ++++ arch/x86/include/asm/amd_nb.h | 6 ++ arch/x86/include/asm/elf.h | 31 ++++++++ arch/x86/include/asm/msr-index.h | 3 + arch/x86/kernel/cpu/amd.c | 47 ++++++++----- arch/x86/kernel/cpu/common.c | 3 + arch/x86/kernel/cpu/cpu.h | 1 + arch/x86/kernel/cpu/intel.c | 18 +++++ arch/x86/kernel/cpu/intel_cacheinfo.c | 127 ++++++++++++--------------------- arch/x86/kernel/sys_x86_64.c | 78 +++++++++++++++++++- arch/x86/mm/mmap.c | 20 +---- arch/x86/vdso/vma.c | 9 +++ 12 files changed, 240 insertions(+), 116 deletions(-)
Documentation/kernel-parameters.txt +13 -0
@@ -299,6 +299,19 @@ bytes respectively. Such letter suffixes can also be entirely omitted. behaviour to be specified. Bit 0 enables warnings, bit 1 enables fixups, and bit 2 sends a segfault. + align_va_addr= [X86-64] + Align virtual addresses by clearing slice [14:12] when + allocating a VMA at process creation time. This option + gives you up to 3% performance improvement on AMD F15h + machines (where it is enabled by default) for a + CPU-intensive style benchmark, and it can vary highly in + a microbenchmark depending on workload and compiler. + + 1: only for 32-bit processes + 2: only for 64-bit processes + on: enable for both 32- and 64-bit processes + off: disable for both 32- and 64-bit processes + amd_iommu= [HW,X86-84] Pass parameters to the AMD IOMMU driver in the system. Possible values are:
arch/x86/include/asm/amd_nb.h +6 -0
@@ -19,9 +19,15 @@ extern int amd_numa_init(void);extern int amd_get_subcaches (int );extern int amd_set_subcaches (int ,int ); +struct amd_l3_cache { +unsigned indices; +u8 subcaches[4 ]; +}; +struct amd_northbridge {struct pci_dev *misc;struct pci_dev *link; +struct amd_l3_cache l3_cache; };struct amd_northbridge_info {
arch/x86/include/asm/elf.h +31 -0
@@ -4,6 +4,7 @@/* * ELF register definitions.. */ +#include <linux/thread_info.h> #include <asm/ptrace.h> #include <asm/user.h>
@@ -320,4 +321,34 @@ extern int syscall32_setup_pages(struct linux_binprm *, int exstack);extern unsigned long arch_randomize_brk (struct mm_struct *mm);#define arch_randomize_brk arch_randomize_brk +/* +* True on X86_32 or when emulating IA32 on X86_64 +*/ +static inline int mmap_is_ia32 (void ) +{ +#ifdef CONFIG_X86_32 +return 1 ; +#endif +#ifdef CONFIG_IA32_EMULATION +if (test_thread_flag (TIF_IA32 )) +return 1 ; +#endif +return 0 ; +} + +/* The first two values are special, do not change. See align_addr() */ +enum align_flags { +ALIGN_VA_32 =BIT (0 ), +ALIGN_VA_64 =BIT (1 ), +ALIGN_VDSO =BIT (2 ), +ALIGN_TOPDOWN =BIT (3 ), +}; + +struct va_alignment { +int flags; +unsigned long mask; +}____cacheline_aligned ; + +extern struct va_alignment va_align; +extern unsigned long align_addr (unsigned long ,struct file *,enum align_flags );#endif /* _ASM_X86_ELF_H */
arch/x86/include/asm/msr-index.h +3 -0
@@ -259,6 +259,9 @@#define MSR_IA32_TEMPERATURE_TARGET 0x000001a2#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 +#define ENERGY_PERF_BIAS_PERFORMANCE 0 +#define ENERGY_PERF_BIAS_NORMAL 6 +#define ENERGY_PERF_BIAS_POWERSAVE 15#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1
arch/x86/kernel/cpu/amd.c +30 -17
70 lines not on this page · raw message
arch/x86/kernel/cpu/common.c +3 -0
@@ -681,6 +681,9 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c)filter_cpuid_features (c, false);setup_smep (c); + +if (this_cpu->c_bsp_init) + this_cpu->c_bsp_init (c); }void __init early_cpu_init (void )
arch/x86/kernel/cpu/cpu.h +1 -0
@@ -18,6 +18,7 @@ struct cpu_dev {struct cpu_model_info c_models[4 ];void (*c_early_init)(struct cpuinfo_x86 *); +void (*c_bsp_init)(struct cpuinfo_x86 *);void (*c_init)(struct cpuinfo_x86 *);void (*c_identify)(struct cpuinfo_x86 *);unsigned int (*c_size_cache)(struct cpuinfo_x86 *,unsigned int );
arch/x86/kernel/cpu/intel.c +18 -0
@@ -456,6 +456,24 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)if (cpu_has (c,X86_FEATURE_VMX ))detect_vmx_virtcap (c); + +/* +* Initialize MSR_IA32_ENERGY_PERF_BIAS if BIOS did not. +* x86_energy_perf_policy(8) is available to change it at run-time +*/ +if (cpu_has (c,X86_FEATURE_EPB )) { +u64 epb; + +rdmsrl (MSR_IA32_ENERGY_PERF_BIAS , epb); +if ((epb &0xF ) ==ENERGY_PERF_BIAS_PERFORMANCE ) { +printk_once (KERN_WARNING "ENERGY_PERF_BIAS:" +" Set to 'normal', was 'performance'\n" +"ENERGY_PERF_BIAS: View and update with" +" x86_energy_perf_policy(8)\n" ); + epb = (epb & ~0xF ) |ENERGY_PERF_BIAS_NORMAL ; +wrmsrl (MSR_IA32_ENERGY_PERF_BIAS , epb); + } + } }#ifdef CONFIG_X86_32
arch/x86/kernel/cpu/intel_cacheinfo.c +47 -80
289 lines not on this page · raw message
arch/x86/kernel/sys_x86_64.c +75 -3
113 lines not on this page · raw message
arch/x86/mm/mmap.c +4 -16
@@ -31,6 +31,10 @@#include <linux/sched.h> #include <asm/elf.h> +struct __read_mostly va_alignment va_align = { + .flags =-1 , +}; +static unsigned int stack_maxrandom_size (void ) {unsigned int max =0 ;
@@ -42,7 +46,6 @@ static unsigned int stack_maxrandom_size(void)return max; } -/* * Top of mmap area (just below the process stack). *
@@ -51,21 +54,6 @@ static unsigned int stack_maxrandom_size(void)#define MIN_GAP (128*1024*1024UL + stack_maxrandom_size())#define MAX_GAP (TASK_SIZE/6*5) -/* -* True on X86_32 or when emulating IA32 on X86_64 -*/ -static int mmap_is_ia32 (void ) -{ -#ifdef CONFIG_X86_32 -return 1 ; -#endif -#ifdef CONFIG_IA32_EMULATION -if (test_thread_flag (TIF_IA32 )) -return 1 ; -#endif -return 0 ; -} -static int mmap_is_legacy (void ) {if (current->personality &ADDR_COMPAT_LAYOUT )
arch/x86/vdso/vma.c +9 -0
@@ -69,6 +69,15 @@ static unsigned long vdso_addr(unsigned long start, unsigned len) addr = start + (offset <<PAGE_SHIFT );if (addr >= end) addr = end; + +/* +* page-align it here so that get_unmapped_area doesn't +* align it wrongfully again to the next page. addr can come in 4K +* unaligned here as a result of stack start randomization. +*/ + addr =PAGE_ALIGN (addr); + addr =align_addr (addr,NULL ,ALIGN_VDSO ); +return addr; }