x86/mce changes for v3.5
Linus,
Please pull the latest x86-mce-for-linus git tree from:
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86-mce-for-linus
HEAD: 239e7bad43dadc43ccf4bbf51f798189fd2cc120 Merge tag 'amd-thresholding-fixes-for-3.5' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras into x86/mce
This tree updates/fixes MCE hardware support, it makes the APIC LVT thresholding interrupt optional because a subset of AMD F15h models don't support it.
Thanks,
Ingo
------------------>
Borislav Petkov (3):
x86, MCE, AMD: Make APIC LVT thresholding interrupt optional x86, MCE, AMD: Hide interrupt_enable sysfs node
x86, MCE, AMD: Disable error thresholding bank 4 on some models
arch/x86/kernel/cpu/mcheck/mce.c | 37 ++++++++++++++++++++ arch/x86/kernel/cpu/mcheck/mce_amd.c | 65 ++++++++++++++++++++++++++++-------- 2 files changed, 88 insertions(+), 14 deletions(-)
arch/x86/kernel/cpu/mcheck/mce.c +37 -0
@@ -1423,6 +1423,43 @@ static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)*/ if (c->x86 ==6 && banks >0 ) mce_banks[0 ].ctl =0 ; + +/* +* Turn off MC4_MISC thresholding banks on those models since +* they're not supported there. +*/ +if (c->x86 ==0x15 && + (c->x86_model >=0x10 && c->x86_model <=0x1f )) { +int i; +u64 val, hwcr; +bool need_toggle; +u32 msrs[] = { +0x00000413 ,/* MC4_MISC0 */ +0xc0000408 ,/* MC4_MISC1 */ + }; + +rdmsrl (MSR_K7_HWCR , hwcr); + +/* McStatusWrEn has to be set */ + need_toggle = !(hwcr &BIT (18 )); + +if (need_toggle) +wrmsrl (MSR_K7_HWCR , hwcr |BIT (18 )); + +for (i =0 ; i <ARRAY_SIZE (msrs); i++) { +rdmsrl (msrs[i], val); + +/* CntP bit set? */ +if (val &BIT (62 )) { + val &= ~BIT (62 ); +wrmsrl (msrs[i], val); + } + } + +/* restore old settings */ +if (need_toggle) +wrmsrl (MSR_K7_HWCR , hwcr); + } }if (c->x86_vendor ==X86_VENDOR_INTEL ) {
arch/x86/kernel/cpu/mcheck/mce_amd.c +51 -14
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