select GENERIC_ATOMIC64 for c6x/score/unicore32 archs

PATCH In review Fengguang Wu 3 participants 8 messages Aug 14, 2012 – Aug 15, 2012

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Fengguang Wu

author

2012-08-14 15:34 UTC #0 lore raw

PATCH 1/1 select GENERIC_ATOMIC64 for c6x/score/unicore32 archs

Sorry I have no compilers for build testing these changes, however the risk looks low and it's much better than to leave the arch broken, considering that Eric will do atomic64_t in the core fs/namespace.c code.

CC "Eric W. Biederman" <[email protected]>

Signed-off-by Fengguang Wu <[email protected]>

---

Andrew: the arch maintainers have been CCed. Best is the maintainers respond, test and perhaps take the corresponding change. Let's see how this will work out..

 arch/c6x/Kconfig       |    1 +
 arch/score/Kconfig     |    1 +
 arch/unicore32/Kconfig |    1 +
 3 files changed, 3 insertions(+)

arch/c6x/Kconfig +1 -0

@@ -16,6 +16,7 @@ config C6X
 	select OF
 	select OF_EARLY_FLATTREE
 	select GENERIC_CLOCKEVENTS
+	select GENERIC_ATOMIC64
 
 config MMU
 	def_bool n

arch/score/Kconfig +1 -0

@@ -10,6 +10,7 @@ config SCORE
        select ARCH_DISCARD_MEMBLOCK
        select GENERIC_CPU_DEVICES
        select GENERIC_CLOCKEVENTS
+       select GENERIC_ATOMIC64
 
 choice
 	prompt "System type"

arch/unicore32/Kconfig +1 -0

@@ -14,6 +14,7 @@ config UNICORE32
 	select GENERIC_IRQ_SHOW
 	select ARCH_WANT_FRAME_POINTERS
 	select GENERIC_IOMAP
+	select GENERIC_ATOMIC64
 	help
 	  UniCore-32 is 32-bit Instruction Set Architecture,
 	  including a series of low-power-consumption RISC chip

Mark Salter

2012-08-14 16:23 UTC #1 lore raw

Quoted 7 lines · Fengguang Wu

Sorry I have no compilers for build testing these changes, however the risk looks low and it's much better than to leave the arch broken, considering that Eric will do atomic64_t in the core fs/namespace.c code.
CC "Eric W. Biederman" <[email protected]>
Signed-off-by Fengguang Wu <[email protected]>

Quoted 8 lines

---
Andrew: the arch maintainers have been CCed. Best is the maintainers respond, test and perhaps take the corresponding change. Let's see how this will work out..
 arch/c6x/Kconfig       |    1 +

The c6x port also needs this:

C6X: add L*_CACHE_SHIFT defines

C6X currently lacks L*_CACHE_SHIFT defines which are used in a few places in the generic kernel. This patch adds those missing defines.

Signed-off-by Mark Salter <[email protected]>

---

arch/c6x/include/asm/cache.h +11 -5

index 6d521d9..feff1d7 100644
@@ -1,7 +1,7 @@
 /*
  *  Port on Texas Instruments TMS320C6x architecture
  *
- *  Copyright (C) 2005, 2006, 2009, 2010 Texas Instruments Incorporated
+ *  Copyright (C) 2005, 2006, 2009, 2010, 2012 Texas Instruments Incorporated
  *  Author: Aurelien Jacquiot ([email protected])
  *
  *  This program is free software; you can redistribute it and/or modify

@@ -16,9 +16,14 @@
 /*
  * Cache line size
  */
-#define L1D_CACHE_BYTES   64
-#define L1P_CACHE_BYTES   32
-#define L2_CACHE_BYTES   128
+#define L1D_CACHE_SHIFT   6
+#define L1D_CACHE_BYTES   (1 << L1D_CACHE_SHIFT)
+
+#define L1P_CACHE_SHIFT   5
+#define L1P_CACHE_BYTES   (1 << L1P_CACHE_SHIFT)
+
+#define L2_CACHE_SHIFT    7
+#define L2_CACHE_BYTES    (1 << L2_CACHE_SHIFT)
 
 /*
  * L2 used as cache

@@ -29,7 +34,8 @@
  * For practical reasons the L1_CACHE_BYTES defines should not be smaller than
  * the L2 line size
  */
-#define L1_CACHE_BYTES        L2_CACHE_BYTES
+#define L1_CACHE_SHIFT        L2_CACHE_SHIFT
+#define L1_CACHE_BYTES        (1 << L2_CACHE_SHIFT)
 
 #define L2_CACHE_ALIGN_LOW(x) \
        (((x) & ~(L2_CACHE_BYTES - 1)))

Fengguang Wu

author

2012-08-15 02:30 UTC #2 lore raw

Quoted 17 lines · Mark Salter

Quoted 7 lines · Fengguang Wu
Sorry I have no compilers for build testing these changes, however the risk looks low and it's much better than to leave the arch broken, considering that Eric will do atomic64_t in the core fs/namespace.c code.
CC "Eric W. Biederman" <[email protected]>
Signed-off-by Fengguang Wu <[email protected]>
Quoted 8 lines
---
Andrew: the arch maintainers have been CCed. Best is the maintainers respond, test and perhaps take the corresponding change. Let's see how this will work out..
 arch/c6x/Kconfig       |    1 +

Quoted 8 lines

The c6x port also needs this:
C6X: add L*_CACHE_SHIFT defines
C6X currently lacks L*_CACHE_SHIFT defines which are used in a few places in the generic kernel. This patch adds those missing defines.
Signed-off-by Mark Salter <[email protected]>

Thanks for the quick fix! git grep shows this:

        lib/atomic64.c: addr >>= L1_CACHE_SHIFT;

So this patch is a prerequisite for the GENERIC_ATOMIC64 patch.

git grep also shows

arch/score/include/asm/cache.h:#define L1_CACHE_SHIFT 4

arch/unicore32/include/asm/cache.h:#define L1_CACHE_SHIFT (5)

So the other two archs are fine.

Thanks,
Fengguang

Fengguang Wu

author Reviewed-by

2012-08-15 02:36 UTC #3 lore raw

In reply to Mark Salter

arch/c6x/include/asm/cache.h line 38

Quoted 3 lines

arch/c6x/include/asm/cache.h +2 -1

-#define L1_CACHE_BYTES        L2_CACHE_BYTES
+#define L1_CACHE_SHIFT        L2_CACHE_SHIFT
+#define L1_CACHE_BYTES        (1 << L2_CACHE_SHIFT)

Nitpick: the last line could better be:

+#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)

Reviewed-by Fengguang Wu <[email protected]>

Thanks!

[email protected]

2012-08-15 05:43 UTC #7 lore raw

In reply to Fengguang Wu

Quoted 6 lines

Sorry I have no compilers for build testing these changes, however the risk looks low and it's much better than to leave the arch broken, considering that Eric will do atomic64_t in the core fs/namespace.c code.
CC "Eric W. Biederman" <[email protected]>
Signed-off-by Fengguang Wu <[email protected]>

It looks ok for unicore32.

Signed-off-by Guan Xuetao <[email protected]>

Mark Salter

2012-08-15 13:43 UTC #4 lore raw

In reply to Fengguang Wu

Quoted 9 lines · Fengguang Wu

arch/c6x/include/asm/cache.h line 38
Quoted 3 lines
arch/c6x/include/asm/cache.h +2 -1
-#define L1_CACHE_BYTES        L2_CACHE_BYTES
+#define L1_CACHE_SHIFT        L2_CACHE_SHIFT
+#define L1_CACHE_BYTES        (1 << L2_CACHE_SHIFT)
Nitpick: the last line could better be:
+#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
Reviewed-by Fengguang Wu <[email protected]>

Yes, I noticed that after sending the patch.

Should I push this through the c6x tree?

--Mark

Fengguang Wu

author

2012-08-15 14:13 UTC #5 lore raw

Quoted 7 lines · Mark Salter

Quoted 6 lines · Fengguang Wu
arch/c6x/include/asm/cache.h line 38
Quoted 3 lines
arch/c6x/include/asm/cache.h +2 -1
-#define L1_CACHE_BYTES        L2_CACHE_BYTES
+#define L1_CACHE_SHIFT        L2_CACHE_SHIFT
+#define L1_CACHE_BYTES        (1 << L2_CACHE_SHIFT)
Nitpick: the last line could better be:

Quoted 7 lines

Quoted 3 lines
+#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
Reviewed-by Fengguang Wu <[email protected]>
Yes, I noticed that after sending the patch.
Should I push this through the c6x tree?

That'd be good. For consistency, will you also include the GENERIC_ATOMIC64 chunk in the titled patch?

I can send Andrew an updated series (reducing the c6x changes, and possibly the score/unicore32 bits) later on.

Thanks,
Fengguang

Mark Salter

2012-08-15 14:19 UTC #6 lore raw

Quoted 7 lines · Fengguang Wu

Quoted 1 line
Should I push this through the c6x tree?
That'd be good. For consistency, will you also include the GENERIC_ATOMIC64 chunk in the titled patch?
I can send Andrew an updated series (reducing the c6x changes, and possibly the score/unicore32 bits) later on.

Ok. Will do.